May 2008 FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Features ! 7.1A, 20V tmM General Description rDS(ON) =0.020Ω, VGS = 4.5V This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain low gate charge for superior switching performance. These devices are well suited for portable electronics applications. rDS(ON) =0.025Ω, VGS = 2.5V ! Extended VGS range (±12 V) for battery applications ! HBM ESD Protection Level of 3.5kV Typical (note 3) ! High performance trench technology for extremely low rDS(ON) ! Low profile TSSOP-8 package Applications ! Load switch ! Battery charge ! Battery disconnect circuits D1 G2 S2 S2 D2 G1 S1 S1 D1 TSSOP-8 FDW2511NZ Rev. A1 G1 Pin 1 ©2008 Fairchild Semiconductor Corporation D2 G2 S1 1 S2 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET D Symbol VDSS Drain to Source Voltage Ratings 20 Units V VGS Gate to Source Voltage ±12 V Drain Current Continuous (TC = 25oC, VGS = 4.5V, RθJA = 77oC/W) Continuous (TC = 100oC, VGS = 2.5V, RθJA = 77oC/W) 7.1 A 4.0 A ID Parameter Figure 4 A PD Power dissipation Pulsed 1.6 W Derate above 25°C 13 mW/oC TJ, TSTG Operating and Storage Temperature o -55 to 150 C Thermal Characteristics RθJA Thermal Resistance Junction to Ambient (Note 1) 77 RθJA Thermal Resistance Junction to Ambient (Note 2) 114 o C/W oC/W Package Marking and Ordering Information Device Marking 2511NZ Device FDW2511NZ Package TSSOP-8 Reel Size 13” Tape Width 12 mm Quantity 2500 units 2 Electrical Characteristics TA = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units 20 - - - V - 1 - - 5 µA - - Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250µA, VGS = 0V VDS = 16V TA=100oC VGS = 0V VGS = ±12V VGS = ±4.5V ±10 µA ±250 nA On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250µA 0.6 0.8 1.5 V ID = 7.1A, VGS = 4.5V - 0.015 0.020 Ω ID = 6.9A, VGS = 4.0V - 0.015 0.021 Ω ID = 6.5A, VGS = 3.1V - 0.016 0.024 Ω ID = 6.3A, VGS = 2.5V - 0.017 0.025 Ω - 1000 - pF - 250 - pF - 175 - pF Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG Gate Resistance VGS = 0.5V, f = 1MHz - 2.8 - Ω Qg(TOT) Total Gate Charge at 4.5V VGS = 0V to 4.5V - 11.5 17.3 nC Qg(2.5) Total Gate Charge at 2.5V VGS = 0V to 2.5V - 7.6 11.4 nC Qgs Gate to Source Gate Charge - 1.7 - nC Qgd Gate to Drain “Miller” Charge - 3.5 - nC FDW2511NZ Rev. A1 VDS = 10V, VGS = 0V, f = 1MHz 2 VDD = 10V ID = 7.1A Ig = 1.0mA www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Absolute Maximum Ratings TA=25°C unless otherwise noted (VGS = 4.5V) tON Turn-On Time - - 146 ns td(ON) Turn-On Delay Time - 13 - ns tr Rise Time td(OFF) Turn-Off Delay Time tf tOFF - 84 - ns - 41 - ns Fall Time - 55 - ns Turn-Off Time - - 144 ns VDD = 10V, ID = 7.1A VGS = 4.5V, RGS = 6.8Ω Drain-Source Diode Characteristics VSD Source to Drain Diode Voltage ISD = 1.3A - 0.7 1.2 V trr Reverse Recovery Time ISD = 7.1A, dISD/dt = 100A/µs - - 27 ns QRR Reverse Recovered Charge ISD = 7.1A, dISD/dt = 100A/µs - - 16 nC Notes: 1. RθJA is 77 oC/W (steady state) when mounted on a 1 inch2 copper pad on FR-4. 2. RθJA is 114 oC/W (steady state) when mounted on a mininum copper pad on FR-4. 3 The diode connected to the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 4 FDW2511NZ Rev. A1 3 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Switching Characteristics TA = 25°C unless otherwise noted 8 1.2 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 6 VGS = 4.5V 4 VGS = 2.5V 2 0.2 0 0 0 25 50 75 100 125 150 25 50 TA , AMBIENT TEMPERATURE (oC) 75 100 125 150 TA, AMBIENT TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Ambient Temperature 2 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 ZθJA, NORMALIZED THERMAL IMPEDANCE 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA 0.01 10-5 10-4 10-3 10-2 10-1 100 101 102 103 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 400 TA = 25oC IDM, PEAK CURRENT (A) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 100 I = I25 150 - TA 125 VGS = 2.5V 10 5 10-5 10-4 10-3 10-2 10-1 100 101 102 103 t, PULSE WIDTH (s) Figure 4. Peak Current Capability FDW2511NZ Rev. A1 4 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Typical Characteristic 400 40 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 10V 100µs ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 30 TJ = 150oC 20 TJ = 25oC 10 TJ = -55oC SINGLE PULSE TJ = MAX RATED TA = 25oC 1 0.5 0 0.1 1.0 10 30 1.0 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. Forward Bias Safe Operating Area 2.0 2.5 Figure 6. Transfer Characteristics 40 40 VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 2.5V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (mΩ) ID, DRAIN CURRENT (A) 1.5 VGS , GATE TO SOURCE VOLTAGE (V) 30 VGS = 4.5V VGS = 1.8V 20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10 ID = 7.1A 30 20 ID = 1A TA = 25oC 0 10 0 0.5 1.0 1.5 1 Figure 7. Saturation Characteristics 3 4 5 Figure 8. Drain to Source On Resistance vs Gate Voltage and Drain Current 1.25 1.50 VGS = VDS, ID = 250µA PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2 VGS, GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) 1.25 1.00 1.00 0.75 VGS = 4.5V, ID = 7.1A 0.75 -80 0.50 -40 0 40 80 120 160 -80 TJ, JUNCTION TEMPERATURE (oC) 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) Figure 9. Normalized Drain to Source On Resistance vs Junction Temperature FDW2511NZ Rev. A1 -40 Figure 10. Normalized Gate Threshold Voltage vs Junction Temperature 5 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Typical Characteristic (Continued) TA = 25°C unless otherwise noted 2000 ID = 250µA CISS = CGS + CGD 1000 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.10 1.05 1.00 COSS ≅ CDS + CGD CRSS = CGD VGS = 0V, f = 1MHz 0.95 100 -80 -40 0 40 80 120 160 0.1 1 TJ , JUNCTION TEMPERATURE (oC) 10 20 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 11. Normalized Drain to Source Breakdown Voltage vs Junction Temperature Figure 12. Capacitance vs Drain to Source Voltage VGS , GATE TO SOURCE VOLTAGE (V) 4.5 VDD = 10V 3.0 1.5 WAVEFORMS IN DESCENDING ORDER: ID = 1A ID = 7.1A 0 0 3 6 Qg, GATE CHARGE (nC) 9 12 Figure 13. Gate Charge Waveforms for Constant Gate Currents FDW2511NZ Rev. A1 6 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Typical Characteristic (Continued) TA = 25°C unless otherwise noted VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01Ω tAV Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms VDS VDD Qg(TOT) L VDS VGS VGS VGS = 4.5V + Qgs2 VDD DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 Figure 18. Switching Time Test Circuit FDW2511NZ Rev. A1 50% 10% 50% PULSE WIDTH Figure 19. Switching Time Waveforms 7 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET Test Circuits and Waveforms .SUBCKT FDW2511NZ 2 1 3 ; rev July 2004 Ca 12 8 1.1e-9 Cb 15 14 1.1e-9 Cin 6 8 0.8e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD DESD2 91 9 DESD2MOD DESD1 91 7 DESD1MOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 ESLC EVTHRES + 19 8 + LGATE GATE 1 EVTEMP RGATE + 18 22 9 20 21 DBODY MWEAK MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE Lgate 1 9 9.1e-10 Ldrain 2 5 1e-9 Lsource 3 7 2.1e-10 RLSOURCE S1A 12 S2A 14 13 13 8 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 VBAT 5 8 EDS - - IT 14 + + Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD + 17 EBREAK 18 - 16 6 It 8 17 1 RLgate 1 9 9.1 RLdrain 2 5 10 RLsource 3 7 2.1 11 50 RDRAIN 6 8 ESG DBREAK + RSLC2 - Ebreak 11 7 17 18 24 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 DRAIN 2 5 + 8 22 RVTHRES Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.0e-2 Rgate 9 20 2.75 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 1.7e-3 Rvthres 22 8 Rvthresmod 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),2.5))} MODEL DbodyMOD D (IS=3.5E-11 RS=1.08e-2 IKF=.5 N= TRS1=8e-4 TRS2=6e-6 XTI=.1 +CJO=3.2e-10 TT=1.07e-8 M=0.68 TIKF=0.001) .MODEL DbreakMOD D (RS=1e-1 TRS1=9e-3 TRS2=-2.0e-5) .MODEL DESD1MOD D (BV=15.0 RS=1) .MODEL DESD2MOD D (BV=14.3 RS=1) .MODEL DplcapMOD D (CJO=0.70e-9 IS=1e-30 N=10 M=0.3) MODEL MstroMOD NMOS (VTO=1.21 KP=147 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=0.93 KP=1.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.75) .MODEL MweakMOD NMOS (VTO=0.752 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27.5 RS=.1) MODEL RbreakMOD RES (TC1=5.0e-4 TC2=8e-7) .MODEL RdrainMOD RES (TC1=2.1e-3 TC2=3.4e-6) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .MODEL RvtempMOD RES (TC1=-.9e-3 TC2=1e-7) .MODEL RvthresMOD RES (TC1=-1.1e-3 TC2=-4.0e-6) MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6 VOFF=-1.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-6) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5) ENDS *$ Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. FDW2511NZ Rev. A1 8 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET PSPICE Electrical Model REV July 2004 template fdw2511nz n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=3.5e-11,rs=1.08e-2,ikf=.5,trs1=8e-4,trs2=6e-6,xti=.1,cjo=3.2e-10,tt=1.07e-8,m=0.68,tikf=0.001) dp..model dbreakmod = (rs=1e-1,trs1=9e-3,trs2=-2.0e-5) dp..model dplcapmod = (cjo=0.70e-9,isl=10e-30,nl=10,m=0.3) m..model mstrongmod = (type=_n,vto=1.21,kp=147,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=0.93,kp=1.7,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=0.752,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6,voff=-1.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-6) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3) LDRAIN DPLCAP 5 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5) c.ca n12 n8 = 1.1e-9 10 c.cb n15 n14 = 1.1e-9 RLDRAIN RSLC1 c.cin n6 n8 = 0.8e-9 51 DRAIN 2 RSLC2 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod desd2 91 9 desd2mod desd1 91 7 desd1mod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 24 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 ISCL RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 DBREAK 50 - EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 LSOURCE SOURCE 3 7 RSOURCE RLSOURCE S1A i.it n8 n17 = 1 l.lgate n1 n9 = 9.1e-10 l.ldrain n2 n5 = 1e-9 l.lsource n3 n7 = 2.1e-10 12 S2A 13 8 14 13 S1B 15 18 RVTEMP CB 6 8 EGS - 19 IT 14 + + res.rlgate n1 n9 = 9.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 2.1 17 S2B 13 CA RBREAK VBAT 5 8 EDS - + 8 22 RVTHRES m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=5.0e-4,tc2=8e-7 m.desd1mod bv=15.0 rs=1) m.desd2mod bv=14.3 rs=1) res.rdrain n50 n16 = 1.0e-2, tc1=2.1e-3,tc2=3.4e-6 res.rgate n9 n20 = 2.75 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.7e-3, tc1=5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-1.1e-3,tc2=-4.0e-6 res.rvtemp n18 n19 = 1, tc1=-.9e-3,tc2=1e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 2.5)) } } FDW2511NZ Rev. A1 9 www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET SABER Electrical Model th REV July 2004 FDW2511NZ_JA Junction Ambient Minimum copper pad area CTHERM1 Junction c2 5.7e-4 CTHERM2 c2 c3 5.72e-4 CTHERM3 c3 c4 5.8e-4 CTHERM4 c4 c5 4.7e-3 CTHERM5 c5 c6 5.1e-3 CTHERM6 c6 c7 0.02 CTHERM7 c7 c8 0.2 CTHERM8 c8 Ambient 6 RTHERM1 CTHERM1 2 RTHERM2 RTHERM1 Junction c2 0.003 RTHERM2 c2 c3 0.25 RTHERM3 c3 c4 1.0 RTHERM4 c4 c5 1.1 RTHERM5 c5 c6 7.5 RTHERM6 c6 c7 33.6 RTHERM7 c7 c8 33.7 RTHERM8 c8 Ambient 33.8 CTHERM2 3 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 5 SABER Thermal Model SABER thermal model FDW2511NZ Minimum copper pad area template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 = 5.7e-4 ctherm.ctherm2 c2 c3 = 5.72e-4 ctherm.ctherm3 c3 c4 = 5.8e-4 ctherm.ctherm4 c4 c5 = 4.7e-3 ctherm.ctherm5 c5 c6 = 5.1e-3 ctherm.ctherm6 c6 c7 = 0.02 ctherm.ctherm7 c7 c8 = 0.2 ctherm.ctherm8 c8 tl = 6 RTHERM5 CTHERM5 6 RTHERM6 CTHERM6 7 RTHERM7 rtherm.rtherm1 th c2 = 0.003 rtherm.rtherm2 c2 c3 = 0.25 rtherm.rtherm3 c3 c4 = 1.0 rtherm.rtherm4 c4 c5 = 1.1 rtherm.rtherm5 c5 c6 = 7.5 rtherm.rtherm6 c6 c7 = 33.6 rtherm.rtherm7 c7 c8 = 33.7 rtherm.rtherm8 c8 tl = 33.8 } CTHERM7 8 RTHERM8 CTHERM8 tl FDW2511NZ Rev. A1 JUNCTION 10 AMBIENT www.fairchildsemi.com FDW2511NZ Dual N-Channel 2.5V Specified PowerTrench® MOSFET SPICE Thermal Model TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 FDW2511NZ Rev.A1 WWW. fairchildsemicom