FQD45N03L
N-Channel Logic Level PWM Optimized Power MOSFET
General Description
Features
This device employs a new advanced MOSFET technology
and features low gate charge while maintaining low onresistance.
• Fast switching
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
• rDS(ON) = 0.028Ω (Typ), VGS = 5V
Applications
• Qgd (Typ) =3nC
• DC/DC converters
• CISS (Typ) =970pF
• rDS(ON) = 0.018Ω (Typ), VGS = 10V
• Qg (Typ) = 9nC, VGS = 5V
D
DRAIN (FLANGE)
GATE
SOURCE
G
TO-252
S
MOSFET Maximum Ratings TC=25°C unless otherwise noted
Symbol
VDSS
Parameter
Drain to Source Voltage
VGS
Gate to Source Voltage
Ratings
30
Units
V
±20
V
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
20
A
Continuous (TC = 100oC, VGS = 4.5V)
20
A
8
A
Continuous (TC = 25oC, VGS = 10V, RθJA=52oC)
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Figure 4
A
41
0.33
W
W/oC
o
-55 to 150
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-252
3
RθJA
Thermal Resistance Junction to Ambient TO-252
100
RθJA
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
52
o
C/W
oC/W
o
C/W
Package Marking and Ordering Information
Device Marking
FQD45N03L
©2004 Fairchild Semiconductor Corporation
Device
FQD45N03L
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Quantity
2500 units
FQD45N03L Rev. B1
FQD45N03L
March 2004
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
30
-
-
-
V
-
1
-
-
250
µA
-
-
±100
nA
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 25V
VGS = 0V
TC= 150oC
VGS = ±20V
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
-
3
V
ID = 20A, VGS = 10V
-
0.018
0.023
ID = 18A, VGS = 4.5V
-
0.028
0.033
Ω
-
970
-
-
205
-
pF
-
80
-
pF
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
-
18
30
nC
Qg(5)
Total Gate Charge at 5V
-
9
16
nC
Qg(TH)
Threshold Gate Charge
-
1.0
1.5
nC
Qgs
Gate to Source Gate Charge
VGS = 0V to 5V VDD = 15V
VGS = 0V to 1V ID = 18A
Ig = 1.0mA
-
3.5
-
nC
Qgd
Gate to Drain “Miller” Charge
-
3.0
-
nC
Switching Characteristics
VDS = 15V, VGS = 0V,
f = 1MHz
pF
(VGS = 4.5V)
tON
Turn-On Time
-
-
87
ns
td(ON)
Turn-On Delay Time
-
11
-
ns
tr
Rise Time
-
47
-
ns
td(OFF)
Turn-Off Delay Time
-
24
-
ns
tf
Fall Time
-
28
-
ns
tOFF
Turn-Off Time
-
-
78
ns
Switching Characteristics
VDD = 15V, ID = 8A
VGS = 5V, RGS = 16Ω
(VGS = 10V)
tON
Turn-On Time
-
-
54
ns
td(ON)
Turn-On Delay Time
-
7
-
ns
tr
Rise Time
-
29
-
ns
td(OFF)
Turn-Off Delay Time
-
45
-
ns
tf
Fall Time
-
27
-
ns
tOFF
Turn-Off Time
-
-
108
ns
180
-
-
µs
ISD = 18A
-
-
1.25
V
ISD = 9A
-
-
1.0
V
VDD = 15V, ID = 8A
VGS = 10V, RGS = 16Ω
Unclamped Inductive Switching
tav
Avalanche Time
ID = 2.7A, L = 3mH
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD= 18A, dISD/dt = 100A/µs
-
-
58
ns
QRR
Reverse Recovered Charge
ISD= 18A, dISD/dt = 100A/µs
-
-
70
nC
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Electrical Characteristics TC = 25°C unless otherwise noted
TC = 25°C unless otherwise noted
25
1.2
POWER DISSIPATION MULTIPLIER
FQD45N03L
Typical Characteristic
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
20
VGS = 10V
15
VGS = 5V
10
5
0.2
0
0
0
25
50
75
100
125
150
25
50
TA , AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
75
100
125
TC, CASE TEMPERATURE (oC)
150
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TC = 25oC
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
150 - TC
I = I25
100
125
VGS = 5V
10
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
10-1
100
101
Figure 4. Peak Current Capability
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Typical Characteristic (Continued) TC = 25°C unless otherwise noted
50
50
PULSE DURATION = 80µs
ID, DRAIN CURRENT (A)
40
ID , DRAIN CURRENT (A)
VGS = 10V
DUTY CYCLE = 0.5% MAX
VDD = 15V
30
TJ = 150oC
20
TJ = 25oC
10
40
VGS = 4V
30
20
VGS = 3V
10
TJ =
-55oC
DURATION = 80µs
TC = 25oC PULSE
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
VGS , GATE TO SOURCE VOLTAGE (V)
0
5
Figure 5. Transfer Characteristics
0.5
1.0
1.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
2.0
Figure 6. Saturation Characteristics
2.0
40
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 5V
ID = 20A
ID = 10A
30
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.5
1.0
VGS = 10V, ID =20A
10
0.5
2
4
6
8
10
-80
-40
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Drain To Source On Resistance vs Gate
Voltage And Drain Current
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
0.8
0.6
0.4
160
Figure 8. Normalized Drain To Source On
Resistance vs Junction Temperatrue
1.2
1.0
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
1.1
1.0
0.9
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
©2004 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain To Source
Breakdown Voltage vs Junction Temperature
FQD45N03L Rev. B1
FQD45N03L
Typical Characteristic (Continued) TC = 25°C unless otherwise noted
2000
10
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
C, CAPACITANCE (pF)
1000
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
40
0.1
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 10A
2
0
1
10
30
0
5
VDS , DRAIN TO SOURCE VOLTAGE (V)
10
15
20
Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain To Source
Voltage
Figure 12. Gate Charge Waveforms For Constant
Gate Current
150
100
VGS = 10V, VDD = 15V, ID = 8A
VGS = 4.5V, VDD = 15V, ID = 8A
td(OFF)
80
60
SWITCHING TIME (ns)
SWITCHING TIME (ns)
tr
tf
40
td(OFF)
td(ON)
20
100
tf
50
tr
td(ON)
0
0
0
10
20
30
40
50
0
RGS, GATE TO SOURCE RESISTANCE (Ω)
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS
BVDSS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
©2004 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
FQD45N03L Rev. B1
FQD45N03L
Test Circuits and Waveforms (Continued)
VDS
VDD
Qg(TOT)
RL
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2004 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveform
FQD45N03L Rev. B1
FQD45N03L
Thermal Resistance vs. Mounting Pad Area
( T JM – T A )
P DM = ----------------------------Z θJA
125
RθJA = 33.32 + 23.84/(0.268+Area)
100
RθJA (oC/W)
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
75
(EQ. 1)
50
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
25
0.01
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
23.84
( 0.268 + Area )
R θ JA = 33.32 + -------------------------------------
©2004 Fairchild Semiconductor Corporation
(EQ. 2)
FQD45N03L Rev. B1
rev October 2002
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC2
5
51
-
LGATE
EVTEMP
RGATE +
18 22
9
20
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 2e-3
RGATE 9 20 2.65
RLDRAIN 2 5 10
RLGATE 1 9 44.1
RLSOURCE 3 7 39.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
ESLC
11
50
21
EBREAK
16
+
17
18
-
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
EVTHRES
+ 19 8
+
GATE
1
DBREAK
RDRAIN
6
8
ESG
LDRAIN 2 5 1e-9
LGATE 1 9 4.41e-9
LSOURCE 3 7 3.99e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 31.4
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
+
.SUBCKT FQD45N03L 2 1 3 ;
CA 12 8 8e-10
CB 15 14 9e-10
CIN 6 8 8.9e-10
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
IT
14
+
+
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*75),5))}
.MODEL DBODYMOD D (IS = 1.28e-11 RS = 8.48e-3 TRS1 = 1.6e-3 TRS2 = 3e-6 XTI=2 CJO = 5.7e-10 TT = 9.5e-9 M = 0.57)
.MODEL DBREAKMOD D (RS = 0.22 TRS1 = 8e-4 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 3.7e-10 IS = 1e-30 N = 10 M = 0.48)
.MODEL MMEDMOD NMOS (VTO = 1.99 KP = 8 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.65)
.MODEL MSTROMOD NMOS (VTO = 2.4 KP = 32 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.5 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 9e-4 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 2e-2 TC2 = 4e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-7)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.6e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2.6e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -3.0 VOFF= -2.0)
VON = -2.0 VOFF= -3.0)
VON = -0.5 VOFF= 0.2)
VON = 0.2 VOFF= -0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
PSPICE Electrical Model
FQD45N03L
SABER Electrical Model
REV October 2002
template FQD45N03L n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.28e-11, rs = 8.48e-3, trs1 = 1.6e-3, trs2 = 3e-6, xti=2, cjo = 5.7e-10, tt = 9.5e-9, m = 0.57)
dp..model dbreakmod = (rs = 0.22, trs1 = 8e-4, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 3.7e-10, isl=10e-30, nl=10, m=0.48)
m..model mmedmod = (type=_n, vto = 1.99, kp=8, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.4, kp = 32, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.62, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -2.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -3.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.2)
LDRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.5)
DPLCAP 5
10
c.ca n12 n8 = 8e-10
c.cb n15 n14 = 9e-10
c.cin n6 n8 = 8.9e-9
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
GATE
1
EVTEMP
RGATE + 18 22
9
20
6
CIN
8
LSOURCE
7
RSOURCE
S1A
12
13
8
S2A
14
13
S1B
CA
EBREAK
+
17
18
-
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
DBODY
MWEAK
MSTRO
RLGATE
res.rbreak n17 n18 = 1, tc1 = 9e-4, tc2 = 0
res.rdrain n50 n16 = 2e-3, tc1 = 2e-2, tc2 = 4e-5
res.rgate n9 n20 = 2.65
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 44.1
res.rlsource n3 n7 = 39.9
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 = 1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1e-2, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.6e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.6e-3, tc2 = -8e-6
11
EVTHRES
16
21
+ 19 8
+
LGATE
DBREAK
50
-
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.41e-9
l.lsource n3 n7 = 3.99e-9
DRAIN
2
RLSOURCE
RBREAK
15
17
18
RVTEMP
S2B
13
CB
+
+
6
8
EGS
SOURCE
3
VBAT
5
8
EDS
-
19
IT
14
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 31.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/75))** 5))
}
}
©2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
th
FQD45N03L
SPICE Thermal Model
JUNCTION
REV October 2002
FQD45N03L_Thermal
CTHERM1 th 6 1.3e-3
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 1.6e-3
CTHERM4 4 3 1.7e-3
CTHERM5 3 2 5.8e-3
CTHERM6 2 tl 2e-2
RTHERM1
CTHERM1
6
RTHERM1 th 6 3.5e-3
RTHERM2 6 5 4.5e-3
RTHERM3 5 4 6.2e-2
RTHERM4 4 3 6.8e-1
RTHERM5 3 2 8.1e-1
RTHERM6 2 tl 8.3e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FQD45N03L_Thermal
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.3e-3
ctherm.ctherm2 6 5 = 1.5e-3
ctherm.ctherm3 5 4 = 1.6e-3
ctherm.ctherm4 4 3 = 1.7e-3
ctherm.ctherm5 3 2 = 5.8e-3
ctherm.ctherm6 2 tl = 2e-2
rtherm.rtherm1 th 6 = 3.5e-3
rtherm.rtherm2 6 5 = 4.5e-3
rtherm.rtherm3 5 4 = 6.2e-2
rtherm.rtherm4 4 3 = 6.8e-1
rtherm.rtherm5 3 2 = 8.1e-1
rtherm.rtherm6 2 tl = 8.3e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
CTHERM6
RTHERM6
tl
©2004 Fairchild Semiconductor Corporation
CASE
FQD45N03L Rev. B1
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Rev. I9