FDP8874
N
May 2008
FDP8874
tmM
N-Channel PowerTrench® MOSFET
30V, 114A, 5.3mΩ
General Description
Features
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM
controllers. It has been optimized for low gate charge, low
rDS(ON) and fast switching speed.
• rDS(ON) = 5.3mΩ, VGS = 10V, ID = 40A
• rDS(ON) = 6.6mΩ, VGS = 4.5V, ID = 40A
• High performance trench technology for extremely low
rDS(ON)
• Low gate charge
Applications
• High power and current handling capability
• DC/DC converters
•
(FLANGE)
DRAIN
RoHS Compliant
D
SOURCE
DRAIN
G
GATE
S
TO-220AB
FDP SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
30
Units
V
VGS
Gate to Source Voltage
±20
V
Continuous (TC = 25oC, VGS = 10V) (Note 1)
114
A
Continuous (TC = 25oC, VGS = 4.5V) (Note 1)
102
A
Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 62oC/W)
16
A
Drain Current
ID
Pulsed
EAS
PD
TJ, TSTG
Single Pulse Avalanche Energy (Note 2)
Figure 4
A
105
mJ
Power dissipation
110
W
Derate above 25oC
0.73
W/oC
-55 to 175
oC
Operating and Storage Temperature
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-220
RθJA
Thermal Resistance Junction to Ambient TO-220 ( Note 3)
1.36
o
C/W
62
o
C/W
Package Marking and Ordering Information
Device Marking
FDP8874
©2008 Fairchild Semiconductor Corporation
Device
FDP8874
Package
TO-220AB
Reel Size
Tube
Tape Width
N/A
Quantity
50 units
FDP8874 Rev. A3
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 24V
VGS = 0V
TC = 150oC
VGS = ±20V
30
-
-
V
-
-
1
-
-
250
µA
-
-
±100
nA
-
2.5
V
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1.2
ID = 40A, VGS = 10V
-
0.0036 0.0053
ID = 40A, VGS = 4.5V
-
0.0045 0.0066
ID = 40A, VGS = 10V,
TJ = 175oC
-
0.0062 0.0090
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
RG
Gate Resistance
Qg(TOT)
Total Gate Charge at 10V
-
3130
-
-
590
-
pF
-
345
-
pF
VGS = 0.5V, f = 1MHz
-
1.9
-
Ω
VGS = 0V to 10V
-
56
72
nC
VDS = 15V, VGS = 0V,
f = 1MHz
Qg(5)
Total Gate Charge at 5V
VGS = 0V to 5V
Qg(TH)
Threshold Gate Charge
VGS = 0V to 1V
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDD = 15V
ID = 40A
Ig = 1.0mA
pF
-
30
38
nC
-
3.0
4.0
nC
-
9.0
-
nC
-
6.0
-
nC
-
11
-
nC
(VGS = 10V)
tON
Turn-On Time
-
-
207
ns
td(ON)
Turn-On Delay Time
-
10
-
ns
ns
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
tOFF
-
128
-
-
44
-
ns
Fall Time
-
31
-
ns
Turn-Off Time
-
-
112
ns
ISD = 40A
-
-
1.25
V
ISD = 20A
-
-
1.0
V
VDD = 15V, ID = 40A
VGS = 4.5V, RGS = 4.7Ω
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
trr
Reverse Recovery Time
ISD = 40A, dISD/dt = 100A/µs
-
-
32
ns
QRR
Reverse Recovered Charge
ISD = 40A, dISD/dt = 100A/µs
-
-
18
nC
Notes:
1: Package current limitation is 80A.
2: Starting TJ = 25°C, L = 51uH, IAS = 64A, VDD = 27V, VGS = 10V.
3: Pulse width = 100s.
4
©2008 Fairchild Semiconductor Corporation
FDP8874 Rev. A3
FDP8874
Electrical Characteristics TC = 25°C unless otherwise noted
FDP8874
Typical Characteristics TC = 25°C unless otherwise noted
125
CURRENT LIMITED
BY PACKAGE
1.0
100
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
75
VGS = 10V
VGS = 4.5V
50
25
0.2
0
0
0
25
50
75
100
150
125
TC , CASE TEMPERATURE
175
25
50
75
(oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs Case
Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25oC
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
VGS = 4.5V
150
VGS = 10V
100
50
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2008 Fairchild Semiconductor Corporation
FDP8874 Rev. A3
FDP8874
Typical Characteristics TC = 25°C unless otherwise noted
500
1000
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10µs
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
DC
1
0.01
0.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
Figure 5. Forward Bias Safe Operating Area
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
160
160
VGS = 5V
VGS = 4V
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
120
80
TJ =
25oC
40
TJ = 175oC
120
VGS = 10V
80
VGS = 3V
40
TC = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TJ = -55oC
0
0
2.0
2.5
3.0
3.5
VGS , GATE TO SOURCE VOLTAGE (V)
0
4.0
0.2
0.4
0.6
0.8
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Saturation Characteristics
1.8
12
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
ID = 40A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
100
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
10
8
6
ID = 1A
4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.6
1.4
1.2
1.0
0.8
VGS = 10V, ID = 40A
2
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 9. Drain to Source On Resistance vs Gate
Voltage and Drain Current
©2008 Fairchild Semiconductor Corporation
0.6
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDP8874 Rev. A3
FDP8874
Typical Characteristics TC = 25°C unless otherwise noted
1.2
1.10
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
0.4
-80
-40
0
40
80
120
160
1.05
1.00
0.95
0.90
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10
5000
VGS , GATE TO SOURCE VOLTAGE (V)
VDD = 15V
C, CAPACITANCE (pF)
CISS = CGS + CGD
COSS ≅ CDS + CGD
1000
CRSS = CGD
VGS = 0V, f = 1MHz
100
0.1
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 40A
ID = 1A
2
0
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2008 Fairchild Semiconductor Corporation
30
0
10
20
30
40
Qg, GATE CHARGE (nC)
50
60
Figure 14. Gate Charge Waveforms for Constant
Gate Current
FDP8874 Rev. A3
FDP8874
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
IAS
+
RG
REQUIRED PEAK IAS
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS = 10V
VGS
Qg(5)
+
Qgs2
VDD
VGS = 5V
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
Figure 19. Switching Time Test Circuit
©2008 Fairchild Semiconductor Corporation
50%
10%
50%
PULSE WIDTH
Figure 20. Switching Time Waveforms
FDP8874 Rev. A3
.SUBCKT FDP8874 2 1 3 ; rev May 2004
Ca 12 8 2.3e-9
Cb 15 14 2.25e-9
Cin 6 8 2.9e-9
LDRAIN
DPLCAP
DRAIN
2
5
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
5
51
ESLC
EVTHRES
+ 19 8
+
LGATE
GATE
1
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
Ebreak 11 7 17 18 33.3
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
RLDRAIN
RSLC1
51
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 8.5e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.7e-9
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
RLgate 1 9 85
RLdrain 2 5 10
RLsource 3 7 27
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
17
18
RVTEMP
S2B
13
CB
19
6
8
VBAT
5
8
EDS
-
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.7e-3
Rgate 9 20 1.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.7e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
15
14
13
S1B
CA
RBREAK
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}
.MODEL DbodyMOD D (IS=4.1E-12 IKF=10 N=1.01 RS=2e-3 TRS1=8e-4 TRS2=2e-7
+ CJO=1.22e-9 M=0.57 TT=3e-12 XTI=3)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.12e-9 IS=1e-30 N=10 M=0.42)
.MODEL MmedMOD NMOS (VTO=2 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.9)
.MODEL MstroMOD NMOS (VTO=2.5 KP=390 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=1.72 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=19 RS=0.1)
.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-8e-7)
.MODEL RdrainMOD RES (TC1=7e-3 TC2=3.8e-6)
.MODEL RSLCMOD RES (TC1=1e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=1e-4 TC2=2.5e-6)
.MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2008 Fairchild Semiconductor Corporation
FDP8874 Rev. A3
FDP8874
PSPICE Electrical Model
FDP8874
SABER Electrical Model
rev May 2004
template FDP8874 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=4.1e-12,ikf=10,nl=1.01,rs=2e-3,trs1=8e-4,trs2=2e-7,cjo=1.22e-9,m=0.57,tt=3e-12,xti=3)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.12e-9,isl=10e-30,nl=10,m=0.42)
m..model mmedmod = (type=_n,vto=2,kp=9,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.5,kp=390,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.72,kp=0.05,is=1e-30, tox=1,rs=0.1)
LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3)
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4)
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5)
RLDRAIN
RSLC1
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2)
51
c.ca n12 n8 = 2.3e-9
RSLC2
c.cb n15 n14 = 2.25e-9
ISCL
c.cin n6 n8 = 2.9e-9
spe.ebreak n11 n7 n17 n18 = 33.3 GATE
spe.eds n14 n8 n5 n8 = 1
1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
EVTEMP
RGATE +
18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
DRAIN
2
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 8.5e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9
S2A
14
13
13
8
S1B
CA
res.rlgate n1 n9 = 85
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 27
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-8e-7
res.rdrain n50 n16 = 1.7e-3, tc1=7e-3,tc2=3.8e-6
res.rgate n9 n20 = 1.9
res.rslc1 n5 n51 = 1e-6, tc1=1e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.7e-3, tc1=1e-4,tc2=2.5e-6
res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))
}
}
©2008 Fairchild Semiconductor Corporation
FDP8874 Rev. A3
th
FDP8874
PSPICE Thermal Model
JUNCTION
REV 23 May 2004
FDP8874T
CTHERM1 TH 6 1.9e-3
CTHERM2 6 5 2.8e-3
CTHERM3 5 4 3.5e-3
CTHERM4 4 3 3.6e-3
CTHERM5 3 2 4.0e-3
CTHERM6 2 TL 1.6e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 3.8e-2
RTHERM2 6 5 5.0e-2
RTHERM3 5 4 1.0e-1
RTHERM4 4 3 1.8e-1
RTHERM5 3 2 3.5e-1
RTHERM6 2 TL 3.7e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FDP8874T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.9e-3
ctherm.ctherm2 6 5 =2.8e-3
ctherm.ctherm3 5 4 =3.5e-3
ctherm.ctherm4 4 3 =3.6e-3
ctherm.ctherm5 3 2 =4.0e-3
ctherm.ctherm6 2 tl =1.6e-2
rtherm.rtherm1 th 6 =3.8e-2
rtherm.rtherm2 6 5 =5.0e-2
rtherm.rtherm3 5 4 =1.0e-1
rtherm.rtherm4 4 3 =1.8e-1
rtherm.rtherm5 3 2 =3.5e-1
rtherm.rtherm6 2 tl =3.7e-1
}
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
CTHERM6
RTHERM6
tl
©2008 Fairchild Semiconductor Corporation
CASE
FDP8874 Rev. A3
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RapidConfigure™
Saving our world 1mW at a time™
SmartMax™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SuperMOS™
®
The Power Franchise®
tm
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
Ultra FRFET™
UniFET™
VCX™
VisualMax™
tm
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems which,
(a) are intended for surgical implant into the body or (b)
support or sustain life, and (c) whose failure to perform when
properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a
significant injury of the user.
2.
A critical component in any component of a life support,
device, or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve the design.
Obsolete
Not In Production
This datasheet contains specifications on a product that is discontinued by
Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I34
@2008 Fairchild Semiconductor Corporation
FDP8874 Rev.A3