FDMC8030 Dual N-Channel Power Trench® MOSFET 40 V, 12 A, 10 mΩ Features General Description Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 12 A This device includes two 40V N-Channel MOSFETs in a dual Power 33 (3 mm X 3 mm MLP) package. The package is enhanced for exceptional thermal performance. Max rDS(on) = 14 mΩ at VGS = 4.5 V, ID = 10 A Max rDS(on) = 28 mΩ at VGS = 3.2 V, ID = 4 A Termination is Lead-free and RoHS Compliant Applications Battery Protection Load Switching Point of Load Pin 1 G1 S1 S1 S1 Bottom Drain2 Contact D1 G2 8 S2 7 Q2 2 S1 S2 6 Q1 3 S1 S2 5 1 G1 D2 G2 S2 S2 S2 Bottom Drain1 Contact 4 S1 Power 33 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TA = 25 °C Ratings 40 Units V (Note 4) ±12 V (Note 1a) 12 -Pulsed 50 Single Pulse Avalanche Energy EAS PD TJ, TSTG (Note 3) 21 Power Dissipation TA = 25 °C (Note 1a) 1.9 Power Dissipation TA = 25 °C (Note 1b) 0.8 Operating and Storage Junction Temperature Range -55 to +150 A mJ W °C Thermal Characteristics RθJA Thermal Resistance, Junction to Ambient (Note 1a) 65 RθJA Thermal Resistance, Junction to Ambient (Note 1b) 155 °C/W Package Marking and Ordering Information Device Marking FDMC8030 Device FDMC8030 ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C Package Power 33 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC8030 Dual N-Channel Power Trench® MOSFET August 2011 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V IGSS Gate to Source Leakage Current, Forward VGS = 12 V, VDS = 0 V 40 V 19 mV/°C 1 μA 100 nA 2.8 V On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C rDS(on) gFS Static Drain to Source On Resistance Forward Transconductance 1.0 1.5 -5 mV/°C VGS = 10 V, ID = 12 A 8 10 VGS = 4.5 V, ID = 10 A 10 14 VGS = 3.2 V, ID = 4 A 19 28 VGS = 10 V, ID = 12 A TJ = 125 °C 13 16 VDD = 5 V, ID = 12 A 57 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 20 V, VGS = 0 V f = 1MHz 1462 1975 pF 321 430 pF 20 30 pF 0.9 2.5 Ω 7 13 ns 3 10 ns 19 33 ns 3 10 ns 21 30 nC 12 17 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 20 V, ID = 12 A VGS = 10 V, RGEN = 6 Ω Total Gate Charge VGS = 0 V to 10 V Total Gate Charge VGS = 0 V to 5 V Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 20 V ID = 12 A nC 2.8 nC 2.5 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 12 A (Note 2) IF = 12 A, di/dt = 100 A/μs 0.83 1.2 V 25 40 ns 9 18 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b.155 °C/W when mounted on a minimum pad of 2 oz copper a. 65 °C/W when mounted on a 1 in2 pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 21 mJ is based on starting TJ = 25 oC, L = 0.3 mH, IAS = 12 A, VDD = 36 V, VGS = 10 V. 100% tested at L = 3 mH, IAS = 5 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurence only. No continuous rating is implied. ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C 2 www.fairchildsemi.com FDMC8030 Dual N-Channel Power Trench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 50 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 4.5 V 40 VGS = 3.5 V VGS = 3.2 V 30 VGS = 3 V 20 10 0 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 0 1 2 3 4 VGS = 3 V 4 VGS =3.2 V 3 VGS = 3.5 V 2 1 0 5 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 30 ID = 12 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 30 40 50 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 25 ID = 12 A 20 15 TJ = 125 oC 10 TJ = 25 oC 5 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 4. On-Resistance vs Gate to Source Voltage Figure 3. Normalized On- Resistance vs Junction Temperature 50 50 40 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX ID, DRAIN CURRENT (A) 20 VGS = 10 V ID, DRAIN CURRENT(A) Figure 1. On-Region Characteristics VDS = 5 V 30 TJ = 150 oC 20 TJ = 25 oC 10 TJ = -55 oC 0 VGS = 4.5 V PULSE DURATION = 80μs DUTY CYCLE = 0.5%MAX 1 2 3 VGS = 0 V 10 1 TJ = 25 oC 0.1 0.01 0.001 0.0 4 TJ = 150 oC TJ = -55 oC 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C 3 1.2 www.fairchildsemi.com FDMC8030 Dual N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted 2000 ID = 12 A 1000 VDD = 15 V Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE(V) 10 VDD = 20 V 6 VDD = 25 V 4 Coss 100 10 Crss 2 f = 1 MHz VGS = 0 V 0 0 5 10 15 1 0.1 20 1 Figure 7. Gate Charge Characteristics 40 Figure 8. Capacitance vs Drain to Source Voltage 30 60 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT(A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE(nC) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 100 μs 10 1 ms 1 10 ms THIS AREA IS LIMITED BY rDS(on) 0.1 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 155 oC/W 1 0.001 10 s DC TA = 25 oC 0.01 0.1 1 0.01 0.01 10 20 tAV, TIME IN AVALANCHE(ms) 0.1 1 10 100200 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Unclamped Inductive Switching Capability Figure 10. Forward Bias Safe Operating Area 1000 P(PK), PEAK TRANSIENT POWER (W) SINGLE PULSE o RθJA = 155 C/W o 100 TA = 25 C 10 1 0.1 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Single Pulse Maximum Power Dissipation ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C 4 www.fairchildsemi.com FDMC8030 Dual N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 155 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C 5 www.fairchildsemi.com FDMC8030 Dual N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25°C unless otherwise noted FDMC8030 Dual N-Channel Power Trench® MOSFET Dimensional Outline and Pad Layout ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C 6 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I55 ©2011 Fairchild Semiconductor Corporation FDMC8030 Rev.C 7 www.fairchildsemi.com FDMC8030 Dual N-Channel Power Trench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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