STMICROELECTRONICS STL9N3LLH5

STL9N3LLH5
N-channel 30 V, 0.015 Ω, 9 A, PowerFLAT™ (3.3x3.3)
STripFET™ V Power MOSFET
Features
Type
VDSS
RDS(on)
max
ID
STL9N3LLH5
30 V
< 0.019 Ω
9 A (1)
1. The value is rated according Rthj-pcb
■
RDS(on) * Qg industry benchmark
■
Extremely low on-resistance RDS(on)
■
Very low switching gate charge
■
High avalanche ruggedness
■
Low gate drive power losses
PowerFLAT™(3.3x3.3)
(Chip scale package)
Applications
■
Figure 1.
Switching applications
Internal schematic diagram
Description
This product utilizes the 5th generation of design
rules of ST’s proprietary STripFET™ technology.
The lowest available RDS(on)*Qg, in this chip scale
package, makes this device suitable for the most
demanding DC-DC converter applications, where
high power density is to be achieved.
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL9N3LLH5
9N3L
PowerFLAT™ (3.3x3.3)
Tape and reel
July 2009
Doc ID 16012 Rev 1
1/12
www.st.com
12
Contents
STL9N3LLH5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2/12
.............................................. 6
Doc ID 16012 Rev 1
STL9N3LLH5
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
30
V
± 22
V
VDS
Drain-source voltage (VGS = 0)
VGS
Gate-source voltage
ID(1)
Drain current (continuous) at TC = 25 °C
9
A
ID (1)
Drain current (continuous) at TC=100 °C
6
A
(2)
Drain current (pulsed)
36
A
PTOT(3)
Total dissipation at TC = 25 °C
50
W
PTOT(1)
Total dissipation at TC = 25 °C
2
W
0.4
W/°C
-55 to 150
°C
Value
Unit
IDM
Derating factor
TJ
Operating junction temperature
storage temperature
Tstg
1. The value is rated according Rthj-pcb
2. Pulse width limited by safe operating area.
3. The vaule is rated according Rthj-c
Table 3.
Thermal resistance
Symbol
Parameter
Thermal resistance junction-case (drain)
2.5
°C/W
(1)
Thermal resistance junction-pcb
42.8
°C/W
Rthj-pcb (2)
Thermal resistance junction-pcb
63.5
°C/W
Rthj-case
Rthj-pcb
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec
2. Steady state
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Electrical characteristics
2
STL9N3LLH5
Electrical characteristics
(TCASE=25 °C unless otherwise specified)
Table 4.
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown
voltage
ID = 250 µA, VGS= 0
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ± 22 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 4.5 A
Symbol
Ciss
Coss
Crss
Qg
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Qgd
RG
Gate input resistance
Table 6.
Symbol
td(on)
tr
td(off)
tf
Typ.
Max.
30
Unit
V
1
10
µA
µA
±100
nA
2.5
V
15
19
19
22
mΩ
mΩ
Min.
Typ.
Max.
Unit
-
724
132
20
pF
pF
pF
-
5
2
2
nC
nC
nC
VDS = Max rating @125 °C
1
VGS= 4.5 V, ID= 4.5 A
Dynamic
Total gate charge
Gate-source charge
Gate-drain charge
Qgs
Min.
VDS = Max rating,
IDSS
Table 5.
4/12
On/off states
Test conditions
VDS =25 V, f=1 MHz,
VGS=0
VDD=15 V, ID = 9 A
VGS =4.5 V
(see Figure 14)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
Open drain
-
Test conditions
Min.
Typ.
-
4
4.2
21
3.5
3.3
Ω
Max.
Unit
-
ns
ns
ns
ns
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
VDD=15 V, ID= 4.5 A,
RG=4.7 Ω, VGS= 10 V
(see Figure 13)
Doc ID 16012 Rev 1
STL9N3LLH5
Electrical characteristics
Table 7.
Symbol
ISD
Source drain diode
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
9
A
ISDM(1)
Source-drain current (pulsed)
-
36
A
VSD(2)
Forward on voltage
-
1.1
V
trr
Qrr
IRRM
ISD= 9 A, VGS=0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 9 A,
di/dt = 100 A/µs,
VDD=20 V, Tj=150 °C
(see Figure 18)
-
21
10
1
ns
nC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5 %
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Electrical characteristics
STL9N3LLH5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM03821v1
ID
(A)
100
Operation in this area is
Limited by max RDS(on)
10
10ms
1
100ms
1s
Tj=150°C
Tc=25°C
0.1
Sinlge
pulse
0.01
0.1
Figure 4.
10
1
VDS(V)
Output characteristics
AM03815v1
ID
(A)
VGS=10V
AM03822v1
ID
(A)
30
100
6V
80
25
5V
20
60
15
4V
40
10
20
5
3V
0
0
Figure 6.
1
2
3
4
Normalized BVDSS vs temperature
AM03819v1
BVDSS
(norm)
0
0
Figure 7.
RDS(on)
(Ω)
25
1.05
20
1.00
15
0.95
10
20 45 70 95 120
TJ(°C)
Doc ID 16012 Rev 1
1
2
3
4
5 VGS(V)
Static drain-source on resistance
1.1
0.9
-50 -30 -5
6/12
VDS(V)
5
0
AM03823v1
ID=4.5A
VGS=10V
2
4
6
8
10 ID(A)
STL9N3LLH5
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
AM03817v1
VGS
(V)
VDD=15V
VGS=4.5V
ID=9A
10
Capacitance variations
AM03816v1
C
(pF)
1000
800
Ciss
8
600
6
400
4
200
2
Coss
0
0
4
2
6
8
0
0
10 Qg(nC)
Figure 10. Normalized gate threshold voltage
vs temperature
AM03820v1
VGS(th)
(norm)
1.10
10
20
Crss
VDS(V)
Figure 11. Normalized on resistance vs
temperature
RDS(on)
(norm)
AM03824v1
1.6
1.4
0.90
1.2
0.80
1
0.60
0.8
0.40
-55 -30 -5
20 45 70 95 120 TJ(°C)
0.6
-55 -30 -5
20 45 70 95 120 TJ(°C)
Figure 12. Source-drain diode forward
characteristics
AM03818v1
VSD
(V)
TJ=-50°C
0.9
0.8
TJ=25°C
0.7
TJ=150°C
0.6
0.5
0.4
0
2
4
6
8
10 ISD(A)
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Test circuits
3
STL9N3LLH5
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100µH
S
3.3
µF
B
25 Ω
1000
µF
D
VDD
2200
µF
3.3
µF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/12
0
Doc ID 16012 Rev 1
10%
AM01473v1
STL9N3LLH5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 16012 Rev 1
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Package mechanical data
STL9N3LLH5
PowerFLAT™ ( 3.3 x 3.3) mechanical data
mm
inch
Dim
Min
A
0.950
A3
Max
Min
1.000
0.037
0.200
Typ
Max
0.039
0.008
b
0.29
0.34
0.39
0.011
0.013
0.015
D
3.200
3.300
3.400
0.126
0.123
0.134
D2
2.24
2.29
2.34
0.088
0.090
0.092
E
2.20
3.30
3.40
0.086
0.123
0.1338
E2
1.660
1.710
1.760
0.065
0.067
0.069
e
0.650
0.025
L
0.40
0.0157
L1
10/12
Typ
0.45
0.50
0.55
Doc ID 16012 Rev 1
0.017
0.0196
0.021
STL9N3LLH5
5
Revision history
Revision history
Table 8.
Document revision history
Date
Revision
09-Jul-2009
1
Changes
First release
Doc ID 16012 Rev 1
11/12
STL9N3LLH5
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