TPS7A8300
www.ti.com
SBVS197C – MAY 2013 – REVISED JULY 2013
2-A, 6-µVRMS, RF, LDO Voltage Regulator
Check for Samples: TPS7A8300
FEATURES
DESCRIPTION
•
•
•
The TPS7A8300 is a low-noise (6 µVRMS), lowdropout voltage regulator (LDO) capable of sourcing
a 2-A load with only 125 mV of maximum dropout.
1
23
•
•
•
•
•
•
(1)
Ultralow Dropout: 125 mV Maximum at 2 A
Output Voltage Noise: 6 µVRMS
Power-Supply Ripple Rejection:
– 40 dB at 1 MHz
Input Voltage Range:
– Without BIAS: +1.4 V to +6.5 V
– With BIAS: +1.1 V to +6.5 V
Two Output Voltage Modes:
– ANY-OUT™ Version (User-Programmable
Output via PCB Layout):
– No External Resistor or Feed-Forward
Capacitors Required
– Output Voltage Range: +0.8 V to 3.95 V
– Adjustable Version:
– Output Voltage Range: +0.8 V to 5.0 V
1.0% Accuracy Over Line, Load, and
Temperature
Stable with a 22-µF Output Ceramic Capacitor
Programmable Soft-Start and Power-Good
(PG) Output
Available Packages:
– 5-mm × 5-mm QFN-20
– 3,5-mm × 3,5-mm QFN-20 (1)
3,5-mm × 3,5-mm QFN-20 package is product-preview.
APPLICATIONS
•
•
•
•
RF, IF Components: VCO, ADC, DAC, LVDS
Wireless Infrastructure: SerDes, FPGA, DSP™
Test and Measurement
Instrumentation, Medical, and Audio
The TPS7A8300 output voltages are fully useradjustable (up to 3.95 V) using a printed circuit board
(PCB) layout without the need of external resistors or
feed-forward capacitors, thus reducing overall
component count. For higher output voltage
applications, the device achieves output voltages up
to 5 V with the use of external resistors. The device
supports very low input voltages (down to 1.1 V) with
the use of an additional BIAS rail.
With very high accuracy (1% over line, load, and
temperature), remote sensing, and soft-start
capabilities to reduce inrush current, the TPS7A8300
is ideal for powering high-current, low-voltage devices
such as high-end microprocessors and fieldprogrammable gate arrays (FPGAs).
The TPS7A8300 is designed to power-up noisesensitive components in high-speed communication
applications. The very low-noise, 6-µVRMS device
output and high broad-bandwidth PSRR (40 dB at
1 MHz) minimizes phase noise and clock jitter in
high-frequency signals. These features maximize
performance of clocking devices, analog-to-digital
converters (ADCs), and digital-to-analog converters
(DACs).
For applications where positive and negative lownoise rails are required, consider TI's TPS7A33 family
of negative high-voltage, ultralow-noise linear
regulators.
TPS7A8300
RF LDO
Amplifier
TPS7A33
Negative-Voltage
Regulator
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ANY-OUT, DSP, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS7A8300
SBVS197C – MAY 2013 – REVISED JULY 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
DESCRIPTION
YYY is the package designator.
Z is the package quantity.
TPS7A8300YYYZ
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
Voltage
UNIT
+7.0
V
IN, BIAS, PG, EN (5% duty cycle)
–0.3
+7.5
V
SNS, OUT
–0.3
(2)
V
NR/SS, FB
–0.3
+3.6
V
50 mV, 100 mV, 200 mV, 400 mV, 800 mV, 1.6 V
–0.3
VOUT + 0.3
V
Electrostatic discharge (ESD)
ratings (3)
VIN + 0.3
Internally limited
PG (sink current into device)
Temperature
(2)
(3)
MAX
–0.3
OUT
Current
(1)
MIN
IN, BIAS, PG, EN
A
5
mA
Operating junction temperature, TJ
–55
+150
°C
Storage, Tstg
–55
+150
°C
2
kV
500
V
Human body model (HBM), JESD22-A114A
Charged device model (CDM), JESD22-C101B.01
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is VIN + 0.3 V or +7.0 V, whichever is smaller.
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS7A8300
THERMAL METRIC
(1)
RGW (QFN)
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance
35.7
θJCtop
Junction-to-case (top) thermal resistance
33.6
θJB
Junction-to-board thermal resistance
15.2
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
15.4
θJCbot
Junction-to-case (bottom) thermal resistance
3.8
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
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SBVS197C – MAY 2013 – REVISED JULY 2013
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and
VBIAS open} (1), VIN ≥ VOUT(TARGET) + 0.3 V (2), VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND (3), VEN = 1.1 V, COUT =
22 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted.
Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VIN
Input supply voltage range
1.1
6.5
VBIAS
Bias supply voltage range (1)
3.0
6.5
V(REF)
Reference voltage
V(REF) = V(FB) = V(NR/SS)
VUVLO1(IN)
Input supply UVLO with BIAS
VIN increasing
VHYS1(IN)
VUVLO1(IN) hysteresis
VUVLO2(IN)
Input supply UVLO without BIAS
VHYS2(IN)
VUVLO2(IN) hysteresis
VUVLO(BIAS) Bias supply UVLO
VHYS(BIAS)
VIN increasing
VOUT
Output voltage accuracy (4) (5)
VBIAS increasing
Using external resistors
0.8 – 1.0%
5.0 + 1.0%
V
–1.0
+1.0
%
VIN = 1.5 V, VOUT = 1.2 V, 5 mA ≤ IOUT ≤ 1.2 A
–1.0
+1.0
%/V
0.0001
%/A
VIN ≥ 1.4 V and VBIAS open, 0.8 V ≤ VOUT ≤ 5.0 V,
IOUT = 2 A, VFB = 0.8 V – 3%
200
mV
VIN = 1.1 V, VBIAS = 5.0 V,
VOUT(TARGET) = 0.8 V, IOUT = 2 A, VFB = 0.8 V – 3%
125
mV
3.4
4.2
A
Minimum load,
VIN = 6.5 V, no VBIAS supply, IOUT = 5 mA
2.8
4
mA
Maximum load,
VIN = 1.4 V, no VBIAS supply, IOUT = 2 A
3.7
5
mA
2.5
μA
0.1
μA
3.5
mA
0
0.5
V
1.1
6.5
V
VOUT forced at 0.9 × VOUT(TARGET),
VIN = VOUT(TARGET) + 300 mV
EN pin current
VIN = 6.5 V, no VBIAS supply, V(EN) = 0 V and 6.5 V
I(BIAS)
BIAS pin current
VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(TARGET) = 0.8 V, IOUT = 2 A
VIL(EN)
EN pin low-level input voltage
(disable device)
VIH(EN)
EN pin high-level input voltage
(enable device)
(2)
(3)
(4)
(5)
%
0.003
2.1
Shutdown, PG = (open),
VIN = 6.5 V, no VBIAS supply, V(EN) = 0.5 V
(1)
V
0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 2 A
5 mA ≤ IOUT ≤ 2 A
I(EN)
V
mV
3.95 + 1.0%
Load regulation
GND pin current
2.9
0.8 – 1.0%
ΔVO(ΔIO)
Output current limit
V
mV
Using voltage setting pins (50 mV, 100 mV, 200 mV,
400 mV, 800 mV, and 1.6 V)
IOUT = 5 mA, 1.4 V ≤ VIN ≤ 6.5 V
Dropout voltage
1.39
290
Line regulation
I(GND)
2.83
V
mV
253
ΔVO(ΔVI)
I(LIM)
1.31
V
V
1.085
320
VUVLO(BIAS) hysteresis
Output voltage range
V(DO)
0.8
1.02
UNIT
–0.1
2.3
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is needed when the VIN supply is higher than
or equal to 1.4 V.
VOUT(TARGET) is the calculated VOUT target value from the output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and
1.6 V in a fixed configuration. In an adjustable configuration, VOUT(TARGET) is the expected VOUT value set by the external feedback
resistors.
This 50-Ω load is disconnected when the test conditions specify an IOUT value.
When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
The device is not tested under conditions where VIN > VOUT + 2.5 V and IOUT = 2 A, because the power dissipation is higher than the
maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power
dissipation limit of the package under test.
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ELECTRICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and
VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V(2), VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND(3), VEN = 1.1 V, COUT =
22 μF, CNR/SS = 0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ, unless otherwise noted.
Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
VIT(PG)
PG pin threshold
For the direction PG↓ with decreasing VOUT
Vhys(PG)
PG pin hysteresis
For PG↑
VOL(PG)
PG pin low-level output voltage
VOUT < VIT(PG), IPG = –1 mA (current into device)
Ilkg(PG)
PG pin leakage current
VOUT > VIT(PG), V(PG) = 6.5 V
I(NR/SS)
NR/SS pin charging current
VNR/SS = GND, VIN = 6.5 V
IFB
FB pin leakage current
VIN = 6.5 V
PSRR
Power-supply ripple rejection
f = 1 MHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 2 A,
CNR/SS = 10 nF, CFF = 10 nF
Vn
Output noise voltage
BW = 10 Hz to 100 kHz, VIN = 1.4 V, VOUT = 0.8 V,
IOUT = 1.5 A, CNR/SS = 10 nF, CFF = 10 nF
Tsd
Thermal shutdown temperature
TJ
Operating junction temperature
4
MIN
TYP
MAX
0.82 VOUT
0.872
VOUT
0.93 VOUT
0.02 VOUT
4.0
6.2
–100
V
0.4
V
1
μA
9.0
μA
+100
nA
dB
6
μVRMS
+160
Reset, temperature decreasing
+140
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V
40
Shutdown, temperature increasing
–40
UNIT
°C
°C
+125
°C
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TPS7A8300
TPS7A8300
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SBVS197C – MAY 2013 – REVISED JULY 2013
PIN CONFIGURATIONS
13
NR/SS
PG
4
12
BIAS
50 mV
5
11
1.6 V
7
8
9
10
200 mV
GND
400 mV
800 mV
OUT
GND
IN
IN
18
17
16
IN
SNS
2
14
EN
FB
3
13
NR/SS
PG
4
12
BIAS
50 mV
5
11
1.6 V
Thermal Pad
100 mV
6
100 mV
Thermal Pad
15
(1)
10
3
1
800 mV
FB
OUT
9
EN
400 mV
14
8
2
GND
SNS
6
IN
19
IN
16
15
7
IN
17
1
200 mV
GND
18
OUT
OUT
OUT
19
RGR PACKAGE(1)
3,5-mm × 3,5-mm QFN-20
(TOP VIEW)
20
OUT
20
RGW PACKAGE
5-mm × 5-mm QFN-20
(TOP VIEW)
3,5-mm × 3,5-mm QFN-20 (RGR) package
is product-preview.
PIN DESCRIPTIONS
NAME
PIN NO.
DESCRIPTION
50 mV, 100 mV,
200 mV, 400 mV,
800 mV, 1.6 V
5, 6, 7, 9, 10,
11
Output voltage setting pins. These pins should be connected to ground or left floating. Connecting these pins to ground
increases the output voltage by the value of the pin name; multiple pins can be simultaneously connected to GND to
select the desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable
Output Voltage section for more details.
BIAS
12
BIAS supply voltage pin for the use of 1.1 V ≤ VIN ≤ 1.4 V and to connect a capacitor between this pin and ground.
EN
14
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. See the
Startup section for more details.
FB
3
Output voltage feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor
from FB to OUT (as close to the device as possible) is recommended for low-noise applications to maximize ac
performance. The use of a feed-forward capacitor may disrupt PG (power good) functionality. See the ANY-OUT
Programmable Output Voltage and Adjustable Operation sections for more details.
GND
8, 18
Ground pin
IN
15-17
Input supply voltage pin. A 10-μF input ceramic capacitor is required. See the Input Capacitor Requirements section for
more details.
OUT
1, 19, 20
PG
4
Active-high power-good pin. An open-drain output indicates when the output voltage reaches 87% of the target. The
use of a feed-forward capacitor may disrupt PG (power good) functionality. See the Power-Good section for more
details.
SNS
2
Output voltage sense input pin. Connect this pin only if the ANY-OUT feature is used. See the ANY-OUT
Programmable Output Voltage and Adjustable Operation sections for more details.
NR/SS
13
Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference
voltage noise and also enables the soft-start function. Although not required, a capacitor is recommended for low-noise
applications to connect a 10-nF capacitor from NR/SS to GND (as close to the device as possible) to maximize ac
performance. See the Noise Reduction and Soft-Start section for more details.
Thermal Pad
Pad
Regulated output pin. A 22-μF or larger ceramic capacitor is required for stability (a 10-μF minimum effective
capacitance is required). See the Output Capacitor Requirements section for more details.
TI strongly recommends connecting the thermal pad to a large-area ground plane. The thermal pad is internally
connected to GND.
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FUNCTIONAL BLOCK DIAGRAM
Current
Limit
IN
OUT
Charge
Pump
BIAS
PG
1.2-V
Reference
0.8-V
Reference
0.72 V
NR/SS
CNR/SS
Under
Voltage
Lockout
Hysteresis
Under
Voltage
Lockout
Hysteresis
Thermal
Shutdown
SNS
Reference
Voltage
Detector
FB
Internal
Enable
Control
32R
CFF
2R
16R
8R
4R
2R
1R
EN
GND
50 mV
100 mV 200 mV 400 mV 800 mV
1.6 V
NOTE: 32R = 1.024 MΩ (that is, 1R = 3.2 kΩ).
Figure 1. Functional Block Diagram
6
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SBVS197C – MAY 2013 – REVISED JULY 2013
TYPICAL CHARACTERISTICS
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open} (1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
3
3
2
-40°C
0°C
+25°C
+85°C
2
0
±1
0
1
2
3
4
5
6
Input Voltage (V)
1
0
-1
3
7
3.5
4
4.5
5
5.5
6
6.5
Input Voltage (V)
C001
Figure 2. LINE REGULATION
(VOUT(TARGET) = 0.8 V, ANY-OUT, IOUT = 5 mA, VBIAS = Open)
7
C002
Figure 3. LINE REGULATION
(VOUT(TARGET) = 3.95 V, ANY-OUT, IOUT = 5 mA, VBIAS = Open)
3
3
2
-40°C
0°C
+25°C
+85°C
2
+125°C
-40°C
0°C
+25°C
+85°C
+125°C
1
VOUT(NOM) (%)
VOUT(NOM) (%)
+85°C
-3
±3
0
-1
-2
1
0
-1
-2
-3
-3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
2
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
C003
Figure 4. LOAD REGULATION
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.4 V, VBIAS = Open)
2
C004
Figure 5. LOAD REGULATION
(VOUT(TARGET) = 3.95 V, ANY-OUT, VIN = 4.25 V, VBIAS = Open)
3
3
2
-40°C
0°C
+25°C
+85°C
2
+125°C
-40°C
0°C
+25°C
+85°C
+125°C
1
VOUT(NOM) (%)
VOUT(NOM) (%)
+25°C
-2
±2
0
±1
1
0
-1
-2
±2
-3
±3
0
1
2
3
4
Bias Voltage (V)
5
6
7
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
C005
Figure 6. BIAS LINE REGULATION
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V, IOUT = 5 mA)
(1)
0°C
+125°C
1
VOUT(NOM) (%)
VOUT(NOM) (%)
+125°C
-40°C
2
C006
Figure 7. LOAD REGULATION
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V, VBIAS = 3 V)
BIAS supply is required when the VIN supply is below 1.4 V. Conversely, no BIAS supply is needed when the VIN supply is higher than
or equal to 1.4 V.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
3
3
2
-40°C
0°C
+25°C
+85°C
2
0
-1
-2
1
0
±1
±3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
2
0
1
2
3
4
5
6
Input Voltage (V)
C007
Figure 8. LOAD REGULATION
(VOUT(TARGET) = 0.8 V, Adjustable, VIN = 1.1 V, VBIAS = 6.5 V)
7
C008
Figure 9. LINE REGULATION
(VOUT(TARGET) = 0.8 V, Adjustable, IOUT = 5 mA, VBIAS = Open)
3
3
2
-40°C
0°C
+25°C
+85°C
2
+125°C
-40°C
0°C
+25°C
+85°C
+125°C
1
VOUT(NOM) (%)
VOUT(NOM) (%)
+85°C
±2
-3
0
-1
1
0
-1
-2
-2
-3
-3
4
4.5
5
5.5
6
6.5
Input Voltage (V)
0
7
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
C009
Figure 10. LINE REGULATION
(VOUT(TARGET) = 5 V, Adjustable, IOUT = 5 mA, VBIAS = Open)
2
C010
Figure 11. LOAD REGULATION
(VOUT(TARGET) = 0.8 V, Adjustable, VIN = 1.4 V, VBIAS = Open)
3
500
2
-40°C
0°C
+25°C
+85°C
-40°C
450
+125°C
1
VDO (mV)
VOUT(NOM) (%)
0°C
+25°C
+125°C
1
VOUT(NOM) (%)
VOUT(NOM) (%)
+125°C
-40°C
0
-1
400
0°C
350
+25°C
300
+85°C
250
+125°C
200
150
100
-2
50
-3
0
0
0.25
0.5
0.75
1
1.25
Output Current (A)
1.5
1.75
2
Figure 12. LOAD REGULATION
(VOUT(TARGET) = 5 V, Adjustable, VIN = 5.3 V, VBIAS = Open)
8
0
0.25
0.5
0.75
1
1.25
Output Current (A)
C011
1.5
1.75
2
C012
Figure 13. DROPOUT VOLTAGE vs OUTPUT CURRENT
(VIN = 1.4 V V, ANY-OUT, VBIAS = Open)
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
500
200
-40°C
400
0°C
160
0°C
350
+25°C
140
+25°C
300
+85°C
120
+85°C
250
+125°C
200
100
150
60
100
40
50
20
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
2
0
1
2
180
180
160
160
0°C
140
140
+25°C
120
120
+85°C
VDO (mV)
200
80
60
40
20
-40°C
0°C
+25°C
+85°C
4
5
6
7
C014
Figure 15. DROPOUT VOLTAGE vs INPUT VOLTAGE
(IOUT = 0.5 A, ANY-OUT, VBIAS = Open)
200
100
3
Input Voltage (V)
C013
Figure 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
(VIN = 5.5 V, ANY-OUT, VBIAS = Open)
VDO (mV)
+125°C
80
0
-40°C
100
+125°C
80
60
40
20
+125°C
0
0
0
1
2
3
4
5
6
Input Voltage (V)
7
0
1
2
3
4
5
6
Bias Voltage (V)
C015
Figure 16. DROPOUT VOLTAGE vs INPUT VOLTAGE
(IOUT = 2 A, ANY-OUT, VBIAS = Open)
7
C016
Figure 17. DROPOUT VOLTAGE vs BIAS VOLTAGE
(IOUT = 0.5 A, ANY-OUT, VIN = 1.1 V)
200
5
-40°C
-40°C
0°C
160
0°C
+25°C
+85°C
140
+25°C
120
+85°C
100
4
+125°C
IQ (mA)
180
VDO (mV)
-40°C
180
VDO (mV)
VDO (mV)
450
+125°C
80
3
2
60
40
1
20
0
0
0
1
2
3
4
Bias Voltage (V)
5
6
7
0
Figure 18. DROPOUT VOLTAGE vs BIAS VOLTAGE
(IOUT = 2 A, ANY-OUT, VIN = 1.1 V)
1
2
3
4
5
6
Input Voltage (V)
C017
7
C018
Figure 19. GROUND CURRENT vs INPUT VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, IOUT = 5 mA, VBIAS = Open)
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
5
5
4
-40°C
0°C
+25°C
+85°C
4
3
IGND (mA)
IQ (mA)
+125°C
2
3
2
1
1
0
0
-40°C
0°C
+25°C
+85°C
+125°C
0
1
2
3
4
5
6
Bias Voltage (V)
7
0
0.25
0.5
Figure 20. GROUND CURRENT vs BIAS VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, IOUT = 5 mA, VIN = 1.1 V)
0.75
1
1.25
1.5
1.75
Output Current (A)
C019
2
C020
Figure 21. GROUND CURRENT vs OUTPUT CURRENT
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.4 V, VBIAS = Open)
5
10
4
8
-40°C
0°C
+25°C
+85°C
3
ISHDN (µA)
IGND (mA)
+125°C
2
1
-40°C
0°C
+25°C
+85°C
6
4
2
+125°C
0
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
Output Current (A)
0
2
Figure 22. GROUND CURRENT vs OUTPUT CURRENT
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V, VBIAS = 3 V)
2
3
5
6
7
C022
Figure 23. SHUTDOWN CURRENT vs INPUT VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VBIAS = Open)
10
8
-40°C
0°C
+25°C
+85°C
9
8
7
ISS/NR (µA)
+125°C
6
4
6
5
4
3
2
2
1
0
-40°C
0°C
+25°C
+85°C
+125°C
0
0
1
2
3
4
Bias Voltage (V)
5
6
7
0
1
2
3
4
Input Voltage (V)
C023
Figure 24. SHUTDOWN CURRENT vs BIAS VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V)
10
4
Input Voltage (V)
10
ISHDN (µA)
1
C021
5
6
7
C024
Figure 25. SOFT-START CURRENT vs INPUT VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VBIAS = Open)
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TYPICAL CHARACTERISTICS (continued)
5
5
4
4
3
3
ICL (A)
ICL (A)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
2
2
-40°C
+25°C
-40°C
1
+125°C
+125°C
0
0
0
0.3
0.6
0.9
1.2
1.5
Output Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
Output Voltage (V)
C025
Figure 26. CURRENT LIMIT vs OUTPUT VOLTAGE
(VOUT(TARGET) = 1.5 V, ANY-OUT, VIN = 1.8 V, VBIAS = Open)
4
C025
Figure 27. CURRENT LIMIT vs OUTPUT VOLTAGE
(VOUT(TARGET) = 3.95 V, ANY-OUT, VIN = 4.25 V, VBIAS = Open)
5
5
4
4
3
3
ICL (A)
ICL (A)
+25°C
1
2
2
-40°C
+25°C
-40°C
1
+25°C
1
+125°C
+125°C
0
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Output Voltage (V)
0.8
0
0.1
0.2
Figure 28. CURRENT LIMIT vs OUTPUT VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V, VBIAS = 3 V)
0.3
0.4
0.5
0.6
0.7
Output Voltage (V)
C027
0.8
C028
Figure 29. CURRENT LIMIT vs OUTPUT VOLTAGE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V, VBIAS = 6.5 V)
1.2
1.6
1.4
1
1.2
1
VIN (V)
VIN (V)
0.8
0.6
0.8
0.6
0.4
0.4
VIN Decreasing
0.2
VIN Decreasing
0.2
VIN Increasing
VIN Increasing
0
0
-40 -25 -10
5
20
35
50
65
Temperature (C)
80
95
110 125
-40 -25 -10
Figure 30. INPUT UVLO THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VBIAS = 3.0 V)
5
20
35
50
65
80
95
110 125
Temperature (C)
C029
C030
Figure 31. INPUT UVLO THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VBIAS = Open)
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
3
1.2
2.85
1
2.7
0.8
2.4
VEN (V)
VBIAS (V)
2.55
2.25
2.1
0.6
0.4
1.95
1.8
VBIAS Increasing
1.65
VEN Decreasing
0.2
VBIAS Decreasing
VEN Increasing
1.5
0
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (C)
-40 -25 -10
5
20
35
50
65
80
95
Temperature (C)
C031
Figure 32. BIAS UVLO THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.1 V)
110 125
C032
Figure 33. ENABLE THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.4 V, VBIAS = Open)
1.2
0.1
0.075
1
0.05
0.025
IEN (µA)
VEN (V)
0.8
0.6
0
-0.025
0.4
-0.05
VEN Decreasing
0.2
-0.075
VEN Increasing
0
-0.1
-40 -25 -10
5
20
35
50
65
80
95
Temperature (C)
110 125
-40 -25 -10
Figure 34. ENABLE THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 6.5 V, VBIAS = Open)
35
50
65
80
95
110 125
C034
Figure 35. ENABLE CURRENT vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = VEN = 6.5 V, VBIAS =
Open)
1
0.8
-40°C
0°C
-40°C
0°C
+25°C
+85°C
+25°C
+85°C
0.8
+125°C
+125°C
0.6
VPG (V)
VPG (V)
20
Temperature (C)
1
0.4
0.2
0.6
0.4
0.2
0
0
0
0.5
1
1.5
IPG (mA)
2
2.5
3
0
0.5
1
1.5
IPG (mA)
C035
Figure 36. PG LOW VOLTAGE vs PG CURRENT
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 6.5 V, VBIAS = Open)
12
5
C033
2
2.5
3
C036
Figure 37. PG LOW VOLTAGE vs PG CURRENT
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.4 V, VBIAS = Open)
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
95
95
Low-to-High
94
High-to-Low
91
90
89
88
91
90
89
88
87
86
86
85
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (C)
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (C)
C037
Figure 38. PG THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 6.5 V, VBIAS = Open)
C038
Figure 39. PG THRESHOLD vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = 1.4 V, VBIAS = Open)
1
100
0.75
90
80
0.5
70
PSRR (dB)
0.25
IPG (µA)
92
87
85
0
-0.25
60
50
40
30
-0.5
20
-0.75
10
-1
0
-40 -25 -10
5
20
35
50
65
80
95
110 125
Temperature (C)
10
90
80
80
70
70
PSRR (dB)
100
60
50
40
Cnr = 0 nF
Io = 2 A
100
1k
100k
1M
C040
50
40
Cnr = 10 nF
20
Cnr = 100 nF
10
0
10k
60
Vin = 1.4 V
30
10
Io = 1.5 A
Figure 41. POWER-SUPPLY REJECTION vs CURRENT
(VOUT(TARGET) = 3.3 V, ANY-OUT, VIN = VEN = 3.8 V, VBIAS =
Open, COUT = 22 μF, CNR/SS = CFF = 10 nF)
90
20
Io = 1 A
Frequency (Hz)
100
30
Io = 0.1 A
C039
Figure 40. PG CURRENT vs TEMPERATURE
(VOUT(TARGET) = 0.8 V, ANY-OUT, VIN = VPG = 6.5 V, VBIAS =
Open)
PSRR (dB)
High-to-Low
93
92
%VOUT(NOM) (%)
%VOUT(NOM) (%)
93
Low-to-High
94
Vin =1.5 V
Vin = 2 V
Vin = 3 V
0
10
100
1k
10k
Frequency (Hz)
100k
1M
10
Figure 42. POWER-SUPPLY REJECTION vs CNR/SS
(VOUT(TARGET) = 3.3 V, ANY-OUT, VIN = VEN = 3.8 V, VBIAS =
Open, IOUT = 1.5 A, COUT = 22 μF, CFF = 10 nF)
100
1k
10k
100k
1M
Frequency (Hz)
C041
C042
Figure 43. POWER-SUPPLY REJECTION vs
INPUT VOLTAGE
(VOUT(TARGET) = 1.2 V, ANY-OUT, VBIAS = Open, IOUT = 1.5 A,
COUT = 22 μF, CNR/SS = CFF = 10 nF)
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
1000
1000
Vo = 3.95 V
Vo = 3.3 V
10
Cnr = 0 nF
100
1RLVH9¥+]
1RLVH9¥+]
100
VOUT = 0.8 V, VNOISE = 6 µVRMS
VOUT = 3.3 V, VNOISE = 10 µVRMS
VOUT = 3.95 V, VNOISE = 11 µVRMS
BW RMSNOISE (10Hz, 100kHz)
Vo = 0.8 V
1
0.1
0.01
10
Cnr = 100 nF
1
0.1
0.01
0.001
0.001
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
(VIN
Cnr = 10 nF
CNR = 0 nF, VNOISE = 20 µVRMS
CNR = 10 nF, VNOISE = 10 µVRMS
CNR = 100 nF, VNOISE = 8 µVRMS
BW RMSNOISE (10Hz, 100kHz)
10
100
Figure 44. SPECTRAL NOISE DENSITY vs
OUTPUT VOLTAGE
= VOUT(TARGET) + 0.5 V, ANY-OUT, VBIAS = Open, IOUT =
1.5 A, COUT = 22 μF, CNR/SS = CFF = 10 nF)
1k
10k
100k
1M
Frequency (Hz)
C043
(VIN
10M
C044
Figure 45. SPECTRAL NOISE DENSITY vs CNR/SS
= 3.8 V, VOUT(TARGET) = 3.3 V, ANY-OUT, VBIAS = Open,
IOUT = 1.5 A, COUT = 22 μF, CFF = 10 nF)
1000
Cff = 0 nF
1RLVH9¥+]
100
Cff = 10 nF
10
CFF = 0 nF, VNOISE = 18 µVRMS
CFF = 10 nF, VNOISE = 10 µVRMS
CFF = 100 nF, VNOISE = 8 µVRMS
BW RMSNOISE (10Hz, 100kHz)
PG (1V/div)
Cff = 100 nF
IOUT (500 mA/div)
1
0.1
VOUT (50 mV/div)
VIN = 3.85V
VOUT = 3.3V
IOUT = 100mA to 1Ato 100mA @ 1A/us
Co = 22uF
0.01
0.001
10
100
1k
10k
100k
1M
Frequency (Hz)
Time (2 μs/div)
10M
C045
Figure 46. SPECTRAL NOISE DENSITY vs CSS/NR
(VIN = 3.8 V, VOUT(TARGET) = 3.3 V, ANY-OUT, VBIAS = Open,
IOUT = 1.5 A, COUT = 22 μF, CNR/SS = 10 nF)
EN (0.5V/div)
Figure 47. LOAD TRANSIENT RESPONSE
EN (0.5V/div)
VOUT (200 mV/div)
PG (200 mV/div)
VIN = 1.4V
VOUT = 0.8V
Cnr = 0nF
VOUT (200 mV/div)
PG (200 mV/div)
Time (20μs/div)
Time (500 μs/div)
Figure 48. START-UP (CNR = 0 nF)
14
VIN = 1.4V
VOUT = 0.8V
Cnr = 10nF
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Figure 49. START-UP (CNR = 10 nF)
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, {1.1 V ≤ VIN < 1.4 V and 3.0 V ≤ VBIAS ≤ 6.5 V} or {VIN ≥ 1.4 V and VBIAS open}(1), VIN ≥ VOUT(TARGET) + 0.3 V,
VOUT(TARGET) = 0.8 V, OUT connected to 50 Ω to GND, VEN = 1.1 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 10 nF, and PG pin
pulled up to VIN with 100 kΩ, unless otherwise noted.
VIN = 1.4 V to 6 V to 1.4 V at 1 V/ms
VOUT = 0.8 V, CNR = CFF = 10 nF
IO = 2 A
VOUT
(20 mV/div)
VIN
(2 V/div)
Time (5 μs/div)
Figure 50. LINE TRANSIENT
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APPLICATION INFORMATION
TYPICAL APPLICATION CIRCUIT
Output voltage is set by grounding the appropriate control pins, as shown in Figure 51. When grounded, all
control pins add a specific voltage on top of the internal reference voltage (VREF = 0.8 V).
For example, when grounding the 400-mV pin, the voltage value of 400 mV is added to the 0.8-V internal
reference voltage for VOUT(NOM) equal to 1.2 V; alternatively, when grounding the 200 mV pin, the voltage value of
200 mV is added to the 0.8-V internal reference voltage for VOUT(NOM) equal to 1.0 V, as described in Equation 1
and Equation 2.
1.1 V ≤ VIN ≤ 1.4 V
above 1.4 V
IN
IN
PG
TPS7A8300
CIN
NR/SS
CNR/SS
OUT
PG
TPS7A8300
CIN
1.2 V = 0.8 VREF
+ 400 mV
OUT
NR/SS
COUT
SNS
CNR/SS
BIAS
COUT
SNS
CFF
CFF
EN
1.0 V = 0.8 VREF
+ 200 mV
EN
FB
1.6V
FB
1.6V
BIAS
CBIASS
800mV
GND
50mV
800mV
400mV
400mV
GND
100mV 200mV
50mV
Typical Application
VIN ≥ 1.4 V
100mV 200mV
Typical Application
1.1 V ≤ VIN < 1.4 V
Figure 51. Maximize PSRR Performance and Minimize RMS Noise
VOUT(NOM) = VREF + 0.4 V = 0.8 V + 0.4 V = 1.2 V
VOUT(NOM) = VREF + 0.2 V = 0.8 V + 0.2 V = 1.0 V
(1)
(2)
ANY-OUT PROGRAMMABLE OUTPUT VOLTAGE
The TPS7A8300 does not require external resistors to set output voltage, which is typical of low-dropout voltage
regulators (LDOs), but uses device pins 5, 6, 7, 9, 10, and 11 to program the regulated output voltage. Each pin
is either connected to ground (active) or is left open (or floating). ANY-OUT programming is set by Equation 3 as
the sum of the internal reference voltage (VREF = 0.8 V) plus the accumulated sum of the respective voltages
assigned to each active pin; that is, 50 mV (pin 5), 100 mV (pin 6), 200 mV (pin 7), 400 mV (pin 9), 800 mV (pin
10), or 1.6 V (pin 11). Table 1 summarizes these voltage values associated with each active pin setting for
reference. By leaving all program pins open, or floating, the output is thereby programmed to the minimum
possible output voltage equal to VREF.
VOUT = VREF + (S ANY-OUT Pins to Ground)
(3)
Table 1. ANY-OUT Programmable Output Voltage
ANY-OUT PROGRAM PINS (Active Low)
16
ADDITIVE OUTPUT VOLTAGE LEVEL
Pin 5 (50 mV)
50 mV
Pin 6 (100 mV)
100 mV
Pin 7 (200 mV)
200 mV
Pin 9 (400 mV)
400 mV
Pin 10 (800 mV)
800 mV
Pin 11 (1.6 V)
1.6 V
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SBVS197C – MAY 2013 – REVISED JULY 2013
Table 2 shows a full list of target output voltages and corresponding pin settings. The voltage setting pins have a
binary weight; therefore, the output voltage can be programmed to any value from 0.8 V to 3.95 V in 50-mV
steps.
There are several alternative ways to set the output voltage. The program pins can be driven using external
general-purpose input/output pins (GPIOs), manually connected to ground using 0-Ω resistors (or left open), or
hardwired by the given layout of the printed circuit board (PCB) to set the ANY-OUT voltage.
NOTE
For output voltages greater than 3.95 V, use a traditional adjustable configuration (see the
Adjustable Operation section).
Table 2. User-Configurable Output Voltage Settings
VOUT(TARGET)
(V)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
VOUT(TARGET)
(V)
50 mV
100 mV
200 mV
400 mV
800 mV
1.6 V
0.80
Open
Open
Open
Open
Open
Open
2.40
Open
Open
Open
Open
Open
GND
0.85
GND
Open
Open
Open
Open
Open
2.45
GND
Open
Open
Open
Open
GND
0.90
Open
GND
Open
Open
Open
Open
2.50
Open
GND
Open
Open
Open
GND
0.95
GND
GND
Open
Open
Open
Open
2.55
GND
GND
Open
Open
Open
GND
1.00
Open
Open
GND
Open
Open
Open
2.60
Open
Open
GND
Open
Open
GND
1.05
GND
Open
GND
Open
Open
Open
2.65
GND
Open
GND
Open
Open
GND
1.10
Open
GND
GND
Open
Open
Open
2.70
Open
GND
GND
Open
Open
GND
1.15
GND
GND
GND
Open
Open
Open
2.75
GND
GND
GND
Open
Open
GND
1.20
Open
Open
Open
GND
Open
Open
2.80
Open
Open
Open
GND
Open
GND
1.25
GND
Open
Open
GND
Open
Open
2.85
GND
Open
Open
GND
Open
GND
1.30
Open
GND
Open
GND
Open
Open
2.90
Open
GND
Open
GND
Open
GND
1.35
GND
GND
Open
GND
Open
Open
2.95
GND
GND
Open
GND
Open
GND
1.40
Open
Open
GND
GND
Open
Open
3.00
Open
Open
GND
GND
Open
GND
1.45
GND
Open
GND
GND
Open
Open
3.05
GND
Open
GND
GND
Open
GND
1.50
Open
GND
GND
GND
Open
Open
3.10
Open
GND
GND
GND
Open
GND
1.55
GND
GND
GND
GND
Open
Open
3.15
GND
GND
GND
GND
Open
GND
1.60
Open
Open
Open
Open
GND
Open
3.20
Open
Open
Open
Open
GND
GND
1.65
GND
Open
Open
Open
GND
Open
3.25
GND
Open
Open
Open
GND
GND
1.70
Open
GND
Open
Open
GND
Open
3.30
Open
GND
Open
Open
GND
GND
1.75
GND
GND
Open
Open
GND
Open
3.35
GND
GND
Open
Open
GND
GND
1.80
Open
Open
GND
Open
GND
Open
3.40
Open
Open
GND
Open
GND
GND
1.85
GND
Open
GND
Open
GND
Open
3.45
GND
Open
GND
Open
GND
GND
1.90
Open
GND
GND
Open
GND
Open
3.50
Open
GND
GND
Open
GND
GND
1.95
GND
GND
GND
Open
GND
Open
3.55
GND
GND
GND
Open
GND
GND
2.00
Open
Open
Open
GND
GND
Open
3.60
Open
Open
Open
GND
GND
GND
2.05
GND
Open
Open
GND
GND
Open
3.65
GND
Open
Open
GND
GND
GND
2.10
Open
GND
Open
GND
GND
Open
3.70
Open
GND
Open
GND
GND
GND
2.15
GND
GND
Open
GND
GND
Open
3.75
GND
GND
Open
GND
GND
GND
2.20
Open
Open
GND
GND
GND
Open
3.80
Open
Open
GND
GND
GND
GND
2.25
GND
Open
GND
GND
GND
Open
3.85
GND
Open
GND
GND
GND
GND
2.30
Open
GND
GND
GND
GND
Open
3.90
Open
GND
GND
GND
GND
GND
2.35
GND
GND
GND
GND
GND
Open
3.95
GND
GND
GND
GND
GND
GND
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ADJUSTABLE OPERATION
The adjustable version of the device has an output voltage range of 0.8 V to 5 V. The nominal output voltage of
the device is set by two external resistors, as shown in Figure 52.
VIN
VOUT
OUT
IN
CIN
10 mF
R1
EN
CNR/SS
10 nF
Device
NR
FB
R2
GND
Where:
COUT
22 mF
VOUT
³ 5 mA, and
R1 + R2
R 1 = R2
VOUT
-1
VREF
Figure 52. Adjustable Operation for Maximum AC Performance
R1 and R2 can be calculated for any output voltage range using Equation 4. This resistive network must provide a
current equal to or greater than 5 μA for optimum noise performance.
VOUT
VOUT
³ 5 mA
R1 = R2
- 1 , where
R1 + R2
VREF
(4)
If greater voltage accuracy is required, take into account the output voltage offset contributions because of the
feedback pin current and use 0.1% tolerance resistors.
Table 3 shows the resistor combination needed to achieve a few of the most common rails using commerciallyavailable, 0.1%-tolerance resistors to maximize nominal voltage accuracy while abiding to the formula shown in
Equation 4.
Table 3. Recommended Feedback-Resistor Values
(1)
FEEDBACK RESISTOR VALUES (1)
VOUT(TARGET)
(V)
R1 (kΩ)
R2 (kΩ)
1.00
2.55
10.2
1.20
5.9
11.8
1.50
9.31
10.7
1.80
18.7
15
1.90
15.8
11.5
2.50
24.3
11.5
3.00
31.6
11.5
3.30
35.7
11.5
5.00
105
20
R1 is connected from OUT to FB; R2 is connected from FB to GND.
CAPACITOR RECOMMENDATION
The TPS7A8300 is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the
input, output, and at the noise-reduction pin (NR, pin 13). Multilayer ceramic capacitors have become the
industry standard for these types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and COG-rated dielectric materials provide relatively good
capacitive stability across temperature, whereas the use of Y5V-rated capacitors is discouraged precisely
because the capacitance varies so widely. In all cases, ceramic capacitance varies a great deal with operating
voltage and temperature and the design engineer should be aware of these characteristics. As a rule of thumb,
ceramic capacitors are recommended to be derated by 50%. To compensate for this derating, increase capacitor
size by 100%. The input and output capacitors recommended herein account for a capacitance derating of 50%.
18
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Attention should be given to the input capacitance to minimize transient input droop during load current steps.
Input capacitances of 10 µF or greater provide the desired effect and do not affect stability. However, note that
simply using large ceramic input capacitances can also cause unwanted ringing at the output if the input
capacitor (in combination with the wire-lead inductance) creates a high-Q peaking effect during transients. For
example, a 5-nH lead inductance and a 10-µF input capacitor form an LC filter with a resonance frequency of
712 kHz that is near the edge of the control loop bandwidth. Short, well-designed interconnect leads to the upstream supply minimize this effect without adding damping. Damping of unwanted ringing can be accomplished
by using a tantalum capacitor, with a few hundred milliohms of ESR, in parallel with the ceramic input capacitor.
Input and Output Capacitor Requirements (CIN and COUT)
The TPS7A8300 is designed and characterized for operation with ceramic capacitors of 22 µF or greater at the
output and 10 µF at the input. Note especially that input and output capacitances should be located as near as
practical to the respective input and output pins.
Noise-Reduction and Soft-Start Capacitor (CNR/SS)
The TPS7A8300 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CNR/SS).This soft-start eliminates power-up initialization problems when powering field-programmable
gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the
output also reduces peak inrush current during start-up, minimizing start-up transients to the input power bus.
To achieve a linear and monotonic start-up, the TPS7A8300 error amplifier tracks the voltage ramp of the
external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on
the soft-start charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VNR/SS).
Soft-start ramp time can be calculated with Equation 5.
tSS = (VNR/SS × CNR/SS) / INR/SS
(5)
For low-noise applications, the noise-reduction capacitor (connected to the NR/SS pin of the LDO) forms an RC
filter for filtering out noise that might ordinarily be amplified by the control loop and appear on the output voltage.
For low-noise applications, a 10-nF to 1-µF CNR/SS is recommended.
Feed-Forward Capacitor (CFF)
Although a feed-forward capacitor (CFF), from the FB pin to the OUT pin is not required to achieve stability, TI
recommends using a 10-nF feed-forward capacitor in low-noise applications to maximize ac performance.
INTERNAL CURRENT LIMIT (ICL)
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate at a steady-state current limit. During a current-limit event, the LDO sources
constant current. Therefore, the output voltage falls while load impedance decreases. Note also that when a
current limit occurs while the resulting output voltage is low, excessive power may be dissipated across the LDO,
resulting in a thermal shutdown of the output.
A foldback feature limits the short-circuit current to protect the regulator from damage under all load conditions. If
OUT is forced below 0 V before EN goes high, the device may not start up. In applications that function with both
a positive and negative voltage supply, there are several ways to ensure proper start-up:
• The TPS7A8300 should be enabled first and disabled last.
• Delaying the EN voltage with respect to IN voltage allows the internal pull-down resistor to discharge any
residual voltage at OUT. If a faster discharge rate is required, an external resistor from OUT to GND may be
used.
DROPOUT VOLTAGE (VDO)
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output
voltage (VDO = VIN – VOUT). However, in the Electrical Characteristics, VDO is defined as the VIN – VOUT voltage at
the rated current (IRATED), where the main current pass-FET is fully on in the ohmic region of operation and is
characterized by the classic RDS(ON) of the FET. VDO indirectly specifies a minimum input voltage above the
nominal programmed output voltage at which the output voltage is expected to remain within its accuracy
boundary. If the input falls below this VDO limit (VIN < VOUT + VDO), then the output voltage decreases in order to
follow the input voltage.
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Dropout voltage is always determined by the RDS(ON) of the main pass-FET. Therefore, if the LDO operates below
the rated current, then the VDO for that current scales accordingly. The RDS(ON) for the TPS7A8300 can be
calculated using Equation 6:
VDO
RDS(ON) =
IRATED
(6)
OUTPUT VOLTAGE ACCURACY
Output voltage accuracy specifies minimum and maximum output voltage error, relative to the expected nominal
output voltage stated as a percent. This accuracy error typically includes the errors introduced by the internal
reference and the load and line regulation across the full range of rated load and line operating conditions over
temperature, unless otherwise specified by the Electrical Characteristics. Output voltage accuracy also accounts
for all variations between manufacturing lots.
POWER-GOOD FUNCTION
The TPS7A8300 has a power-good function that works by toggling the state of the PG output pin. When the
output voltage falls below the PG threshold voltage (VIT(PG)), the PG pin open-drain output engages (low
impedance to GND). When the output voltage exceeds the VIT(PG) threshold by an amount greater than VHYS(PG),
the PG pin becomes high-impedance. By connecting a pull-up resistor to an external supply, any downstream
device can receive PG as a logic signal. Make sure that the external pull-up supply voltage results in a valid logic
signal for the receiving device or devices. Use a pull-up resistor from 10 kΩ to 100 kΩ.
The power-good function is not valid when employing the feed-forward capacitor (CFF).
START-UP
Enable (EN) and Undervoltage Lockout (UVLO)
The TPS7A8300 only turns on when both EN and UVLO are above the respective voltage thresholds. The UVLO
circuit monitors input and bias voltage (VIN and VBIAS, respectively) to prevent device turn-on before VIN and VBIAS
rises above the lockout voltage. The UVLO circuit also causes a shutdown when VIN and VBIAS falls below
lockout. The EN signal allows independent logic-level turn-on and shutdown of the LDO when the input voltage is
present. EN can be connected directly to VIN if independent turn-on is not needed.
Soft-Start and Inrush Current
Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO have
achieved threshold voltage. The noise-reduction capacitor serves a dual purpose of both governing output noise
reduction and programming the soft-start ramp during turn-on.
Inrush current is defined as the current into the LDO at the IN pin during the time of the turn-on ramp up. Inrush
current then consists primarily of the sum of load and charge current to the output capacitor. This current is
difficult to measure because the input capacitor must be removed, which is not recommended. However, this
soft-start current can be estimated by Equation 7:
VOUT(t)
COUT ´ dVOUT(t)
IOUT(t) =
+
RLOAD
dt
where:
•
•
•
20
VOUT(t) is the instantaneous output voltage of the turn-on ramp,
dVOUT(t)/dt is the slope of the VOUT ramp, and
RLOAD is the resistive load impedance.
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SBVS197C – MAY 2013 – REVISED JULY 2013
AC PERFORMANCE
LDO ac performance is typically understood to include power-supply rejection ratio, load step transient response,
and output noise. These metrics are primarily a function of open-loop gain and bandwidth, phase margin, and
reference noise.
Power-Supply Ripple Rejection (PSRR)
PSRR is a measure of how well the LDO control loop rejects ripple noise from the input source to make the dc
output voltage as noise-free as possible across the frequency spectrum (usually 10 Hz to 10 MHz). Even though
PSRR is therefore a loss in noise signal amplitude (the output ripple relative to the input ripple), the PSRR
reciprocal is plotted in the Electrical Characteristics as a positive number in decibels (dB) for convenience.
Equation 8 gives the PSRR calculation as a function of frequency where input noise voltage [VS(IN)(f)] and output
noise voltage [VS(OUT)(f)] are understood to be purely ac signals.
VS(IN)(f)
PSRR (dB) = 20 Log10
VS(OUT)(f)
(8)
Noise that couples from the input to the internal reference voltage for the control loop is also a primary
contributor to reduced PSRR magnitude and bandwidth. This reference noise is greatly filtered by the noisereduction capacitor at the NR pin of the LDO in combination with an internal filter resistor (RSS) for optimal
PSRR.
The LDO is often employed not only as a dc-dc regulator, but also to provide exceptionally clean power-supply
voltages that are free of noise and ripple to power-sensitive system components. This usage is especially true for
the TPS7A8300.
Load-Step Transient Response
The load-step transient response is the output voltage response by the LDO to a step change in load current,
whereby output voltage regulation is maintained. The worst-case response is characterized for a load step of
10 mA to 2 A (at 1 A per microsecond) and shows a classic critically-damped response of a very stable system.
The voltage response shows a small dip in the output voltage when charge is initially depleted from the output
capacitor and then the output recovers as the control loop adjusts itself. The depth of charge depletion
immediately after the load step is directly proportional to the amount of output capacitance. However, to some
extent, recovery speed is inversely proportional to that same output capacitance. In other words, larger output
capacitances act to decrease any voltage dip or peak occurring during a load step but also decrease the controlloop bandwidth, thereby slowing response.
The worst-case off-loading step characterization occurs when the current step transitions from 2 A to 0 mA.
Initially, the LDO loop cannot respond fast enough to prevent a small increase in output voltage charge on the
output capacitor. Because the LDO cannot sink charge current, the control loop must turn off the main pass-FET
to wait for the charge to deplete, thus giving the off-load step its typical monotonic decay (which appears
triangular in shape).
Noise
The TPS7A8300 is designed, in particular, for system applications where minimizing noise on the power-supply
rail is critical to system performance. This scenario is the case for phase-locked loop (PLL)-based clocking
circuits (for instance, where minimum phase noise is all important), or in-test and measurement systems where
even small power-supply noise fluctuations can distort instantaneous measurement accuracy.
LDO noise is defined as the internally-generated intrinsic noise created by the semiconductor circuits alone. This
noise is the sum of various types of noise (such as shut noise associated with current-through-pin junctions,
thermal noise caused by thermal agitation of charge carriers, flicker noise, or 1/f noise that is a property of
resistors and dominates at lower frequencies as a function of 1/f, burst noise, and avalanche noise).
To calculate the LDO RMS output noise, a spectrum analyzer must first measure the spectral noise across the
bandwidth of choice (typically 10 Hz to 100 kHz in units of µV/√Hz). RMS noise is then calculated in the usual
manner as the integrated square root of the squared spectral noise over the band, then averaged by the
bandwidth.
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Behavior when transitioning from steady dropout into regulation
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO,
right after being in a normal regulation state, but not during startup), the pass device is driven as hard as
possible, while the control loop is out of balance. During the normal time it takes the device to regain regulation,
VIN ≥ VOUT(NOM) + VDO, VOUT overshoots if the input voltage slew rate is 0.1 V/µs or faster.
THERMAL INFORMATION
Thermal Protection
The TPS7A8300 contains a thermal shutdown protection circuit to turn off the output current when excessive
heat is dissipated in the LDO. Thermal shutdown occurs when the thermal junction temperature (TJ) of the main
pass-FET exceeds +160°C (typical). Thermal shutdown hysteresis assures that the LDO again resets (turns on)
when the temperature falls to +140°C (typical). The thermal time-constant of the semiconductor die is fairly short,
and thus the output oscillates on and off at a high rate when thermal shutdown is reached until power dissipation
is reduced.
For reliable operation, the junction temperature should be limited to a maximum of +125°C. To estimate the
thermal margin in a given layout, increase the ambient temperature until the thermal protection shutdown is
triggered using worst-case load and highest input voltage conditions. For good reliability, thermal shutdown
should occur at least +45°C above the maximum expected ambient temperature condition for the application.
This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A8300 is designed to protect against thermal overload conditions.
The circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A8300 into thermal
shutdown degrades device reliability.
Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
should be as free as possible of other heat-generating devices that can cause added thermal stresses.
Power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. PD can
be calculated using Equation 9:
PD = (VOUT - VIN) ´ IOUT
(9)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input voltage necessary for output
regulation to be obtained.
The primary heat conduction path for the QFN (RGW) package is through the thermal pad to the PCB. The
thermal pad should be soldered to a copper pad area under the device. This pad area should then contain an
array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(θJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to
Equation 10.
TJ = TA + (qJA ´ PD)
(10)
22
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Unfortunately, this thermal resistance (θJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The θJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area and is to be used only as a relative measure of package thermal performance. Note that
for a well-designed thermal layout, θJA is actually the sum of the QFN package junction-to-case (bottom) thermal
resistance (θJCbot) plus the thermal resistance contribution by the PCB copper. When θJCbot is known, one can
estimate the amount of heat-sinking area required for a given θJA, refer to Figure 53. θJCbot can be found in the
Thermal Information table.
120
100
qJA (°C/W)
80
60
qJA (RGW)
40
20
0
0
1
2
3
4
5
7
6
8
9
10
2
Board Copper Area (in )
2
NOTE: θJA value at a board size of 9-in (that is, 3-in × 3-in) is a JEDEC standard.
Figure 53. θJA vs Board Size
Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO while in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of copper-spreading area. The key thermal metrics (ΨJT and ΨJB)
are given in the Thermal Information table and are used in accordance with Equation 11.
YJT: TJ = TT + YJT ´ PD
YJB: TJ = TB + YJB ´ PD
where:
•
•
•
PD is the power dissipated as explained in Equation 9,
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge.
(11)
BOARD LAYOUT
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to each other as possible, connected by a wide, component-side,
copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and
negatively affects system performance. This grounding and layout scheme minimizes inductive parasitics, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability.
A ground reference plane is also recommended and should be either embedded in the PCB itself or located on
the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink) heat from the LDO device
when connected to the PowerPAD™. In most applications, this ground plane is necessary to meet thermal
requirements.
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REVISION HISTORY
NOTE: Page numbers for previous revision may differ from page numbers in the current version.
Changes from Revision B (July 2013) to Revision C
Page
•
Changed text in Feed-Forward Capacitor subsection ........................................................................................................ 19
•
Changed Power-Good section ............................................................................................................................................ 20
•
Deleted PG Functionality section ........................................................................................................................................ 20
Changes from Revision A (June 2013) to Revision B
•
Changed from product preview to production data ............................................................................................................... 1
Changes from Original (May 2013) to Revision A
•
24
Page
Page
Changed product preview data sheet ................................................................................................................................... 1
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TPS7A8300RGRR
PREVIEW
VQFN
RGR
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PA9Q
TPS7A8300RGRT
PREVIEW
VQFN
RGR
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
PA9Q
TPS7A8300RGWR
ACTIVE
VQFN
RGW
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PZGM
TPS7A8300RGWT
ACTIVE
VQFN
RGW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PZGM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS7A8300RGWR
Package Package Pins
Type Drawing
VQFN
RGW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.5
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A8300RGWR
VQFN
RGW
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
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