TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com 1.5-A, Low-Voltage LDO Regulator with Dual Input Voltages FEATURES DESCRIPTION • • The TPS740xx is a wide bandwidth, very low-dropout, 1.5-A voltage regulator ideal for powering microprocessors. 23 • • • • • • • • • • Small Consumption Current: 3 mA Maximum Input Voltage Range: – VIN: 1.2 V to 5.5 V – VBIAS: 2.9 V to 5.5 V Stable with Any Output Capacitance: ≥ 2.2 μF ±1% Initial Accuracy Maximum Dropout Voltage (VIN – VOUT): 300 mV Over Temperature Adjustable Output Voltage: Down to 0.9 V Ultra-Fast Transient Response Excellent Line and Load Regulation Logic-Controlled Shutdown Option Thermal Shutdown and Current Limit Protection Power 8-Pin Mini Small-Outline Package (MSOP) and Jr S-PAK™ packages. Junction Temperature Range: –40°C to +125°C APPLICATIONS • • • • • • Graphics Processors PC Add-In Cards Microprocessors Low-Voltage Digital ICs High-Efficiency Linear Power Supplies Switch-Mode Power-Supply Post Regulation The TPS740xx uses a bias input supply to allow very low voltage of a main input supply. The main input supply operates from 1.2 V to 5.5 V and the bias input supply requires between 3.0 V to 5.5 V for proper operation. The TPS740xx offers adjustable output voltages down to 0.9 V. The TPS740xx requires a minimum of output capacitance. A small 2.2-μF ceramic capacitor is enough for its stability. The TPS740xx is available in an 8-pin power MSOP package and a 5-pin Jr S-PAK. Its operating temparature range is –40°C to +125°C. 100 90 VDO (VIN - VOUT) (mV) 1 80 +125°C 70 60 50 40 +25°C 30 20 -40°C 10 0 0 0.5 1.0 1.5 IOUT (A) VIN IN TPS74001 COUT FB R2 BIAS CBIAS Dropout Voltage R1 CIN VBIAS VOUT OUT GND Typical Application Circuit (Adjustable) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Jr S-PAK is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOUT (2) PRODUCT TPS740xx yyy z (1) (2) (3) XX is nominal output voltage (for example, 12 = 1.2 V, 15 = 1.5 V, 01 = Adjustable). (3) YYY is package designator. Z is package quantity. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Fixed output voltages of 1.2 V is available; minimum order quantities may apply. Contact factory for details and availability. For fixed 0.9-V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE Voltage Current (2) (3) 2 MAX UNIT –0.3 +6.0 V EN, FB, OUT –0.3 VBIAS + 0.3 (2) V OUT Electrostatic discharge rating (3) (1) MIN IN, BIAS Internally limited Human body model (HBM, JESD22-A114A) Charged device model (CDM, JESD22-C101B.01) A 2 kV 500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The absolute maximum rating is VBIAS + 0.3 V or +6.0 V, whichever is smaller. ESD testing is performed according to the respective JESD22 JEDEC standard. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com THERMAL INFORMATION TPS74001DGK THERMAL METRIC (1) (2) DGK (4 pin short) DPT 8 PINS 5 PINS 136.9 30.0 Junction-to-ambient thermal resistance (4) θJA TPS74001DPT (3) (5) θJCtop Junction-to-case (top) thermal resistance 35.3 15.3 θJB Junction-to-board thermal resistance (6) 68.0 14.4 ψJT Junction-to-top characterization parameter (7) 0.9 0.6 ψJB Junction-to-board characterization parameter (8) 67.8 14.4 θJCbot Junction-to-case (bottom) thermal resistance (9) n/a 5.8 (1) (2) (3) (4) (5) (6) (7) (8) (9) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. Thermal data for the DGK and DPT packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) DPT only, the exposed pad is connected to the PCB ground layer through a 8 × 8 thermal via array. (b) i. DPT: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. ii. DGK: The top copper layer has a dedicated pattern of 5% copper coverage and the bottom copper layer has another decicated pattern of 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 3 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VBIAS = VOUT + 2.0 V, VIN = VOUT + 1 V, COUT = 10 μF, following Recommended Resistor Values, and VEN = 1.1 V, unless otherwise noted. Typical values are at TJ = +25°C. TPS74001 (adjustable output voltage) is tested at VOUT = 0.9 V. TPS740xx PARAMETER TEST CONDITIONS VIN Input voltage range VBIAS Bias pin voltage range MAX UNIT 1.2 TYP 5.5 V 2.9 5.5 V TJ = 25°C –1 1 % TJ = –40°C to +125°C –2 2 % VOUT/VIN Line regulation VIN = VOUT + 1 V to 5.5 V –0.1 0.1 %/V VOUT/IOUT Load regulation ILOAD = 0 mA to 1.5 A VOUT Accuracy (1) VDO VIN dropout voltage (2) VBIAS dropout voltage (2) IGND Ground pin current ISHDN (3) Shutdown supply current (IGND) IBIAS Bias pin current ICL Current limit mV ILOAD = 1.5 A, VIN = VBIAS 1.3 1.6 V ILOAD = 1.5 A 2 3 mA Fixed output version only. VEN ≤ 0.4 V, TJ = –40°C to +85°C, VOUT = 0 V 1 5 μA ILOAD = 1.5 A VOUT = 80% × VOUT (NOM) IEN Enable pin current VEN = 1.5 V TSD Thermal shutdown temperature 2 mA 1.6 6.0 A 1.1 5.5 V 0 0.4 V 1 μA +125 °C 0.1 –40 Shutdown, temperature increasing +165 Reset, temperature decreasing +140 VREF Reference voltage (1) (2) (3) % 300 RLOAD = 1 kΩ to GND TJ 1.5 100 VEN, LO Enable input low level Operating junction temperature 0.01 ILOAD = 1.5 A VEN, HI Enable input high level 4 MIN 0.882 0.9 °C 0.918 V Adjustable output voltage devices: resistor tolerance is not taken into account. Dropout is defined as the voltage from the input voltage to VOUT when VOUT is 3% below nominal. IGND(MAX) = 3 mA includes the maximum 2 mA of IBIAS. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS Adjustable Output Voltage Version IN Current Limit BIAS UVLO OUT Thermal Limit VOUT R1 0.9V Reference FB R2 GND Figure 1. Fixed Output Voltage Version IN Current Limit BIAS UVLO OUT Thermal Limit VOUT R1 0.9V Reference EN Hysteresis and Deglitch R2 GND Figure 2. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 5 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com PIN CONFIGURATION DPT PACKAGE Jr S-PAK (TOP VIEW) DGK PACKAGE MSOP-8 (TOP VIEW) EN/FB 1 8 GND BIAS 2 7 GND IN 3 6 GND OUT 4 5 GND 1 2 3 4 5 EN/FB BIAS GND IN OUT TAB Table 1. TERMINAL FUNCTIONS TERMINAL DGK (MSOP-8) DPT (Jr S-PAK) EN 1 1 Enable pin; fixed output voltage version only. Driving this pin high enables the regulator; driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. FB 1 1 Feedback pin; adjustable output voltage version only. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. BIAS 2 2 Bias input voltage for error amplifier, reference, and internal control circuits. IN 3 4 Input to the device. OUT 4 5 Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability. GND 5-8 3 Ground TAB 6 DESCRIPTION NAME TAB Internally connected to ground Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. POWER-SUPPLY RIPPLE REJECTION (INPUT SUPPLY) POWER-SUPPLY RIPPLE REJECTION (BIAS SUPPLY) 80 80 70 70 60 60 50 50 PSRR (dB) PSRR (dB) TPS74001 40 VBIAS = 3.3 V VIN = 1.8 V VOUT = 1.0 V IOUT = 1.5 A COUT = 2.2-mF Ceramic 30 20 10 40 VBIAS = 3.3 V VIN = 1.8 V VOUT = 1.0 V IOUT = 1.5 A COUT = 2.2-mF Ceramic 30 20 10 0 10 1k 100 10 k 10 1M 100 k 1k 100 Frequency (Hz) 10 k 1M 100 k Frequency (Hz) Figure 3. Figure 4. DROPOUT VOLTAGE (INPUT SUPPLY) DROPOUT VOLTAGE (BIAS SUPPLY) 300 1.8 VBIAS = 5 V VOUT = 1.0 V VIN = 2.5 V VOUT = 1.5 V 1.6 Dropout Voltage (V) 250 Dropout Voltage (mV) TPS74001 0 200 150 100 1.4 1.2 1 0.8 0.6 0.4 50 0.2 0 0 0 200 400 600 800 1000 1200 1400 0 1600 200 400 1000 1200 1400 Figure 6. DROPOUT VOLTAGE vs TEMPERATURE (INPUT SUPPLY) DROPOUT VOLTAGE vs TEMPERATURE (BIAS SUPPLY) 1600 2 VBIAS = 5 V IOUT = 1.5 A VOUT = 1.5 V 1.8 1.6 Dropout Voltage (V) Dropout Voltage (mV) 300 800 Figure 5. 400 350 600 Output Current (mA) Output Current (mA) 250 200 150 100 VIN = 2.5 V IOUT = 1.5 A VOUT = 1.5 V 1.4 1.2 1 0.8 0.6 0.4 50 0.2 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Temperature (°C) 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 7 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. DROPOUT CHARACTERISTICS (INPUT VOLTAGE) 1.6 1.6 VBIAS = 5 V VOUT = 1.5 V 1.4 VIN = 2.5 V VOUT = 1.5 V 1.4 1.2 Output Voltage (V) Output Voltage (V) DROPOUT CHARACTERISTICS (BIAS VOLTAGE) 1 0.8 0.6 0.4 1.2 1 0.8 0.6 0.4 IOUT = 10 mA 0.2 IOUT = 10 mA 0.2 IOUT = 1.5 A 0 IOUT = 1.5 A 0 0 0.5 1 1.5 0 2.5 2 1 2 Input Voltage (V) LOAD REGULATION MAXIMUM BIAS CURRENT vs BIAS VOLTAGE (1) 7 300 VBIAS = 5 V VIN = 2.5 V 1.5 TPS74001 1.495 Reference Device A VFB = 0 V IOUT = 1.5 A VIN = 2.5 V 250 Bias Current (mA) 1.505 200 150 100 50 1.49 0 1.485 0 200 400 600 800 1000 1200 1400 3 1600 3.5 4 4.5 5 5.5 6 6.5 Bias Voltage (V) Output Current (mA) Figure 11. Figure 12. MAXIMUM BIAS CURRENT vs TEMPERATURE BIAS CURRENT vs TEMPERATURE 45 300 VBIAS = 5 V VFB = 0 V VIN = 2.5 V 40 35 Bias Current (mA) Bias Current (mA) 6 Figure 10. 1.51 250 5 4 Figure 9. 1.515 Output Voltage (V) 3 Bias Voltage (V) 200 150 100 IOUT = 10 mA VIN = 2.5 V VOUT = 1.5 V VBIAS = 5 V IOUT = 100 mA IOUT = 750 mA IOUT = 1500 mA 30 25 20 15 10 50 5 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 Figure 13. (1) 8 5 20 35 50 65 80 95 110 125 Temperature (°C) Temperature (°C) Figure 14. This device does not show large bias current at any condition. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. BIAS CURRENT vs OUTPUT CURRENT 50 VBIAS = 5 V VIN = 2.5 V VOUT = 1.5 V IOUT = 0 mA VIN = 2.5 V VOUT = 1.5 V 12 Ground Current (mA) 40 Bias Current (mA) GROUND CURRENT vs BIAS VOLTAGE 14 30 20 10 10 8 6 4 2 0 0 0 200 400 600 800 1000 1200 1400 3 1600 3.5 4 Figure 15. Ground Current (mA) Ground Current (mA) 6 6.5 IOUT = 750 mA VIN = 2.5 V VOUT = 1.5 V 40 10 8 6 4 30 20 10 2 0 0 3 3.5 4 4.5 5 5.5 6 3 6.5 3.5 4.5 5 Bias Voltage (V) Figure 17. Figure 18. 5.5 6 6.5 BIAS CURRENT vs INPUT VOLTAGE 20 IOUT = 1500 mA VIN = 2.5 V VOUT = 1.5 V IOUT = 100 mA VBIAS = 5 V VOUT = 1.5 V 18 16 Bias Current (mA) 40 4 Bias Voltage (V) BIAS CURRENT vs BIAS VOLTAGE 50 Ground Current (mA) 5.5 BIAS CURRENT vs BIAS VOLTAGE 50 IOUT = 100 mA VIN = 2.5 V VOUT = 1.5 V 12 5 Figure 16. BIAS CURRENT vs BIAS VOLTAGE 14 4.5 Bias Voltage (V) Output Current (mA) 30 20 10 14 12 10 8 6 4 2 0 0 3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 Bias Voltage (V) Input Voltage (V) Figure 19. Figure 20. 2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 2.5 9 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. BIAS CURRENT vs INPUT VOLTAGE REFERENCE VOLTAGE vs INPUT VOLTAGE 0.91 300 VBIAS = 5 V IOUT = 1500 mA Reference Voltage (V) 250 Bias Current (mA) IOUT = 750 mA VBIAS = 5 V VOUT = 1.5 V 200 150 100 0.905 0.9 0.895 50 0.89 0 0 0.5 1 1.5 1.4 2.5 2 4.4 Input Voltage (V) Figure 21. Figure 22. REFERENCE VOLTAGE vs BIAS VOLTAGE 6.4 5.4 OUTPUT VOLTAGE vs TEMPERATURE 0.901 1.55 VIN = 2.5 V VBIAS = 5 V VIN = 2.5 V 1.54 1.53 0.9005 Output Voltage (V) Reference Voltage (V) 3.4 2.4 Input Voltage (V) 0.9 0.8995 1.52 1.51 1.5 1.49 1.48 1.47 1.46 0.899 1.45 3 4 3.5 4.5 5 5.5 6 6.5 -40 -25 -10 5 Bias Voltage (V) 65 80 110 125 95 ENABLE THRESHOLD vs BIAS VOLTAGE 1.6 3.5 1.4 3 1.2 Enable Threshold (V) Short-Circuit Current (A) SHORT-CIRCUIT CURRENT vs TEMPERATURE 2.5 2 1.5 VBIAS = 5 V VIN = 2.5 V VOUT = 0 V 1 0.8 0.6 0.4 Off 0.2 0 VIN = 2.5 V On 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 3 Temperature (°C) 3.5 4 4.5 5 5.5 6 6.5 Bias Voltage (V) Figure 25. 10 50 Figure 24. 4 0.5 35 Temperature (°C) Figure 23. 1 20 Figure 26. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, VIN = 2.5 V, VBIAS = 5.0 V, VOUT(target) = 1.5 V, VEN = VBIAS, CIN = 2.2 μF, CBIAS = 2.2 μF, and COUT = 10 μF, unless otherwise noted. ENABLE THRESHOLD vs TEMPERATURE LOAD TRANSIENT RESPONSE 1.6 Output Voltage (100 mV/div) 1.2 1 0.8 0.6 0.4 0.2 Off VBIAS = 5 V VIN = 2.5 V On Output Current (1 A/div) Enable Threshold (V) 1.4 VBIAS = 3.3 V VIN = 1.8 V VOUT = 1.0 V COUT = 2.2-mF Ceramic 5 20 35 50 65 80 95 IOUT IOUT = 1.5 A IOUT = 50 mA 0 -40 -25 -10 VOUT Time (10 ms/div) 110 125 Figure 27. Figure 28. BIAS VOLTAGE LINE TRANSIENT RESPONSE INPUT VOLTAGE LINE TRANSIENT RESPONSE VBIAS = 5.5 V VOUT VBIAS Output Voltage (20 mV/div) VIN = 1.8 V VOUT = 1.0 V COUT = 2.2-mF Ceramic IOUT = 1.5 A Input Voltage (2 V/div) Bias Voltage (2 V/div) Output Voltage (20 mV/div) Temperature (°C) VBIAS = 3.3 V VBIAS = 3.3 V VOUT = 1.0 V COUT = 2.2-mF Ceramic IOUT = 1.5 A VOUT VIN VIN = 5.5 V VIN = 1.8 V Time (500 ms/div) Time (500 ms/div) Figure 29. Figure 30. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 11 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com APPLICATION INFORMATION The TPS740xx belongs to a family of low dropout (LDO) regulators. These regulators use a low-current bias input to power all internal control circuitry, allowing the NMOS-pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS740xx to be stable with any capacitor type of 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications. With the fixed output voltage version, an enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability is ideal for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often present in processor-intensive systems. Figure 31 illustrates the typical application circuit for the TPS74001 adjustable output device. VIN VOUT OUT IN CIN 1m F R1 TPS74001 FB VBIAS BIAS COUT 10m F R2 GND CBIAS 1m F VOUT = 0.9 ´ ( 1+ R1 R2 ) Figure 31. Typical Application Circuit for the TPS74001 (Adjustable) R1 and R2 can be calculated for any output voltage using the formula shown in Figure 31. Table 2 lists sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 is recommended to be lower than 4.99 kΩ. Figure 32 illustrates the typical application circuit for the TPS740xx fixed output device. VIN BIAS TPS740xx EN VBIAS VOUT OUT IN CIN 1mF COUT 10mF GND CBIAS 1mF Figure 32. Typical Application Circuit for the TPS740xx (Fixed Voltage Versions) 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com Table 2. Standard 1% Resistor Values for Programming the Output Voltage R1 (kΩ) R2 (kΩ) VOUT (V) Short Open 0.9 0.562 5.11 1.0 0.75 4.53 1.05 1.07 4.99 1.1 1.58 4.75 1.2 1.91 2.87 1.5 2.43 2.43 1.8 3.01 1.69 2.5 4.22 1.58 3.3 5.23 1.74 3.6 INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS The device is designed to be stable for all available types and values of output capacitors greater than or equal to 2.2 μF. The device is also stable with multiple capacitors in parallel, which can be of any type or value. The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1 μF. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 μF. Good-quality, low-ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors should be placed as close to the pins as possible for optimum performance. TRANSIENT RESPONSE The TPS740xx is designed to have excellent transient response for most applications with a small amount of output capacitance. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In these cases, adding additional input capacitance improves the transient response much more than simply adding additional output capacitance. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient event; refer to the Typical Characteristics section. Because the TPS740xx is stable with output capacitors as low as 2.2 μF, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 13 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com DROPOUT VOLTAGE The TPS740xx offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT applications. The low dropout of the TPS740xx allows the device to be used in place of a dc/dc converter and still achieve good efficiency. This performance provides designers with the power architecture for the application to achieve the smallest, simplest, and lowest cost solution. There are two different specifications for dropout voltage with the TPS740xx. The first specification (shown in Figure 33) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low dropout. This specification assumes that VBIAS is at least 2.0 V above VOUT. If VBIAS is higher than VOUT + 2.0 V, VIN dropout is less than specified. BIAS IN Reference VBIAS = 5V ±5% VIN = 1.8V VOUT = 1.5V IOUT = 1.5A Efficiency = 83% OUT VOUT COUT FB Simplified Block Diagram Figure 33. Typical Application of the TPS74001 Using an Auxiliary Bias Rail The second specification (shown in Figure 34) is referred to as VBIAS Dropout and applies to applications where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 2.0 V above VOUT. Because of this usage, when IN and BIAS are tied together they easily consume large amounts of power. Do not to exceed the power rating of the IC package. VIN BIAS Reference IN VBIAS = 3.3V ±5% VIN = 3.3V ± 5V VOUT = 1.5V IOUT = 1.5A Efficiency = 45% OUT VOUT COUT FB Simplified Block Diagram Figure 34. Typical Application of the TPS74001 Without an Auxiliary Bias Rail 14 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com SEQUENCING REQUIREMENTS VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. NOTE: current charge greater When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 μA of from OUT. Although this condition does not cause any damage to the device, the output current may up the OUT node if total resistance between OUT and GND (including external feedback resistors) is than 10 kΩ. ENABLE/SHUTDOWN (Fixed Voltage Version Only) The enable (EN) pin is active high and is compatible with standard digital signaling levels. When VEN is below 0.4 V, it turns the regulator off; when VEN is above 1.1 V, it turns the regulator on. Unlike many regulators, the enable circuitry has hysteresis and deglitching for use with relatively slow ramping analog signals. This configuration allows the TPS740xx to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50 mV of hysteresis and a deglitch circuit to help avoid on/off cycling as a result of small glitches in the VEN signal. The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4 V and 1.1 V limits. If precise turn-on timing is required, a fast rise-time signal must be used to enable the TPS740xx. If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable circuit. INTERNAL CURRENT LIMIT The TPS740xx features a current limit that is flat over temperature and supply voltage. The current limit responds in approximately 10μs to reduce the current during a short-circuit fault. The internal current limit protection circuitry of the TPS740xx is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS740xx above the rated current degrades device reliability. THERMAL PROTECTION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +40°C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS740xx is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS740xx into thermal shutdown degrades device reliability. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 15 TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com LAYOUT RECOMMENDATIONS AND POWER DISSIPATION An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the top side of R1 in Figure 31 should be connected as close as possible to the load. If BIAS is connected to IN, it is recommended to connect BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turn-on response. Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 1: PD = (VIN – VOUT) × IOUT (1) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On the DGK (MSOP-8) package, the primary conduction path for heat is through four GND pins (right side of the IC) to the printed circuit board (PCB). On the DPT (Jr S-PAK) package, the primary conduction path for heat is through the tab to the PCB. This tab should be connected to ground. On both packages, ground pattern on PCB should have an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 2: (+125°C - TA) RqJA = PD (2) 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx TPS740xx SBVS091A – JUNE 2011 – REVISED JUNE 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (June 2011) to Revision A Page • Changed VBIAS Input Voltage Range Features sub-bullet before document release ........................................................... 1 • Changed Electrical Characteristics before device release ................................................................................................... 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): TPS740xx 17 PACKAGE OPTION ADDENDUM www.ti.com 2-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS74001DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS74001DGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR TPS74001DPTR ACTIVE VSON DPT 5 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS74001DPTT ACTIVE VSON DPT 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS74001DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS74001DGKT MSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74001DGKR MSOP DGK 8 2500 346.0 346.0 29.0 TPS74001DGKT MSOP DGK 8 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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