CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 D D D Y8 Y8 Y7 5 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y5 Y5 Y4 description The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-Ω transmission lines. 25 6 Y0 Y0 Y1 VCC0 Y1 Y2 Y2 Y4 Y3 Y3 D VCC0 D FN PACKAGE (TOP VIEW) Low-Output Skew for Clock-Distribution Applications Differential Low-Voltage Pseudo-ECL (LVPECL)-Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine Differential Clock Outputs Output Reference Voltage, VREF , Allows Distribution From a Single-Ended Clock Input Single-Ended LVPECL-Compatible Output Enable Packaged in Plastic Chip Carrier NC V REF CLKIN V CC CLKIN OE GND D NC – No internal connection When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state, Y outputs are in the high state). The VREF output can be strapped to the CLKIN input for a single-ended CLKIN input. The CDC111 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS CLKIN CLKIN OE Yn Yn X X H L H L H L L H H L L H L L VREF VREF L L L H H L L L H L H L L H H VREF VREF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 logic diagram (positive logic) CLKIN CLKIN OE 28 2 25 27 24 23 21 20 19 18 17 16 14 13 12 11 10 9 7 6 5 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 mW Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C " † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a juction temperature of 150_C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 recommended operating conditions (see Note 3) VCC Supply voltage VIH High level input voltage High-level VIL Low level input voltage Low-level TA Operating free-air temperature MIN MAX UNIT 3 3.6 V VCC = 3 V to 3.6 V VCC = 3.3 V VCC–1.165 2.135 VCC–0.88 2.420 V VCC = 3 V to 3.6 V VCC = 3.3 V VCC–1.81 1.49 VCC–1.475 1.825 V 0 70 °C 500 MHz fclock Input frequency NOTE 3: VCC = VCCO V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VREF VCC = 3 V to 3.6 V VCC = 3.3 V VCC –1.38 1.92 VCC –1.26 2.04 V VOH VCC = 3 V to 3.6 V VCC = 3.3 V VCC –1.025 2.275 VCC – 0.88 2.42 V VOL VCC = 3 V to 3.6 V VCC = 3.3 V VCC –1.81 1.49 VCC –1.62 1.68 V II ICC VI = 2.4 V, IO = 0, VCC = 3 .6 V VCC = 3 .6 V 150 µA 80 mA switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (see Figures 1 and 2) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL CLKIN CLKIN CLKIN, Y Y Y, tPHL OE Y, Y MIN MAX 450 600 450 600 UNIT ps 900 ps tsk(o) Y, Y 50 ps tsk(pr) Y, Y 150 ps tr tf Y, Y 200 600 ps Y, Y 200 600 ps POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION ZO = 50 Ω From Output Under Test 50 Ω VCC – 2 V Y, Y Outputs 80% 20% tr 80% 20% VOH VOL tf VOLTAGE WAVEFORMS RISE AND FALL TIMES LOAD CIRCUIT CLKIN VCC – 0.9 V VCC – 1.7 V CLKIN tPLH tPHL VOH Y Outputs VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC – 0.9 V OE 50% 50% VCC – 1.7 V Y VOH Y VOL Waveform 1 tPLH tPHL tPLH tPHL VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 45 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns. B. Waveform 1 is for a Y output with internal conditions such that the output is high except when disabled by the output control, and for a Y output with internal conditions such that the output is low except when disabled by the output control. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION CLKIN CLKIN Y0 Y0 tPLH1 tPHL1 tPLH2 tPHL2 tPLH3 tPHL3 tPLH4 tPHL4 tPLH5 tPHL5 tPLH6 tPHL6 tPLH7 tPHL7 tPLH8 tPHL8 tPLH9 tPHL9 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 NOTES: A. Output skew, tsk(o), is calculated as the greater of: – The difference between the fastest and slowest tPLHn (n = 1, 2, . . . 9) – The difference between the fastest and slowest tPHLn (n = 1, 2, . . . 9) B. Process skew, tsk(pr), is calculated as the greater of: – The difference between the fastest and slowest tPLHn (n = 1, 2, . . . 9) – The difference between the fastest and slowest tPHLn (n = 1, 2, . . . 9) across multiple devices Figure 2. Waveforms for Calculation of tsk(o), tsk(pr) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 MECHANICAL DATA FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated