STMICROELECTRONICS STK850

STK850
N-channel 30V - 0.0024Ω - 30A - PolarPAK®
STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on)
RDS(on)*Qg
PTOT
STK850
30V
<0.0029Ω
71nC*mΩ
5.2W
■
Ultra low top and bottom junction to case
thermal resistance
■
Very low capacitances
■
100% Rg tested
■
Fully encapsulated die
■
100% Matte tin finish (in compliance with the
2002/95/EC european directive)
■
PolarPAK® is a trademark of VISHAY
PolarPAK®
Application
■
Figure 1.
Internal schematic diagram
Switching applications
Description
This Power MOSFET is the latest development of
STMicroelectronics unique “single feature size”
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, moreover the double sides cooling
package with ultra low junction to case thermal
resistance allows to handle higher levels of
current.
Table 1.
Bottom View
Top View
Device summary
Order code
Marking
Package
Packaging
STK850
K850
PolarPAK®
Tape & reel
October 2007
Rev 9
1/16
www.st.com
16
Contents
STK850
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
.............................................. 9
STK850
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
VDS
Parameter
Drain-source voltage (VGS = 0)
Value
Unit
30
V
VGS (1)
Gate-source voltage
± 16
V
VGS(2)
Gate-source voltage
± 18
V
ID (4)
Drain current (continuous) at TC = 25°C
30
A
ID
Drain current (continuous) at TC = 100°C
18.75
A
Drain current (pulsed)
120
A
Total dissipation at TC = 25°C
5.2
W
0.0416
W/°C
Single pulse avalanche energy
1.4
J
Operating junction temperature
Storage temperature
-55 to 150
°C
IDM (3)
PTOT (4)
Derating factor
EAS
(5)
TJ
Tstg
1. Continuous mode
2. Guaranteed for test time < 15ms
3. Pulse width limited by package
4. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤10sec
5. Starting TJ = 25°C, ID = 15A, VDD = 25V
Table 3.
Thermal data
Symbol
Parameter
Rthj-amb(1) Thermal resistance junction-amb
Typ.
Max.
Unit
20
24
°C/W
Rthj-c(2)
Thermal resistance junction-case (top drain)
0.8
1
°C/W
Rthj-c(3)
Thermal resistance junction-case (source)
2.2
2.7
°C/W
1. When mounted on FR-4 board of 1inch2, 2 oz. Cu. and ≤10sec
2. Steady State
3.
Measured at Source pin when the device is mounted on FR-4 board in steady state
3/16
Electrical characteristics
2
STK850
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
Symbol
V(BR)DSS
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 250µA, VGS= 0
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±16V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250µA
RDS(on)
Static drain-source on
resistance
VGS= 10V, ID= 15A
Symbol
Ciss
Coss
Crss
Qg
Qgs
Qgd
Qgs1
Qgs2
RG
Min.
Typ.
Max.
30
VDS = Max rating,Tc=125°C
1
1
10
µA
µA
±100
nA
2.5
V
0.0024 0.0029
0.0029 0.0035
VGS= 4.5V, ID= 15A
Unit
V
VDS = Max rating,
IDSS
Table 5.
4/16
On/off
Ω
Ω
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Test conditions
VDS =25V, f=1 MHz, VGS=0
Total gate charge
Gate-source charge
Gate-drain charge
VDD=15V, ID = 30A
Pre Vth gate-to-source
charge
Post Vth gate-to-source
charge
VDD=15V, ID = 12A
VGS =4.5V
(see Figure 21)
Gate input resistance
f=1 MHz Gate DC Bias = 0
Test signal level = 20mV
open drain
VGS =4.5V
(see Figure 16)
Min.
Typ.
Max.
3150
940
90
24.5
8
8.2
Unit
pF
pF
pF
32.5
nC
nC
nC
0.6
nC
7.2
nC
1.1
Ω
STK850
Electrical characteristics
Table 6.
Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
Table 7.
Symbol
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
VDD= 15V, ID= 15A,
RG=4.7Ω, VGS=4.5V
(see Figure 15)
VDD=15V, ID= 15A,
RG=4.7Ω, VGS=4.5V
(see Figure 15)
Parameter
Test conditions
ISDM (1)
VSD (2)
Forward on voltage
ISD= 15A, VGS=0
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 30A, di/dt = 100A/µs,
VDD=20V, TJ=150°C
trr
Qrr
IRRM
Typ.
Max.
Unit
20
57
ns
ns
31
13
ns
ns
Source drain diode
Source-drain current
Source-drain current
(pulsed)
ISD
Min.
(see Figure 20)
Min.
Typ.
39
39.8
2
Max.
Unit
30
120
A
A
1.2
V
ns
nC
A
1. Pulse width limited by package
2. Pulsed: pulse duration = 300µs, duty cycle 1.5%
5/16
Electrical characteristics
STK850
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Transconductance
Figure 7.
Static drain-source on resistance
6/16
STK850
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
Figure 10. Normalized gate threshold voltage
vs temperature
Figure 11. Normalized on resistance vs
temperature
Figure 12. Source-drain diode forward
characteristics
Figure 13. Normalized BVDSS vs temperature
7/16
Electrical characteristics
STK850
Figure 14. Allowable IAV vs time in avalanche
The previous curve gives the single pulse safe operating area for unclamped inductive
loads, under the following conditions:
PD(AVE) =0.5*(1.3*BVDSS *IAV)
EAS(AR) =PD(AVE) *tAV
Where:
IAV is the allowable current in avalanche
PD(AVE) is the average power dissipation in avalanche (single pulse)
tAV is the time in avalanche
8/16
STK850
3
Test circuits
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
Figure 17. Test circuit for inductive load
Figure 18. Unclamped inductive load test
switching and diode recovery times
circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
9/16
Test circuits
STK850
Figure 21. Gate charge waveform
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
10/16
Qgd
STK850
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/16
Package mechanical data
Table 8.
STK850
PolarPAK® (option “L”) mechanical data
mm
inch
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.75
0.80
0.85
0.030
0.031
0.033
A1
0.05
b1
0.48
0.58
0.68
0.019
0.023
0.027
b2
0.41
0.51
0.61
0.016
0.020
0.024
b3
2.19
2.29
2.39
0.086
0.090
0.094
b4
0.89
1.04
1.19
0.035
0.041
0.047
b5
0.23
0.33
0.43
0.009
0.013
0.017
c
0.20
0.25
0.30
0.008
0.010
0.012
D
6
6.15
6.30
0.236
0.242
0.248
D1
5.74
5.89
6.04
0.226
0.232
0.238
E
5.01
5.16
5.31
0.197
0.203
0.209
E1
4.75
4.90
5.05
0.187
0.193
0.199
H1
0.23
H2
0.45
H3
0.31
H4
0.45
K1
4.22
K2
1.08
K3
1.37
0.054
K4
0.24
0.009
M1
4.30
4.50
4.70
M2
3.43
3.58
3.73
M3
0.22
0.009
M4
0.05
0.002
P1
0.15
0.20
0.25
T1
3.48
3.64
T2
0.56
0.76
T3
1.20
0.047
T4
3.90
0.154
T5
<
12/16
0.002
0°
0.009
0.56
0.018
0.51
0.012
0.56
0.018
4.37
4.52
0.166
0.172
0.178
1.13
1.18
0.043
0.044
0.046
0.169
0.177
0.185
0.135
0.141
0.147
0.006
0.008
0.010
4.10
0.137
0.143
0.161
0.95
0.022
0.030
0.037
0.007
0.014
10°
12°
0.41
0.18
0.36
10°
12°
0°
0.022
0.016
0.020
0.022
STK850
Package mechanical data
Figure 22. PolarPAK® (option “L”) drawings
13/16
Package mechanical data
Figure 23. Recommended PAD layout
14/16
STK850
STK850
5
Revision history
Revision history
Document
Table 9.
Document revision history
Date
Revision
Changes
10-Nov-2005
1
First version
19-Dec-2005
2
Complete version
30-Jan-2006
3
Modified description on first page
21-Mar-2006
4
The document has been reformatted
25-May-2006
5
New note on Table 2
10-Oct-2006
6
Modified general features
08-May-2007
7
New data on Table 5 and new Figure 21
03-Sep-2007
8
Updated mechanical data
01-Oct-2007
9
Inserted new Figure 23: Recommended PAD layout
15/16
STK850
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