STY100NS20FD N-channel 200V - 0.022Ω - 100A - Max247 MESH OVERLAY™ Power MOSFET General features Type VDSS RDS(on) ID STY100NS20FD 200V <0.024Ω 100A ■ Extremely high dv/dt capability ■ 100% avalanche tested ■ Gate charge minimized ■ ± 20V gate to source voltage rating ■ Low intrinsic capacitance ■ Fast body-drain diode:low trr, Qrr 2 3 1 Description Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of Power MOSFETs with outstanding performances. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(ON) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. Max247 Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STY100NS20FD Y100NS20FD Max247 Tube May 2006 Rev 3 1/12 www.st.com 12 Contents STY100NS20FD Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STY100NS20FD 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Drain-source voltage (VGS = 0) 200 V Drain-gate voltage (RGS = 20 kΩ) 200 V Gate- source voltage ±20 V ID Drain current (continuos) at TC = 25°C 100 A ID Drain current (continuos) at TC = 100°C 63 A Drain current (pulsed) 400 A Total dissipation at TC = 25°C 450 W Derating factor 3.6 W/°C Peak diode recovery voltage slope 25 V/ns –65 to 150 °C 150 °C Value Unit 0.277 °C/W 30 °C/W 300 °C Value Unit VDS VDGR VGS IDM (1) PTOT dv/dt (2) Tstg Tj Parameter Storage temperature Max. operating junction temperature 1. Pulse width limited by safe operating area 2. ISD <100A, di/dt < 200A/µs, VDD = 80% V(BR)DSS Table 2. Symbol Thermal resistance Parameter Rthj-case Thermal resistance junction-case Max Rthj-amb Thermal resistance junction-ambient Max Tl Table 3. Symbol Maximum lead temperature for soldering purpose Avalanche data Parameter IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 110 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 750 mJ 3/12 Electrical characteristics 2 STY100NS20FD Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol On/off states Parameter Test condictions Typ. Max. Unit Drain-source breakdown voltage ID = 250 µA, VGS = 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating VDS = Max rating, @125°C 10 100 µA µA IGSS Gate body leakage current (VDS = 0) VGS = ± 20V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA 3 4 V RDS(on) Static drain-source on resistance VGS = 10V, ID = 50A 0.022 0.024 Ω Typ. Max. Unit V(BR)DSS Table 5. Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd 200 2 V Dynamic Parameter Test condictions Forward transconductance VDS > ID(on) x RDS(on)max, ID = 50A Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1 MHz, VGS=0 Total gate charge Gate-source charge Gate-drain charge VDD = 100V, ID = 100A, VGS = 10V (see Figure 13) 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 4/12 Min. Min. 30 S 7900 1500 460 pF pF pF 360 35 135 nC nC nC STY100NS20FD Electrical characteristics Table 6. Switching times Symbol Parameter td(on) tr tr(Voff) tf tc Table 7. Symbol Turn-on delay time Rise time Off-voltage rise time Fall time Cross-over time Test Condictions Min. VDD = 100V, ID = 50A RG = 4.7Ω VGS = 10V (see Figure 12) VDD = 100V, ID = 100A, RG = 4.7Ω, VGS = 10V (see Figure 12) Typ. Max. Unit 42 140 ns ns 245 140 220 ns ns ns Source drain diode Max Unit Source-drain current 100 A ISDM(1) Source-drain current (pulsed) 400 A VSD(2) Forward on voltage ISD = 100A, VGS = 0 1.6 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD=100A, Tj=150°C ISD trr Qrr IRRM Parameter Test condictions di/dt = 100A/µs, VDD=160V, (see Figure 17) Min Typ. 225 1.35 12 ns µC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/12 Electrical characteristics STY100NS20FD 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/12 STY100NS20FD Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 11. Source-drain diode forward characteristics 7/12 Test circuit 3 STY100NS20FD Test circuit Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit Figure 16. Unclamped inductive waveform 8/12 Figure 17. Switching time waveform STY100NS20FD 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com 9/12 Package mechanical data STY100NS20FD Max247 MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. A 4.70 5.30 A1 2.20 2.60 b 1.00 1.40 b1 2.00 2.40 b2 3.00 3.40 c 0.40 0.80 D 19.70 20.30 e 5.35 5.55 E 15.30 15.90 L 14.20 15.20 L1 3.70 4.30 MIN. TYP. MAX. P025Q 10/12 STY100NS20FD 5 Revision history Revision history Table 8. Revision history Date Revision 15-May-2006 3 Changes New template 11/12 STY100NS20FD Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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