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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
FEATURES
DESCRIPTION
D Common-Mode Voltage Range (−20 V to 25 V)
More Than Doubles TIA/EIA-485 Requirement
D Receiver Equalization Extends Cable Length,
Signaling Rate (HVD23, HVD24)
D Reduced Unit-Load for up to 256 Nodes
D Bus I/O Protection to Over 16-kV HBM
D Failsafe Receiver for Open-Circuit,
Short-Circuit and Idle-Bus Conditions
D Low Standby Supply Current 1-µA Max
D More Than 100 mV Receiver Hysteresis
APPLICATIONS
D Long Cable Solutions
−
−
−
Factory Automation
Security Networks
Building HVAC
These devices are designed for bidirectional data
transmission on multipoint twisted-pair cables. Example
applications are digital motor controllers, remote sensors
and terminals, industrial process control, security stations,
and environmental control systems.
These devices combine a 3-state differential driver and a
differential receiver, which operate from a single 5-V power
supply. The driver differential outputs and the receiver
differential inputs are connected internally to form a
differential bus port that offers minimum loading to the bus.
This port features an extended common-mode voltage
range making the device suitable for multipoint
applications over long cable runs.
D Severe Electrical Environments
−
−
−
The transceivers in the HVD2x family offer performance
far exceeding typical RS−485 devices. In addition to
meeting all requirements of the TIA/EIA−485−A standard,
the HVD2x family operates over an extended range of
common-mode voltage, and has features such as high
ESD protection, wide receiver hysteresis, and failsafe
operation. This family of devices is ideally suited for
long-cable networks, and other applications where the
environment is too harsh for ordinary transceivers.
Electrical Power Inverters
Industrial Drives
Avionics
HVD2x APPLICATION SPACE
HVD2x Devices Operate Over a Wider Common-Mode Voltage Range
100
−20 V
+25 V
HVD23
Signaling Rate − Mbps
HVD20
SUPER−485
10
HVD24
HVD21
RS−485
1
−7 V
HVD22
−20 V
−15 V −10 V
+12 V
−5 V
0
5V
10 V
15 V
20 V
25 V
0.1
10
100
Cable Length − m
1000
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002 − 2003, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (continued)
The ‘HVD20 provides high signaling rate (up to 25 Mbps) for interconnecting networks of up to 64 nodes.
The ‘HVD21 allows up to 256 connected nodes at moderate data rates (up to 5 Mbps). The driver output slew rate is
controlled to provide reliable switching with shaped transitions which reduce high-frequency noise emissions.
The ‘HVD22 has controlled driver output slew rate for low radiated noise in emission-sensitive applications and for
improved signal quality with long stubs. Up to 256 ‘HVD22 nodes can be connected at signaling rates up to 500 kbps.
The ‘HVD23 implements receiver equalization technology for improved jitter performance on differential bus applications
with data rates up to 25 Mbps at cable lengths up to 160 meters.
The ‘HVD24 implements receiver equalization technology for improved jitter performance on differential bus applications
with data rates in the range of 1 Mbps to 10 Mbps at cable lengths up to 1000 meters.
The receivers also include a failsafe circuit that provides a high-level output within 250 microseconds after loss of the input
signal. The most common causes of signal loss are disconnected cables, shorted lines, or the absence of any active
transmitters on the bus. This feature prevents noise from being received as valid data under these fault conditions. This
feature may also be used for Wired-Or bus signaling.
The SN65HVD2X devices are characterized for operation over the temperature range of −40°C to 85°C.
PRODUCT SELECTION GUIDE
PART NUMBERS
CABLE LENGTH AND SIGNALING RATE(1)
NODES
SN65HVD20
Up to 50 m at 25 Mbps
Up to 64
D: VP20
P: 65HVD20
SN65HVD21
Up to 150 m at 5 Mbps (with slew rate limit)
Up to 256
D: VP21
P: 65HVD21
SN65HVD22
Up to1200 m at 500 kbps (with slew rate limit)
Up to 256
D: VP22
P: 65HVD22
SN65HVD23
Up to 160 m at 25 Mbps (with receiver equalization)
Up to 64
D: VP23
P: 65HVD23
SN65HVD24
Up to 500 m at 3 Mbps (with receiver equalization)
Up to 256
D: VP24
P: 65HVD24
(1) Distance and signaling rate predictions based upon Belden 3105A cable and 15% eye pattern jitter.
AVAILABLE OPTIONS
PLASTIC THROUGH-HOLE
P−PACKAGE
(JEDEC MS-001)
PLASTIC SMALL-OUTLINE(1)
D−PACKAGE
(JEDEC MS-012)
SN65HVD20P
SN65HVD21P
SN65HVD22P
SN65HVD23P
SN65HVD24P
SN65HVD20D
SN65HVD21D
SN65HVD22D
SN65HVD23D
SN65HVD24D
(1) Add R suffix for taped and reeled carriers.
2
MARKING
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DRIVER FUNCTION TABLE
HVD20, HVD21, HVD22
INPUT
ENABLE
D
DE
A
H
H
L
H
X
L
X
OPEN
HVD23, HVD24
OUTPUTS
INPUT
ENABLE
B
D
DE
A
OUTPUTS
H
L
H
H
H
L
L
H
L
H
L
H
Z
Z
X
L
Z
Z
OPEN
Z
Z
X
OPEN
Z
Z
H
H
L
OPEN
H
L
H
B
H = high level, L= low level, X = don’t care, Z = high impedance (off), ? = indeterminate
RECEIVER FUNCTION TABLE
DIFFERENTIAL INPUT
ENABLE
OUTPUT
VID = (VA – VB)
0.2 V ≤ VID
RE
R
L
H
−0.2 V < VID < 0.2 V
L
H (see Note A)
VID ≤ −0.2 V
X
L
L
H
Z
X
OPEN
Z
Open circuit
L
H
Short Circuit
L
H
Idle (terminated) bus
L
H
H = high level, L= low level, Z = high impedance (off)
NOTE A: If the differential input VID remains within the transition range for
more than 250 µs, the integrated failsafe circuitry detects a bus
fault, and set the receiver output to a high state. See Figure 15.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
SN65HVD2X
Supply voltage(2), VCC
−0.5 V to 7 V
Voltage at any bus I/O terminal
−27 V to 27 V
Voltage input, transient pulse, A and B, (through 100 Ω, see Figure 16)
Voltage input at any D, DE or RE terminal
Receiver output current, IO
−10 mA to 10 mA
Human Body Model(3)
Electrostatic discharge
−60 V to 60 V
−0.5 V to VCC+ 0.5 V
Charged-Device Model(4)
Machine Model(5)
Continuous total power dissipation
A, B, GND
16 kV
All pins
5 kV
All pins
1.5 kV
All pins
200 V
See Power Dissipation Rating Table
Junction temperature, TJ
150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A.
3
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
POWER DISSIPATION RATINGS
PACKAGE
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
577 mW
DERATING FACTOR(3)
ABOVE TA = 25°C
4.62 mW/°C
369 mW
300 mW
913 mW
7.3 mW/°C
584 mW
474 mW
984 mW
7.87 mW/°C
630 mW
512 mW
1344 mW
10.8 mW/°C
860 mW
700 mW
CIRCUIT BOARD
MODEL
Low-K(1)
TA ≤ 25°C
POWER RATING
High-K(2)
Low-K(1)
High-K(2)
D
P
(1) In accordance with the Low-K thermal metric definitions of EIA/JESD51−3.
(2) In accordance with the High-K thermal metric definitions of EIA/JESD51−7.
(3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
PARAMETER
θJB
θJC
TEST CONDITIONS
Junction-to-board thermal resistance
Junction-to-case thermal resistance
P
56
47.1
P
54
HVD21
Typical
HVD22
HVD23
Device power dissipation
VCC = 5 V, TJ = 25
25°C,
C,
RL = 54 Ω,, CL = 50 pF (driver),
CL = 15 pF (receiver),
50% Duty cycle square-wave signal,
Driver and receiver enabled
295
5 Mbps
260
500 kbps
233
25 Mbps
302
5 Mbps
267
HVD20
25 Mbps
408
5 Mbps
342
500 kbps
300
25 Mbps
417
5 Mbps
352
HVD22
HVD23
VCC = 5.5 V, TJ = 125
125°C,R
C,RL = 54 Ω,,
CL = 50 pF, CL = 15 pF (receiver),
50% Duty cycle square-wave signal,
Driver and receiver enabled
HVD24
TSD
25 Mbps
HVD24
HVD21
Worst case
UNITS
86.2
D
HVD20
PD
VALUE
D
Thermal shut-down junction temperature
°C/W
mW
°C
170
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC
Voltage at any bus I/O terminal
High-level input voltage, VIH
Low-level input voltage, VIL
Differential input voltage, VID
A, B
D, DE, RE
A with respect to B
Driver
Output current
Receiver
Operating free-air temperature, TA(1)
MIN
NOM
4.5
5
5.5
V
−20
25
V
2
0
VCC
0.8
V
−25
25
V
−110
110
−8
8
−40
85
°C
130
°C
Junction temperature, TJ
−40
(1) Maximum free-air temperature operation is allowed as long as the device recommended junction temperature is not exceeded.
4
MAX UNIT
mA
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
VIK
VO
VOD(SS)
Input clamp voltage
Open-circuit output voltage
Steady-state differential output voltage
magnitude
TEST CONDITIONS
II = −18 mA
A or B, No load
MIN TYP(1)
−1.5
MAX
0.75
0
No load (open circuit)
3.3
4.2
RL = 54 Ω,
See Figure 1
With common-mode loading, See Figure 2
1.8
2.5
V
VCC
VCC
V
Change in steady-state differential output
voltage between logic states
See Figure 1 and Figure 3
VOC(SS)
Steady-state common-mode output voltage
See Figure 1
∆VOC(SS)
Change in steady-state common-mode output
voltage, VOC(H) – VOC(L)
See Figure 1 and Figure 4
VOC(PP)
Peak-to-peak common-mode output voltage,
VOC(MAX) – VOC(MIN)
RL = 54 Ω, CL = 50 pF,
See Figure 1 and Figure 4
VOD(RING)
II
Differential output voltage over and under shoot
RL = 54 Ω, CL = 50 pF, See Figure 5
D, DE
−100
IO(OFF)
IOZ
Output current with power off
VCC < = 2.5 V
DE at 0 V
See receiver line input
current
High impedance state output current
IOS
Short-circuit output current
COD
Differential output capacitance
(1) All typical values are at VCC = 5 V and 25°C.
−0.1
2.1
2.5
−0.1
0.1
V
2.9
V
0.1
V
0.35
VO = −20 V to 25 V,
See Figure 9
V
1.8
∆|VOD(SS)|
Input current
UNIT
V
10%
100
−250
µA
250
mA
MAX
UNIT
See receiver CI
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
Differential output propagation delay, low-to- high
tPHL
Differential output propagation delay, high-to-low
tr
Differential output rise time
tf
Differential output fall time
tPZH
Propagation delay time, high-impedance-to-high-level output
tPHZ
Propagation delay time, high-level-output-to-high-impedance
tPZL
Propagation delay time, high-impedance-to-low-level output
tPLZ
Propagation delay time, low-level-output-to-high-impedance
td(standby)
td(wake)
Time from an active differential output to standby
Wake-up time from standby to an active differential output
TEST CONDITIONS
RL = 54 Ω,,
CL = 50 pF,
See Figure 3
HVD20, HVD23
6
10
20
HVD21, HVD24
20
32
60
160
280
500
RL = 54 Ω,,
CL = 50 pF,
See Figure 3
HVD20, HVD23
2
6
12
HVD21, HVD24
20
40
60
200
400
600
RE at 0 V,
See Figure 6
RE at 0 V,
See Figure 7
HVD22
HVD22
HVD20, HVD23
40
HVD21, HVD24
100
HVD22
300
HVD20, HVD23
40
HVD21, HVD24
100
HVD22
300
RE at VCC, See Figure 8
HVD20, HVD23
tsk(p)
Pulse skew | tPLH – tPHL |
MIN TYP(1)
HVD21, HVD24
HVD22
ns
ns
ns
ns
2
µs
8
µs
2
6
ns
50
(1) All typical values are at VCC = 5 V and 25°C.
5
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions
PARAMETER
VIT(+)
VIT(−)
Positive-going differential input voltage threshold
VHYS
Hysteresis voltage (VIT+ − VIT−)
Negative-going differential input voltage threshold
TEST CONDITIONS
See Figure 10
VO = 2.4 V, IO = −8 mA
VO = 0.4 V, IO = 8 mA
VIT(F+)
Positive-going differential input failsafe voltage
threshold
See Figure 15
VCM = −7 V to 12 V
VCM = −20 V to 25 V
VIT(F−)
Negative-going differential input failsafe voltage
threshold
See Figure 15
VCM = −7 V to 12 V
VCM = −20 V to 25 V
VIK
VOH
Input clamp voltage
VOL
Low-level output voltage
High-level output voltage
II(BUS)
Bus input current (power on or power off)
II
Input current
RI
II = −18 mA
VID = 200 mV, IOH = −8 mA, See Figure 11
VID = −200 mV, IOL = 8 mA, See Figure 11
CID
Differential input capacitance
(1) All typical values are at 25°C.
MAX
60
200
−200
−60
100
130
40
120
200
120
250
−200
−120
−40
−250
−120
−1.5
VI = −7 to 12 V,
Other input = 0 V
−400
500
HVD21, HVD22, HVD24
−100
125
VI = −20 to 25 V,
Other input = 0 V
HVD20, HVD23
−800
1000
HVD21, HVD22, HVD24
−200
250
−100
100
HVD21, 22, 24
96
mV
mV
V
0.4
24
mV
V
4
HVD20, 23
UNIT
mV
HVD20, HVD23
RE
Input resistance
MIN TYP(1)
V
µA
µA
kΩ
VID = 0.5 + 0.4 sine (2π x 1.5 x 106t)
20
pF
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high level output
tr
tf
Receiver output rise time
tPZH
tPHZ
Receiver output enable time to high level
tPZL
tPLZ
Receiver output enable time to low level
tr(standby)
Time from an active receiver output to standby
tr(wake)
Wake-up time from standby to an active receiver
output
tsk(p)
tp(set)
Pulse skew | tPLH – tPHL |
Delay time, bus fail to failsafe set
tp(reset)
Delay time, bus recovery to failsafe reset
6
Propagation delay time, high-to-low level output
Receiver output fall time
Receiver output disable time from high level
Receiver output disable time from low level
TEST CONDITIONS
See Figure 11
TYP
MAX
HVD20, HVD23
16
35
HVD21, HVD22, HVD24
25
50
2
4
90
120
16
35
90
120
16
35
See Figure 11
See Figure 12
See Figure 13
MIN
UNIT
ns
ns
ns
ns
2
See Figure 14, DE at 0 V
See Figure 15,
pulse rate = 1 kHz
8
250
µs
5
350
ns
µs
50
ns
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
RECEIVER EQUALIZATION CHARACTERISTICS(1)
over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
0m
100 m
25 Mbps
150 m
200 m
200 m
tj(pp)
Peak-to-peak
eye-pattern jitter
Pseudo-random NRZ code with a bit
pattern length of 216 − 1 ,
Beldon 3105A cable, See Figure 27
10 Mbps
250 m
300 m
5 Mbps
3 Mbps
1 Mbps
500 m
500 m
1000 m
TYP(2)
HVD23
2
HVD20
6
HVD23
3
HVD20
15
HVD23
4
HVD20
27
HVD23
8
HVD20
22
HVD23
8
HVD20
34
HVD23
15
HVD20
49
HVD23
27
HVD21
128
HVD24
18
HVD20
93
HVD21
103
HVD23
90
HVD24
16
HVD21
216
HVD24
62
MAX
UNIT
ns
(1) The HVD20 and HVD21 do not have receiver equalization, but are specified for comparison.
(2) All typical values are at VCC = 5 V, and temperature = 25°C.
SUPPLY CURRENT
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Driver enabled (DE at VCC), Receiver enabled (RE at 0 V)
No load, VI = 0 V or VCC
ICC
Supply current
Driver enabled (DE at VCC), Receiver disabled (RE at VCC)
No load, VI = 0 V or VCC
Driver disabled (DE at 0 V), Receiver enabled (RE at 0 V)
No load
Driver disabled (DE at 0 V), Receiver disabled (RE at VCC)
D open
MIN
TYP
MAX
HVD20
6
9
HVD21
8
12
HVD22
6
9
HVD23
7
11
HVD24
10
14
HVD20
5
8
HVD21
7
11
HVD22
5
8
HVD23
5
9
HVD24
8
12
HVD20
4
7
HVD21
5
8
HVD22
4
7
HVD23
4.5
9
HVD24
5.5
10
All
HVD2x
1
UNIT
mA
mA
mA
µA
7
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
RE Inputs
D Inputs (HVD20, 21, 22)
DE Input
D Inputs (HVD23, 24)
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
R1
R3
R1
R3
Input
Input
29 V
R2
29 V
29 V
A and B Outputs
R2
R Output
VCC
VCC
5Ω
Output
Output
9V
29 V
HVD20, 23
HVD21, 22, 24
8
R1/R2
9 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
NOTES:
Test load capacitance includes probe and jig capacitance (unless otherwise specified).
Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle, Zo = 50 Ω (unless otherwise specified)
IO
II
27 Ω
VOD
0 V or 3 V
50 pF
27 Ω
IO
VOC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
IO
VOD
0 V or 3 V
60 Ω
375 Ω
IO
VTEST = −20 V to 25 V
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V
INPUT
RL = 54 Ω
Signal
Generator
VOD
1.5 V
90%
0V
tPHL
VOD(H)
10%
VOD(L)
tPLH
CL = 50 pF
50 Ω
1.5 V
0V
OUTPUT
tr
tf
Figure 3. Driver Switching Test Circuit and Waveforms
27 Ω
A
VA
D
Signal
Generator
50 Ω
B
27 Ω
≈ 3.25 V
VB
50 pF
≈ 1.75 V
VOC(PP)
VOC
∆VOC(SS)
VOC
Figure 4. Driver VOC Test Circuit and Waveforms
9
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
VOD(SS)
VOD(RING)
VOD(PP)
0 V Differential
VOD(RING)
VOD(SS)
NOTE: VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from the
VOD(H) and VOD(L) steady state values.
Figure 5. VOD(RING) Waveform and Definitions
A
S1
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
DE
Signal
Generator
3V
Output
B
1.5 V
DE
CL = 50 pF
RL = 110 Ω
1.5 V
0.5 V
tPZH
0V
VOH
Output
50 Ω
2.5 V
tPHZ
VOff 0
Figure 6. Driver Enable/Disable Test, High Output
5V
S1
D
3V
Output
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
DE
Signal
Generator
RL = 110 Ω
1.5 V
DE
1.5 V
0V
CL = 50 pF
tPZL
Output
50 Ω
tPLZ
5V
2.5 V
VOL
0.5 V
Figure 7. Driver Enable/Disable Test, Low Output
A
0 V or 3 V
D
RL = 54 Ω
B
DE
Signal
Generator
CL = 50 pF
VOD
3V
DE 1.5 V
0V
td(Wake)
td(Standby)
1.5 V
VOD
0.2 V
50 Ω
Figure 8. Driver Standby/Wake Test Circuit and Waveforms
10
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
IOS
VO
Voltage
Source
Figure 9. Driver Short-Circuit Test
IO
VID
VO
Figure 10. Receiver DC Parameter Definitions
Signal
Generator
50 Ω
Input B
VID
A
B
Signal
Generator
50 Ω
IO
R
CL = 15 pF
1.5 V
50%
Input A
0V
tPHL
VOH
tPLH
VO
Output
90%
1.5 V
tr
10% V
OL
tf
Figure 11. Receiver Switching Test Circuit and Waveforms
VCC
VCC
D
DE
A
54 Ω
B
3V
R
RE
Signal
Generator
1 kΩ
0V
RE
1.5 V
0V
CL = 15 pF
tPZH
tPHZ
50 Ω
R
1.5 V
VOH
VOH −0.5 V
GND
Figure 12. Receiver Enable Test Circuit and Waveforms, Data Output High
11
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SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
0V
VCC
D
DE
A
54 Ω
B
3V
1 kΩ
R
RE
5V
1.5 V
0V
CL = 15 pF
RE
tPZL
Signal
Generator
tPLZ
VCC
50 Ω
R
1.5 V
VOL +0.5 V
VOL
Figure 13. Receiver Enable Test Circuit and Waveforms, Data Output Low
VCC
Switch Down for V(A) = 1.5 V,
Switch Up for V(A) = −1.5 V
A
1.5 V or
−1.5 V
R
3V
B
1 kΩ
RE
CL = 15 pF
1.5 V
0V
RE
Signal
Generator
tr(Standby)
tr(Wake)
50 Ω
5V
R
1.5 V
VOH −0.5 V
VOL +0.5 V
0V
VOH
VOL
Figure 14. Receiver Standby and Wake Test Circuit and Waveforms
Bus Data Valid Region
200 mV
Bus Data
Transition Region
−40 mV
VID −200 mV
−1.5 V
Bus Data Valid Region
tp(SET)
tp(RESET)
VOH
R
1.5 V
VOL
Figure 15. Receiver Active Failsafe Definitions and Waveforms
100 Ω
VTEST
0V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
15 µs
1.5 ms
Figure 16. Test Circuit and Waveforms, Transient Overvoltage Test
12
−VTEST
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
PIN ASSIGNMENTS
D or P PACKAGE
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
LOGIC DIAGRAM
POSITIVE LOGIC
R
1
RE
DE
2
3
D
4
6 A
7
B
TYPICAL CHARACTERISTICS
HVD20, HVD23
BUS PIN CURRENT
vs
BUS PIN VOLTAGE
HVD21, HVD22, HVD24
BUS PIN CURRENT
vs
BUS PIN VOLTAGE
150
600
DE = 0 V
DE = 0 V
100
Bus Pin Current − µ A
Bus Pin Current − µ A
400
200
VCC = 0 V
0
VCC = 5 V
−200
VCC = 0 V
0
VCC = 5 V
−50
−100
−400
−600
−30
50
−20
−10
0
10
20
30
−150
−30
−20
−10
0
10
Bus Pin Voltage − V
Bus Pin Voltage − V
Figure 17
Figure 18
20
30
13
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
SUPPLY CURRENT
vs
SIGNALING RATE
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
DRIVER LOAD CURRENT
75
ICC − Supply Current − mA
70
5
HVD20
VOD − Driver Differential Output Voltage − V
VCC = 5 V,
DE = RE = VCC,
LOAD = 54 Ω, 50 pF
65
HVD22
HVD21
60
55
50
45
40
0.1
1
10
Signaling Rate − Mbps
4.5
3.5
VCC = 5 V
3
2.5
2
VCC = 4.5 V
1.5
1
0.5
0
100
VCC = 5.5 V
4
0
10
20
30
40
50
60
IL − Driver Load Current − mA
Figure 19
70
80
Figure 20
HVD20, HVD23
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTAL INPUT VOLATGE
PEAK-TO-PEAK JITTER
vs
CABLE LENGTH
30
VIT(−)
5
VIT(+)
25
VCM = 25 V
VCM = 25 V
4
VCM = 0 V
VCM = 0 V
3
2
VCM = −20 V
VCM = −20 V
1
−0.1
0
0.1
VID − Differential Input Voltage − V
Figure 21
14
VCC = 5 V,
TA = 25°C,
VIC = 2.5 V,
Cable: Belden 3105A
HVD20 = 25 Mbps
20
15
10
HVD23 = 25 Mbps
5
0
−1
−0.2
Peak-to-Peak Jitter − ns
VO − Receiver Output Voltage − V
6
0.2
0
100
120
140
160
Cable Length − m
Figure 22
180
200
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
HVD20, HVD21, HVD23, HVD24
HVD20, HVD23
PEAK-TO-PEAK JITTER
vs
CABLE LENGTH
PEAK-TO-PEAK JITTER
vs
SIGNALING RATE
70
HVD21: 500 m Cable
HVD21 = 10 Mbps
110
Peak-to-Peak Jitter − ns
Peak-to-Peak Jitter − ns
60
130
VCC = 5 V,
TA = 25°C,
VIC = 2.5 V,
Cable: Belden 3105A
50
40
HVD20 = 10 Mbps
30
HVD23 = 10 Mbps
20
90
VCC = 5 V,
TA = 25°C,
VIC = 2.5 V,
Cable: Belden 3105A
70
50
30
10
HVD24: 500 m Cable
HVD24 = 10 Mbps
0
200
10
220
240
260
Cable Length − m
Figure 23
280
300
3
3.5
4
4.5
Signaling Rate − Mbps
5
Figure 24
15
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
APPLICATION INFORMATION
THEORY OF OPERATION
The HVD2x family of devices integrates a differential receiver and differential driver with additional features for
improved performance in electrically-noisy, long-cable, or other fault-intolerant applications.
The receiver hysteresis (typically 130 mV) is much larger than found in typical RS-485 transceivers. This helps
reject spurious noise signals which would otherwise cause false changes in the receiver output state.
Slew rate limiting on the driver outputs (SN65HVD21, 22, and 24) reduces the high-frequency content of signal
edges. This decreases reflections from bus discontinuities, and allows longer stub lengths between nodes and
the main bus line. Designers should consider the maximum signaling rate and cable length required for a
specific application, and choose the transceiver best matching those requirements.
When DE is low, the differential driver is disabled, and the A and B outputs are in high-impedance states. When
DE is high, the differential driver is enabled, and drives the A and B outputs according to the state of the D input.
When RE is high, the differential receiver output buffer is disabled, and the R output is in a high-impedance state.
When RE is low, the differential receiver is enabled, and the R output reflects the state of the differential bus
inputs on the A and B pins.
If both the driver and receiver are disabled, (DE low and RE high) then all nonessential circuitry, including
auxiliary functions such as failsafe and receiver equalization is placed in a low-power standby state. This
reduces power consumption to less than 5 µW. When either enable input is asserted, the circuitry again
becomes active.
In addition to the primary differential receiver, these devices incorporate a set of comparators and logic to
implement an active receiver failsafe feature. These components determine whether the differential bus signal
is valid. Whenever the differential signal is close to zero volts (neither high nor low), a timer initiates, If the
differential input remains within the transition range for more than 250 microseconds, the timer expires and set
the receiver output to the high state. If a valid bus input (high or low) is received at any time, the receiver output
reflects the valid bus state, and the timer is reset.
(V A−V B) : Not High
+
−
Bus Input
Invalid
(V A−VB) : Not Low
Timer
250 ms
R
1
120 mV
+
−
120 mV
Active
Filters
2
RE
STANDBY
3
DE
6
D
4
Slew
Rate
Control
Figure 25. Function Block Diagram
16
7
A
B
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
Figure 26. HVD22 Receiver Operation With 20-V Offset on Input Signal
ƪ
ƫƪǒ
ƫƪ
ƫ
k0
(DC
loss)
p1
(MHz)
k1
p2
(MHz)
k2
p3
(MHz)
k3
Similar to 160m of Belden 3105A
0.95
0.25
0.3
3.5
0.5
15
1
Similar to 250m of Belden 3105A
0.9
0.25
0.4
3.5
0.7
12
1
Similar to 500m of Belden 3105A
0.8
0.25
0.6
2.2
1
8
1
Similar to 1000m of Belden 3105A
0.6
0.3
1
3
1
6
1
H(s) + k0
ǒ1–k 1Ǔ )
k1p1
ǒs ) p 1Ǔ
1–k
Ǔ)
2
k p
2 2
ǒs ) p2Ǔ
ǒ1–k3Ǔ )
Signal
Generator
k p
3 3
ǒs ) p3Ǔ
H(s)
Figure 27. Cable Attenuation Model for Jitter Measurements
17
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
INTEGRATED RECEIVER EQUALIZATION USING THE HVD23
Figure 28 illustrates the benefits of integrated receiver equalization as implemented in the HVD23 transceiver.
In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was
Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of
nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the differential voltage at the receiver
inputs (after the cable attenuation). Channel 2 (bottom) shows the output of the receiver.
Figure 28. HVD23 Receiver Performance at 25 Mbps Over 150 Meter Cable
18
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
INTEGRATED RECEIVER EQUALIZATION USING THE HVD24
Figure 29 illustrates the benefits of integrated receiver equalization as implemented in the HVD24 transceiver.
In this test setup, a differential signal generator applied a signal voltage at one end of the cable, which was
Belden 3105A twisted-pair shielded cable. The test signal was a pseudo-random bit stream (PRBS) of
nonreturn-to-zero (NRZ) data. Channel 1 (top) shows the eye-pattern of the bit stream. Channel 2 (middle)
shows the eye-pattern of the differential voltage at the receiver inputs (after the cable attenuation). Channel
3 (bottom) shows the output of the receiver.
Figure 29. HVD24 Receiver Performance at 5 Mbps Over 500 Meter Cable
19
www.ti.com
SLLS552D − DECEMBER 2002 − REVISED APRIL 2005
NOISE CONSIDERATIONS FOR EQUALIZED RECEIVERS
The simplest way of overcoming the effects of cable losses is to increase the sensitivity of the receiver. If the
maximum attenuation of frequencies of interest is 20 dB, increasing the receiver gain by a factor of ten
compensates for the cable. However, this means that both signal and noise are amplified. Therefore, the
receiver with higher gain is more sensitive to noise and it is important to minimize differential noise coupling
to the equalized receiver.
Differential noise is crated when conducted or radiated noise energy generates more voltage on one line of the
differential pair than the other. For this to occur from conducted or electric far-field noise, the impedance to
ground of the lines must differ.
For noise frequency out to 50 MHz, the input traces can be treated as a lumped capacitance if the receiver is
approximately 10 inches or less from the connector. Therefore, matching impedance of the lines is
accomplished by matching the lumped capacitance of each.
The primary factors that affect the capacitance of a trace are in length, thickness, width, dielectric material,
distance from the signal return path, stray capacitance, and proximity to other conductors. It is difficult to match
each of the variables for each line of the differential pair exactly, but a reasonable effort to do so keeps the lines
balanced and less susceptible to differential noise coupling.
Another source of differential noise is from near-field coupling. In this situation, an assumption of equal
noise-source impedance cannot be made as in the far-field. Familiarly known as crosstalk, more energy from
a nearby signal is coupled to one line of the differential pair. Minimization of this differential noise is
accomplished by keeping the signal pair close together and physical separation from high-voltage, high-current,
or high-frequency signals.
In summary, follow these guidelines in board layout for keeping differential noise to a minimum.
D
D
D
D
D
20
Keep the differential input traces short.
Match the length, physical dimensions, and routing of each line of the pair.
Keep the lines close together.
Match components connected to each line.
Separate the inputs from high-voltage, high-frequency, or high-current signals.
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN65HVD20D
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD20DR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD20P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD21D
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD21DR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD21P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD22D
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD22DR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD22P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD22PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD23D
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD23DR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD23P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD23PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD24D
ACTIVE
SOIC
D
8
75
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD24DR
ACTIVE
SOIC
D
8
2500
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65HVD24P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
SN65HVD24PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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