FREESCALE MPC17531AEP

Freescale Semiconductor
Technical Data
Document Number: MPC17531A
Rev. 3.0, 2/2008
700 mA Dual H-Bridge Motor
Driver with 3.0 V Compatible
Logic I/O
The 17531A is a monolithic dual H-Bridge power IC ideal for
portable electronic applications containing bipolar step motors and/or
brush DC-motors (e.g., cameras and disk drive head positioners).
The 17531A operates from 2.0 V to 8.6 V using the internal charge
pump, with independent control of each H-Bridge via parallel MCU
interface. The device features built-in shoot-through current
protection and an undervoltage shutdown function.
The 17531A has four operating modes: Forward, Reverse, Brake,
and Tri-Stated (High Impedance). The 17531A has a low total
RDS(ON) of 1.2 Ω (max @ 25°C).
The 17531A efficiently drives many types of micromotors with low
power dissipation owing to its low output resistance and high output
slew rates. The H-Bridge outputs can be independently pulse width
modulated (PWM’ed) at up to 200 kHz for speed/torque and current
control.
17531A
DUAL H-BRIDGE
VMFP SUFFIX
EV SUFFIX (PB-FREE)
98ASA10616D
20-TERMINAL VMFP
QFN SUFFIX
EP SUFFIX (PB-FREE)
98ARL10577D
24-TERMINAL QFN
Features
•
•
•
•
•
•
•
•
•
Low Total RDS(ON) 0.8 W (Typ), 1.2 Ω (Max) @ 25°C
Output Current 0.7 A (DC)
Shoot-Through Current Protection Circuit
PWM Control Input Frequency up to 200 kHz
Built-In Charge Pump Circuit
Low Power Consumption
Undervoltage Detection and Shutdown Circuit
Power Save Mode with Current Draw ≤ 2.0 µA
Pb-Free Packaging Designated by Suffix Codes EV and EP
ORDERING INFORMATION
Temperature
Range (TA)
Device
MPC17531AEV/EL
MPC17531AEP/R2
3.0 V
5.0 V
17531A
VDD
VM
C1L
C1H
C2L
OUT1A
C2H
CRES OUT1B
MCU
IN1A OUT2A
IN1B OUT2B
IN2A
IN2B
PSAVE
S
N
Bipolar
Step
Motor
GND
Figure 1. 17531A Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
-20°C to 65°C
Package
20 VMFP
24 QFN
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CRES
C2H
Charge
Pump
C1H
C1L
C2L
LowVoltage
Shutdown
VDD
VM1
IN1A
OUT1A
H-Bridge
OUT1B
IN1B
VDD
PSAVE
Control
Logic
PGND1
Level Shifter
Predriver
VM2
IN2A
OUT2A
H-Bridge
OUT2B
IN2B
PGND2
LGND
Figure 2. 17531A Simplified Internal Block Diagram
17531A
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
VDD
1
20
LGND
IN1A
2
19
IN2A
IN1B
3
18
IN2B
PSAVE
4
17
VM2
OUT2A
5
16
OUT2B
PGND1
6
15
PGND2
OUT1A
7
14
OUT1B
VM1
8
13
C2L
CRES
9
12
C1L
10
11
C1H
C2H
Figure 3. 17531A, 20-Terminal VMFP Connections
Table 1. 17531A, 20-Terminal VMFP Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.
Terminal
Number
Terminal
Name
Formal Name
1
VDD
Logic Supply
2
IN1A
Logic Input Control 1A
Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).
3
IN1B
Logic Input Control 1B
Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).
4
PSAVE
Power Save
5
OUT2A
H-Bridge Output 2A
6
PGND1
Power Ground 1
7
OUT1A
H-Bridge Output 1A
8
VM1
Motor Drive Power Supply 1
9
CRES
Predriver Power Supply
10
C2H
Charge Pump 2H
Charge pump bucket capacitor 2 (positive pole).
11
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
12
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
13
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
14
OUT1B
H-Bridge Output 1B
15
PGND2
Power Ground 2
16
OUT2B
H-Bridge Output 2B
17
VM2
Motor Drive Power Supply 2
18
IN2B
Logic Input Control 2B
Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).
19
IN2A
Logic Input Control 2A
Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).
20
LGND
Logic Ground
Definition
Control circuit power supply terminal.
Logic input controlling power save mode.
Output A of H-Bridge channel 2.
High-current power ground 1.
Output A of H-Bridge channel 1.
Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
Internal triple charge pump output as predriver power supply.
Output B of H-Bridge channel 1.
High-current power ground 2.
Output B of H-Bridge channel 2.
Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
Low-current logic signal ground.
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
24
NC
IN2A
LGND
IN2B
19
18
2
17
3
16
MPC17530EP
4
15
5
14
6
13
8
NC
7
9
10
11
VM2
NC
OUT2B
PGND2
OUT1B
C2L
12
C1L
OUT1A
20
C1H
PGND1
21
C2H
OUT2A
22
CRES
PSAVE
23
1
VM1
NC
VDD
IN1B
Transparent Top View of Package
IN1A
TERMINAL CONNECTIONS
Figure 4. 17531A, 24-Terminal QFN Connections
Table 2. 17531A, 24-Terminal QFN Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.
Terminal
Number
Terminal
Name
Formal Name
1, 6, 7, 17
NC
No Connect
This terminal is not used.
2
PSAVE
Power Save
Logic input controlling power save mode.
3
OUT2A
H-Bridge Output 2A
4
PGND1
Power Ground 1
5
OUT1A
H-Bridge Output 1A
8
VM1
Motor Drive Power Supply 1
9
CRES
Predriver Power Supply
10
C2H
Charge Pump 2H
Charge pump bucket capacitor 2 (positive pole).
11
C1H
Charge Pump 1H
Charge pump bucket capacitor 1 (positive pole).
12
C1L
Charge Pump 1L
Charge pump bucket capacitor 1 (negative pole).
13
C2L
Charge Pump 2L
Charge pump bucket capacitor 2 (negative pole).
14
OUT1B
H-Bridge Output 1B
15
PGND2
Power Ground 2
16
OUT2B
H-Bridge Output 2B
18
VM2
Motor Drive Power Supply 2
19
IN2B
Logic Input Control 2B
Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).
20
IN2A
Logic Input Control 2A
Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).
21
LGND
Logic Ground
Low-current logic signal ground.
22
VDD
Logic Supply
Control circuit power supply terminal.
23
IN1A
Logic Input Control 1A
Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).
24
IN1B
Logic Input Control 1B
Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).
Definition
Output A of H-Bridge channel 2.
High-current power ground 1.
Output A of H-Bridge channel 1.
Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
Internal triple charge pump output as pre-driver power supply.
Output B of H-Bridge channel 1.
High-current power ground 2.
Output B of H-Bridge channel 2.
Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
17531A
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VM
VC
RES
-0.5 to 11.0
V
-0.5 to 14.0
V
Logic Supply Voltage
VDD
-0.5 to 5.0
V
Signal Input Voltage
VIN
-0.5 to VDD + 0.5
V
IO
0.7
IOPK
1.4
VESD1
±1200
VESD2
± 150
Operating Junction Temperature
TJ
-20 to 150
°C
Operating Ambient Temperature
TA
-20 to 65
°C
TSTG
-65 to 150
°C
RθJA
50
°C/W
Motor Supply Voltage
Charge Pump Output Voltage
Driver Output Current
A
Continuous
Peak (1)
ESD Voltage
V
Human Body Model
(2)
Machine Model (3)
Storage Temperature Range
Thermal Resistance
(4)
Power Dissipation (5)
PD
W
WMFP
1.0
QFN
2.5
Terminal Soldering Temperature (6)
TSOLDER
260
°C
Notes
1. TA = 25°C. Pulse width = 10 ms at 200 ms intervals.
2.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
3.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4.
5.
For QFN only, mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).
TA = 25°C.
6.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VM-CP
2.0
5.0
8.6
V
VM-NCP
–
–
10
V
VCRES - VM
5.0
6.0
–
V
VDD
2.7
3.0
3.6
V
–
–
100
–
–
1.0
–
–
1.0
–
–
1.0
–
–
3.0
–
–
0.7
POWER INPUT
Motor Supply Voltage (Using Internal Charge Pump) (7)
V
Motor Supply Voltage ( CRES Applied Externally) (8)
V
Gate Drive Voltage - Motor Supply Voltage ( CRES Applied Externally) (9)
Logic Supply Voltage
Driver Quiescent Supply Current
µA
I
No Signal Input
QM
I
QM-PSAVE
Power Save Mode
mA
Logic Quiescent Supply Current
No Signal Input
I
QVDD
I
QVDDPSAVE
(10)
Power Save Mode
Operating Power Supply Current
Logic Supply Current
I
(11)
mA
VDD
ICRES
Charge Pump Circuit Supply Current (12)
Low VDD Detection Voltage (13)
V
DDDET
1.0
1.6
2.5
V
Driver Output ON Resistance (14)
RDS(ON)
–
0.8
1.2
Ohms
12
13
13.5
8.5
9.2
–
0.01
0.1
1.0
GATE DRIVE
VCRES
Gate Drive Voltage (12)
V
No Current Load
Gate Drive Ability (Internally Supplied)
I
VCRESload
CRES = -1.0 mA
Recommended External Capacitance (C1L – C1H, C2L – C2H, CRES – GND)
CCP
V
µF
Notes
7.
Gate drive voltage VCRES is applied from an external source. 2 x VDD + VM must be < VCRES max (13.5 V).
8.
V
No internal charge pump used. CRES is applied from an external source.
9.
10.
11.
V
V
RDS(ON) is not guaranteed if CRES - VM < 5.0 V. Also, function is not guaranteed if CRES - VM < 3.0 V.
I
QVDD includes the current to pre-driver circuit.
I
VDD includes the current to predriver circuit at fIN = 100 kHz.
12.
At fIN = 20 kHz.
13.
Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. VCRES is
V
applied from an external source. 2 x VDD + VM must be < CRES max (13.5 V).
14.
IO = 0.7 A source + sink.
17531A
6
Analog Integrated Circuit Device Data
Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VIN
0
–
VDD
V
High-Level Input Voltage
VIH
VDD x 0.7
–
–
V
Low-Level Input Voltage
VIL
–
–
VDD x 0.3
V
High-Level Input Current
IIH
–
–
1.0
µA
Low-Level Input Current
IIL
-1.0
–
–
µA
IIL- PSAVE
–
50
100
µA
CONTROL LOGIC
Logic Input Voltage
Logic Inputs (2.7 V < VDD < 3.3 V)
PSAVE Terminal Input Current Low
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Pulse Input Frequency
f IN
–
–
200
kHz
Input Pulse Rise Time (15)
tR
–
–
1.0
µs
Input Pulse Fall Time (17)
tF
–
–
1.0
µs
t PLH
t PHL
–
0.1
0.5
–
0.1
0.5
t VGON
–
1.0
3.0
ms
t VDDDET
–
–
10
ms
INPUT
(16)
(16)
OUTPUT
Propagation Delay Time (18)
Turn-ON Time
Turn-OFF Time
Charge Pump Wake-Up Time (19)
Low-Voltage Detection Time
Notes
15.
16.
17.
18.
19.
µs
Time is defined between 10% and 90%.
That is, the input waveform slope must be steeper than this.
Time is defined between 90% and 10%.
Output load is 8.0 Ω DC.
CCP = 0.1 µF.
17531A
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
TIMING DIAGRAMS
TIMING DIAGRAMS
IN1,
IN2,
PSAVE
V
50%
DDDETon
VDD
tPLH
t
t
VDDDET
90%
OUTA,
OUTB
DDDEToff
50%
0.8 V
tPHL
V
2.5 V
VDDDET
90%
0%
(<1.0 µA)
IM
10%
Figure 5. tPLH, tPHL, and tPZH Timing
Figure 6. Low-Voltage Detection Timing
VDD
t VGON
V
CRES
11 V
Figure 7. Charge Pump Timing
Table 6. Truth Table
INPUT
OUTPUT
Charge Pump and Low
Voltage Detector
PSAVE
IN1A
IN2A
IN1B
IN2B
OUT1A
OUT2A
OUT1B
OUT2B
L
L
L
L
L
RUN
L
H
L
H
L
RUN
L
L
H
L
H
RUN
L
H
H
Z
Z
RUN
H
X
X
Z
Z
STOP
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
PSAVE terminal is pulled up to VDD with internal resistance.
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17531A is a monolithic dual H-Bridge ideal for
portable electronic applications to control bipolar step motors
and brush DC motors such as those found in camera len
assemblies, camera shutters, and optical disk drives. The
device features an on-board charge pump, as well as built-in
shoot-through current protection and undervoltage
shutdown.
The 17531A has four operating modes: Forward, Reverse,
Brake, and Tri-Stated (High Impedance). The MOSFETs
comprising the output bridge have a total source + sink
RDS(ON) ≤ 1.2 Ω.
The 17531A can simultaneously drive two brush DC
motors or one bipolar step motor. The drivers are designed to
be PWM’ed at frequencies up to 200 kHz.
FUNCTIONAL TERMINAL DESCRIPTION
LOGIC SUPPLY (VDD)
MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)
The VDD terminal carries the logic supply voltage and
current into the logic sections of the IC. VDD has an
undervoltage threshold. If the supply voltage drops below the
undervoltage threshold, the output power stage switches to a
tri-state condition. When the supply voltage returns to a level
that is above the threshold, the power stage automatically
resumes normal operation according to the established
condition of the input terminals.
The VM terminals carry the main supply voltage and
current into the power sections of the IC. This supply then
becomes controlled and/or modulated by the IC as it delivers
the power to the loads attached between the OUTput
terminals. All VM terminals must be connected together on
the printed circuit board.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND
IN2B)
These logic input terminals control each H-Bridge output.
IN1A logic HIGH = OUT1A HIGH. However, if all inputs are
taken HIGH, the outputs bridges are both tri-stated (refer to
Table 6, Truth Table, page 9).
POWER SAVE (PSAVE)
The PSAVE terminal is a HIGH = TRUE power save mode
input. When PSAVE = HIGH, all H-Bridge outputs (OUT1A,
OUT1B, OUT2A, and OUT2B) are tri-stated (High-Z),
regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B)
states, and the internal charge pump and low voltage
detection current are shut off to save power.
H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND
OUT2B)
CHARGE PUMP (C1L AND C1H, C2L AND C2H)
These two pairs of terminals, the C1L and C1H and the
C2L and C2H, connect to the external bucket capacitors
required by the internal charge pump. The typical value for
the bucket capacitors is 0.1 µF.
PREDRIVER POWER SUPPLY (CRES)
The CRES terminal is the output of the internal charge
pump. Its output voltage is approximately three times of VDD
voltage. The VCRES voltage is power supply for the internal
predriver circuit of H-Bridges.
POWER GROUND (PGND)
Power ground terminals. They must be tied together on the
PCB.
LOGIC GROUND (LGND)
Logic ground terminal.
These terminals provide connection to the outputs of each
of the internal H-Bridges (see Figure 2, 17531A Simplified
Internal Block Diagram, page 2).
17531A
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
FUNCTIONAL TERMINAL DESCRIPTION
TYPICAL APPLICATIONS
Figure 8 shows a typical application for the 17531A. When
applying the gate voltage to the CRES terminal from an
external source, be sure to connect it via a resistor equal to,
or greater than, RG = VCRES / 0.02 Ω.
The internal charge pump of this device is generated from
the VDD supply; therefore, care must be taken to provide
sufficient gate-source voltage for the high-side MOSFETs
when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.3 V), in order to
ensure full enhancement of the high-side MOSFET channels.
3.3 V 5.0 V
17531A
V
CRES < 14 V
V
RG > CRES /0.02 Ω
RG
NC
NC
NC
NC
0.01 µF
C1L
C1H
C2L
C2H
CRES
VDD
VM
OUT1A
OUT1B
OUT2A
MCU
IN1A
IN1B
IN2A
IN2B
OUT2B
PSAVE
GND
NC = No Connect
Figure 8. 17531A Typical Application Diagram
CEMF SNUBBING TECHNIQUES
PCB LAYOUT
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients via placing a capacitor or zener at the
supply terminal (VM) (see Figure 9).
When designing the printed circuit board (PCB), connect
sufficient capacitance between power supply and ground
terminals to ensure proper filtering from transients. For all
high-current paths, use wide copper traces and shortest
possible distances.
3.3 V
5.0 V
17531A
VM
VDD
3.3 V
5.0 V
17531A
VM
VDD
C1L
C1L
C1H
C1H
C2L
C2H
OUT
C2L
C2H
OUT
CRES
CRES
OUT
OUT
GND
GND
Figure 9. CEMF Snubbing Techniques
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” drawing number listed below.
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
17531A
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
17531A
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
98ARL10577D
ISSUE A
17531A
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
98ARL10577D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
CASE 1508-01
ISSUE A
17531A
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
2.0
9/2005
•
•
Implemented Revision History page
Converted to Freescale format
3.0
2/2008
•
Corrected Table 2, Pin Definitiuons on page 4.
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
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