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SLVS325C − MARCH 2001 − REVISED MAY 2002
FEATURES
D 100-mA Low-Dropout Regulator With EN
D Available in 1.8-V, 3.3-V, 4.7-V, and Adj.
D High PSRR (70 dB at 10 kHz)
D Ultralow Noise (15 µVRMS)
D Fast Start-Up Time (63 µs)
D Stable With Any 1-µF Ceramic Capacitor
D Excellent Load/Line Transient
D Very Low Dropout Voltage
DESCRIPTION
The TPS791xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power supply rejection ratio (PSRR), ultralow
noise, fast start-up, and excellent line and load
transient responses in a small outline, SOT23,
package. Each device in the family is stable, with
a small 1-µF ceramic capacitor on the output. The
family uses an advanced, proprietary BiCMOS
fabrication process to yield extremely low dropout
voltages (e.g., 38 mV at 100 mA, TPS79147).
Each device achieves fast start-up times
(approximately 63 µs with a 0.001 µF bypass
capacitor) while consuming very low quiescent
current (170 µA typical). Moreover, when the
device is placed in standby mode, the supply
current is reduced to less than 1 µA. The
TPS79118 exhibits approximately 15 µVRMS of
output voltage noise with a 0.1 µF bypass
capacitor. Applications with analog components
that are noise sensitive, such as portable RF
electronics, benefit from the high PSRR and low
noise features as well as the fast response time.
(38 mV at Full Load, TPS79147)
D 5-Pin SOT23 (DBV) Package
D TPS792xx Provides EN Options
APPLICATIONS
D Cellular and Cordless Telephones
D VCOs
D RF
D Bluetooth, Wireless LAN
D Handheld Organizers, PDA
2
EN
3
OUT
RIPPLE REJECTION
vs
FREQUENCY
100
4
BYPASS
Fixed Option
DBV PACKAGE
(TOP VIEW)
IN
1
6
OUT
GND
2
5
FB
EN
3
4
BYPASS
VI = 4.3 V
Co = 10 µF
C(byp) = 0.01 µF
90
80
IO = 100 mA
60
IO = 10 mA
40
30
Adjustable Option
20
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
0.4
0.35
VO = 4.3 V
Co = 1 µF
C(byp) = 0.1 µF
0.3
70
50
Hz
GND
5
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Output Spectral Noise Density −
1
Ripple Rejection − dB
IN
TPS79133
µ V/
DBV PACKAGE
(TOP VIEW)
10 M
0.25
0.2
IO = 100 mA
0.15
0.1
IO = 1 mA
0.05
0
100
1k
10 k
f − Frequency − Hz
100 k
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark owned by the Bluetooth SIG, Inc.
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Copyright 2002, Texas Instruments Incorporated
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SLVS325C − MARCH 2001 − REVISED MAY 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TJ
VOLTAGE
PACKAGE
1.2 to 5.5 V
1.8 V
−40°C to 125°C
SOT23
(DBV)
3.3 V
4.7 V
(1) The DBVT indicates tape and reel of 250 parts.
(2) The DBVR indicates tape and reel of 3000 parts.
PART NUMBER
TPS79101DBVT(1)
TPS79101DBVR(2)
SYMBOL
PEUI
TPS79118DBVT(1)
TPS79133DBVT(1)
TPS79118DBVR(2)
TPS79133DBVR(2)
PERI
TPS79147DBVT(1)
TPS79147DBVR(2)
PETI
PESI
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS79101, TPS79118
TPS79133, TPS79147
Input voltage range(2)
−0.3 V to 6 V
Voltage range at EN
−0.3 V to VI + 0.3 V
Voltage on OUT
−0.3 V to 6 V
Peak output current
Internally limited
ESD rating, HBM
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
See Dissipation Rating Table
Operating virtual junction temperature range, TJ
−40°C to 150°C
Operating ambient temperature range, TA
−40°C to 85°C
Storage temperature range, Tstg
−65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
PACKAGE DISSIPATION RATING
BOARD
PACKAGE
RθJC
Low K(1)
High K(2)
DBV
63.75°C/W
DBV
63.75°C/W
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
256°C/W
DERATING FACTOR
ABOVE TA = 25°C
3.906 mW/°C
391 mW
215 mW
156 mW
178.3°C/W
5.609 mW/°C
561 mW
308 mW
RθJA
224 mW
(1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI (1)
Continuous output current, IO (2)
NOM
MAX
UNIT
2.7
5.5
V
0
100
mA
Operating junction temperature, TJ
−40
125
°C
(1) To calculate the minimum input voltage for your maximum output current, use the following formula:
VI(min) = VO(max) + VDO (max load)
(2) Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
2
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SLVS325C − MARCH 2001 − REVISED MAY 2002
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, (TJ = −40 to 125 °C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF,
Co(byp)= 0.01 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TPS79101
TJ = 25°C, 1.22 V ≤ VO ≤ 5.2 V
0 µA< IO < 100 mA(1),
1.22 V ≤ VO ≤ 5.2 V
TPS79118
TJ = 25°C
0 µA < IO < 100 mA, 2.8 V < VI < 5.5 V
TPS79133
TJ = 25°C
0 µA < IO < 100 mA, 4.3 V < VI < 5.5 V
3.234
TPS79147
TJ = 25°C
0 µA < IO < 100 mA, 5.2 V < VI < 5.5 V
4.606
Output voltage
0.98 VO
1.8
1.764
1.836
0 µA < IO < 100 mA, TJ = 25°C
Output voltage line regulation (∆VO/VO)(2)
VO + 1 V < VI ≤ 5.5 V, TJ = 25°C
VO + 1 V < VI ≤ 5.5 V
BW = 100 Hz to 100 kHz,
IO = 100 mA, TJ = 25
25°C
C
RL = 33 Ω,
TJ = 25°C
Time, start-up (TPS79133)
Co = 1 µF,
F,
3.366
4.7
4.794
170
UVLO threshold
5
µA
A
mV
0.05
0.12
C(byp) = 0.001 µF
C(byp) = 0.0047 µF
32
C(byp) = 0.01 µF
C(byp) = 0.1 µF
16
C(byp) = 0.001 µF
C(byp) = 0.0047 µF
53
C(byp) = 0.01 µF
98
VO = 0 V(1)
VCC rising
Output current limit
V
3.3
250
Load regulation
UNIT
1.02 VO
0 µA < IO < 100 mA
Output noise voltage (TPS79118)
MAX
VO
0 µA < IO < 100 mA, TJ = 25°C
Quiescent current (GND current)
TYP
17
%/V
µV
VRMS
15
µs
67
285
600
mA
2.25
2.65
V
UVLO hysteresis
TJ = 25°C, VCC rising
100
mV
(1) The minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum output current
is 100 mA.
(2) If VO ≤ 1.8 V then VImin = 2.7 V, VImax = 5.5 V:
Line regulation (mV) + ǒ%ńVǓ
V
O
ǒV Imax * 2.7 VǓ
100
1000
If VO ≥ 2.5 V then VImin = VO + 1 V, VImax = 5.5 V:
Line regulation (mV) + ǒ%ńVǓ
ǒ
ǒ
ǓǓ
VO V Imax * VO ) 1 V
100
1000
3
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SLVS325C − MARCH 2001 − REVISED MAY 2002
ELECTRICAL CHARACTERISTICS continued
over recommended operating free-air temperature range, (TJ = −40 to 125 °C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF,
Co(byp)= 0.01 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Standby current
High level enable input voltage
EN = VI,
2.7 V < VI < 5.5 V
Low level enable input voltage
2.7 V < VI < 5.5 V
Input current (EN)
EN = VI
f = 100 Hz,
f = 100 Hz,
TPS79118
f = 10 kHz,
f = 100 kHz,
Power supply ripple rejection
f = 100 Hz,
f = 100 Hz,
TPS79133
f = 10 kHz,
f = 100 kHz,
MIN
2.7 V < VI < 5.5 V
MAX
0.07
1
2
−1
TJ = 25°C,
TJ = 25°C,
IO = 10 mA
IO = 100 mA
80
TJ = 25°C,
TJ = 25°C,
IO = 100 mA
IO = 100 mA
72
TJ = 25°C,
TJ = 25°C,
IO = 10 mA
IO = 100 mA
70
TJ = 25°C,
TJ = 25°C,
IO = 100 mA
IO = 100 mA
73
µA
0.7
V
1
µA
75
45
dB
75
37
50
TPS79133
38
TPS79147
IO = 100 mA, TJ = 25°C
IO = 100 mA
(1) IN voltage equals VO(typ) − 100 mV; The TPS79118 dropout voltage is limited by the input voltage range limitations.
UNIT
V
IO = 100 mA, TJ = 25°C
IO = 100 mA
Dropout voltage(1)
4
TYP
90
mV
70
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SLVS325C − MARCH 2001 − REVISED MAY 2002
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
VOUT
VIN
Current
Sense
UVLO
SHUTDOWN
ILIM
_
GND
R1
+
FB
EN
R2
UVLO
Thermal
Shutdown
External to
the Device
250 kΩ
Bandgap
Reference
VIN
Vref
Bypass
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
VOUT
VIN
UVLO
Current
Sense
GND
SHUTDOWN
ILIM
_
R1
+
EN
UVLO
R2
Thermal
Shutdown
VIN
250 kΩ
Bandgap
Reference
Vref
Bypass
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
ADJ
FIXED
BYPASS
4
4
EN
3
3
I
The EN terminal is an input which enables or shuts down the device. When EN is a logic high, the device
will be in shutdown mode. When EN is a logic low, the device will be enabled.
FB
5
N/A
I
This terminal is the feedback input voltage for the adjustable device.
GND
2
2
IN
1
1
I
The IN terminal is the input to the device.
OUT
6
5
O
The OUT terminal is the regulated output of the device.
An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates
a low-pass filter to further reduce regulator noise.
Regulator ground
5
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SLVS325C − MARCH 2001 − REVISED MAY 2002
TYPICAL CHARACTERISTICS
TPS79118
TPS79133
TPS79118
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
3.303
VI = 2.8 V
Co = 10 µF
TJ = 25° C
3.302
V O − Output Voltage − V
1.801
1.8
1.799
1.798
1.797
1.815
3.301
3.3
3.299
3.298
20
40
60
80
IO − Output Current − mA
0
100
20
40
60
80
20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 3
TPS79133
TPS79133
TPS79118
GROUND CURRENT
vs
JUNCTION TEMPERATURE
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
260
Hz
VI = 4.3 V
Co = 10 µF
3.29
IO = 100 mA
3.28
220
200
IO = 1 mA
180
IO = 100 mA
160
140
120
3.27
−40 −25 −10 5
100
20 35 50 65 80 95 110 125
−40 −25 −10 5
TJ − Junction Temperature − °C
20 35 50 65 80 95 110 125
Output Spectral Noise Density −
IO = 1 mA
3.3
VI = 2.8 V
Co = 1 µF
C(byp) = 0.1 µF
0.16
0.14
0.12
IO = 100 mA
0.1
0.08
IO = 1 mA
0.06
0.04
0.02
0
100
TJ − Junction Temperature − °C
Figure 4
0.2
0.18
µ V/
240
Ground Current − µ A
Figure 5
1k
10 k
f − Frequency − Hz
100 k
Figure 6
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
IO = 1 mA
0.15
IO = 100 mA
0.1
0.05
0
100
1k
10 k
f − Frequency − Hz
Figure 7
1.2
1
Output Spectral Noise Density −
0.2
VI = 2.8 V
Co = 10 µF
C(byp) = 0.1 µF
100 k
IO = 0.001 µF
0.8
VI = 2.8 V
IO = 100 mA
Co = 10 µF
IO = 0.1 µF
IO = 0.01 µF
0.4
0.2
0
100
1k
10 k
f − Frequency − Hz
Figure 8
0.35
VI = 4.3 V
Co = 1 µF
C(byp) = 0.1 µF
0.3
IO = 0.0047 µF
0.6
0.4
Output Spectral Noise Density −
0.25
Hz
TPS79118
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
µ V/
TPS79118
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Hz
V O − Output Voltage − V
1.78
−40 −25 −10 5
100
3.31
Hz
IO = 100 mA
1.79
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
VI = 4.3 V
Co = 10 µF
µ V/
1.795
Figure 2
3.32
Output Spectral Noise Density −
IO = 1 mA
1.8
IO − Output Current − mA
Figure 1
6
1.805
1.785
3.297
0
VI = 2.8 V
Co = 10 µF
1.81
µ V/
V O − Output Voltage − V
1.802
1.82
VI = 4.3 V
Co = 10 µF
TJ = 25° C
V O − Output Voltage − V
1.803
100 k
0.25
0.2
IO = 100 mA
0.15
0.1
IO = 1 mA
0.05
0
100
1k
10 k
f − Frequency − Hz
Figure 9
100 k
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SLVS325C − MARCH 2001 − REVISED MAY 2002
1.8
µ V/
VI = 4.3 V
Co = 10 µF
C(byp) = 0.1 µF
0.35
0.3
0.25
IO = 100 mA
0.2
0.15
IO = 1 mA
0.1
0.05
0
100
1k
10 k
f − Frequency − Hz
IO = 0.001 µF
1.6
1.4
IO = 0.0047 µF
1.2
IO = 0.1 µF
1
0.8
IO = 0.01 µF
0.6
0.4
0.2
0
100 k
1k
100
100 k
BW = 100 Hz to 100
kHz
60
50
VO = 3.3 V
40
30
VO = 1.8 V
20
10
0
0.001
Figure 12
TPS79133
TPS79133
TPS792133
OUTPUT IMPEDANCE
vs
FREQUENCY
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
80
VI = 4.3 V
Co = 10 µF
TJ = 25°C
100
VI = 3.2 V,
Co = 10 µF
V DO − Dropout Voltage − mV
70
2
IO = 1 mA
1.5
1
IO = 100 mA
0.5
VI = 3.2 V
CO = 10 µF
90
60
50
IO = 100 mA
40
30
20
IO = 10 mA
10
80
TJ = 125°C
70
60
TJ = 25°C
50
40
30
20
TJ = −40°C
10
0
10
0
100
1k
10 k 100 k
1M
10 M
f − Frequency − Hz
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 13
0
0.02
Minimum Required Input Voltage − V
V DO − Dropout Voltage − mV
100
TJ = 125°C
TJ = 25°C
40
TJ = −40°C
20
4
VI − Input Voltage − V
Figure 16
4.5
5
4.7
90
VI = 3.2 V
Co = 10 µF
4.2
TJ = 125°C
3.7
TJ = −40°C
3.2
TJ = 25°C
70
60
50
30
20
10
2
2.5
3
3.5
4
VO − Output Voltage − V
Figure 17
4.5
5
IO = 100 mA
40
2.7
2.2
1.5
IO = 1 mA
80
Ripple Rejection − dB
5.2
3.5
0.1
TPS79118
IO = 100 mA
3
0.08
RIPPLE REJECTION
vs
FREQUENCY
MINIMUM REQUIRED INPUT VOLTAGE
vs
OUTPUT VOLTAGE
120
60
0.06
Figure 15
TPS79101
80
0.04
IO − Output Current − A
Figure 14
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
0
2.5
0.1
0.01
C(bypass) − Bypass Capacitance − µF
Figure 11
3
Z o − Output Impedance − Ω
10 k
70
f − Frequency − Hz
Figure 10
2.5
VI = 4.3 V
IO = 100 mA
Co = 10 µF
V DO − Dropout Voltage − mV
Output Spectral Noise Density −
2
Hz
0.4
ROOT MEAN SQUARED OUTPUT NOISE
vs
BYPASS CAPACITANCE
µ V (RMS)
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
RMS − Root Mean Squared Output Noise −
TPS79133
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
Output Spectral Noise Density −
µ V/
Hz
TYPICAL CHARACTERISTICS
0
100
VI = 2.8 V
Co = 10 µF
C(byp) = 0.01 µF
1k
10 k
100 k
1M
10 M
f − Frequency − Hz
Figure 18
7
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SLVS325C − MARCH 2001 − REVISED MAY 2002
TYPICAL CHARACTERISTICS
TPS79118
TPS79118
TPS79133
RIPPLE REJECTION
vs
FREQUENCY
RIPPLE REJECTION
vs
FREQUENCY
RIPPLE REJECTION
vs
FREQUENCY
80
IO = 10 mA
60
50
40
IO = 100 mA
60
50
40
30
1k
10 k
100 k
1M
0
100
10 M
100 k
1M
10 M
100
1k
10 k 100 k
f − Frequency − Hz
1M
10 M
Figure 21
TPS79133
TPS79133
RIPPLE REJECTION
vs
FREQUENCY
OUTPUT VOLTAGE, ENABLE VOLTAGE
vs
TIME (START-UP)
80
70
60
IO = 10 mA
80
30
20
20
1M
IO = 10 mA
50
30
10
10 M
100
1k
10 k 100 k
f − Frequency − Hz
1M
10 M
IO = 100 mA
Co = 1 µF
C(byp) = 0.01 µF
10
0
∆ VO − Change In
Output Voltage − mV
TPS79118
LOAD TRANSIENT RESPONSE
VI = 2.8 V
Co = 10 µF
20
0
−20
−10
Current Load − mA
−40
3.8
100
2.8
60 70 80 90 100
t − Time − µs
Figure 25
1
0
3
2
C(byp) = 0.0047 µF
1
C(byp) = 0.01 µF
0
0
20 40
0
0
200 400 600 800 1 k 12 k 14 k 16 k 18 k 2 k
t − Time − µs
Figure 26
60 80 100 120 140 160 180 200
t − Time − µs
Figure 24
TPS79118
30 40 50
VI = 4.3 V
VO = 3.3 V
IO = 100 mA
Co = 1 µF
TJ = 25°C
2
Figure 23
LINE TRANSIENT RESPONSE
10 20
3
C(byp) = 0.001 µF
60
40
1k
10 k 100 k
f − Frequency − Hz
IO = 100 mA
70
40
100
VI = 4.3 V
Co = 1 µF
C(byp) = 0.1 µF
90
IO = 100 mA
Enable Voltage − V
100
VI = 4.3 V
CO = 1 µF
C(byp) = 0.01 µF
0
10
TPS79133
Ripple Rejection − dB
Ripple Rejection − dB
− Output Voltage − mV
O
− Input Voltage − V V
I
V
10 k
RIPPLE REJECTION
vs
FREQUENCY
Figure 22
8
30
Figure 20
100
10
40
f − Frequency − Hz
Figure 19
50
IO = 10 mA
20
1k
f − Frequency − Hz
90
50
V O − Output Voltage − V
0
100
60
VI = 2.8 V
Co = 1 µF
C(byp) = 0.1 µF
10
IO = 100 mA
70
TPS79133
V O − Output Voltage − mV
10
IO = 100 mA
20
VI = 2.8 V
Co = 1 µF
C(byp) = 0.01 µF
80
V I − Input Voltage − V
20
70
Ripple Rejection − dB
70
30
VI = 4.3 V
Co = 10 µF
C(byp) = 0.01 µF
90
IO = 10 mA
Ripple Rejection − dB
80
Ripple Rejection − dB
100
90
90
LINE TRANSIENT RESPONSE
20
0
−20
5.3
4.3
IO = 100 mA
Co = 1 µF
C(byp) = 0.01 µF
0
5
10
15 20
dv
0.4 V
+
µs
dt
25
30
t − Time − µs
Figure 27
35 40
45 50
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SLVS325C − MARCH 2001 − REVISED MAY 2002
TYPICAL CHARACTERISTICS
TPS79118
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
TPS79133
Ω
VI = 4.3 V
Co = 10 µF
20
ESR − Equivalent Series Resistance −
∆ V − Change In
O
I O − Output Current − mA Output Voltage − mV
LOAD TRANSIENT RESPONSE
0
−20
−40
100
0
0
100
Co = 0.47 µF
VI = 5.5 V
TJ = −40 °C to 125°C
10
Region of Instability
1
0.1
Region of
Instability
0.01
50 100 150 200 250 300 350 400 450 500
0
t − Time − µs
0.02
Figure 28
Ω
Co = 1 µF
VI = 5.5 V
TJ = −40 °C to 125°C
Region of Instability
1
0.1
Region of Stability
0.01
0.04
0.06
0.08
IO − Output Current − A
Figure 30
0.1
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
ESR − Equivalent Series Resistance −
Ω
ESR − Equivalent Series Resistance −
100
0.02
0.08
TPS79118
TPS79118
0
0.06
Figure 29
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
10
0.04
IO − Output Current − A
0.1
100
Co = 10 µF
VI = 5.5 V
TJ = −40 °C to 125°C
10
Region of Instability
1
0.1
Region of Stability
0.01
0
0.02
0.04
0.06
0.08
0.1
IO − Output Current − A
Figure 31
9
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SLVS325C − MARCH 2001 − REVISED MAY 2002
APPLICATION INFORMATION
The TPS791xx family of low-dropout (LDO) regulators have been optimized for use in noise-sensitive
battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output
noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA
when the regulator is turned off.
A typical application circuit is shown in Figure 32.
TPS791xx
VI
1
IN
BYPASS
OUT
0.1 µF
4
5
VO
3
0.01 µF
EN
+
GND
1 µF
2
Figure 32. Typical Application Circuit
EXTERNAL CAPACITOR REQUIREMENTS
A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS791xx, is required for stability and to improve transient response, noise rejection, and ripple rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
Like all low dropout regulators, the TPS791xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 1 µF. Any 1 µF or larger ceramic
capacitor is suitable. The device is also stable with a 0.47 µF ceramic capacitor with at least 75 mΩ of ESR.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS791xx has a BYPASS pin
which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor,
in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to
reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator
to operate properly, the current flow out of the BYPASS pin must be at a minimum because any leakage current
creates an IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor
must have minimal leakage current.
For example, the TPS79118 exhibits approximately 15 µVRMS of output voltage noise using a 0.1 µF ceramic
bypass capacitor and a 1 µF ceramic output capacitor. Note that the output starts up slower as the bypass
capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250 kΩ
resistor and external capacitor.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at
the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly
to the ground pin of the device.
10
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SLVS325C − MARCH 2001 − REVISED MAY 2002
POWER DISSIPATION AND JUNCTION TEMPERATURE
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
P
T max * T
A
+ J
D(max)
R
qJA
(1)
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package, see the dissipation rating table.
TA is the ambient temperature.
The regulator dissipation is calculated using:
P
D
ǒ
+ V *V
I
O
Ǔ
I
O
(2)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the
thermal protection circuit.
PROGRAMMING THE TPS79101 ADJUSTABLE LDO REGULATOR
The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider as
shown in Figure 33. The output voltage is calculated using:
V
O
+V
ǒ1 ) R1
Ǔ
R2
ref
(3)
Where:
Vref = 1.2246 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should
be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VO. The recommended
design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and
then calculate R1 using:
R1 +
ǒ
V
V
Ǔ
O *1
ref
R2
(4)
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor
be placed between OUT and FB. For voltages <1.8 V, the value of this capacitor should be 100 pF. For voltages
>1.8 V, the approximate value of this capacitor can be calculated as:
C1 +
(3
10*7)
(R1
(R1 ) R2)
R2)
(5)
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum
recommended output capacitor is 2.2 µF instead of 1 µF.
11
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SLVS325C − MARCH 2001 − REVISED MAY 2002
TPS79101
VI
OUTPUT VOLTAGE
PROGRAMMING GUIDE
IN
1 µF
≥2V
EN
OUT
VO
C1
R1
≤ 0.7 V
0.01 µF
BYPASS FB
GND
1 µF
OUTPUT
VOLTAGE
R1
R2
C1
2.5 V
31.6 kΩ 30.1 kΩ
22 pF
3.3 V
51 kΩ 30.1 kΩ
15 pF
3.6 V
59 kΩ 30.1 kΩ
15 pF
R2
Figure 33. TPS79101 Adjustable LDO Regulator Programming
REGULATOR PROTECTION
The TPS791xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might
be appropriate.
The TPS791xx features internal current limiting and thermal protection. During normal operation, the TPS791xx
limits output current to approximately 400 mA. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum
voltage ratings of the device. If the temperature of the device exceeds approximately 165°C, thermal-protection
circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation
resumes.
12
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SLVS325C − MARCH 2001 − REVISED MAY 2002
MECHANICAL DATA
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,50
0,30
0,95
5
0,20 M
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0°−8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-4/F 10/00
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-178
13
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SLVS325C − MARCH 2001 − REVISED MAY 2002
MECHANICAL DATA
DBV (R-PDSO-G6)
PLASTIC SMALL-OUTLINE
0,95
6X
6
0,50
0,25
0,20 M
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0°−8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-5/F 10/00
NOTES:A.
B.
C.
D.
E.
14
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Leads 1, 2, 3 are wider than leads 4, 5, 6 for package orientation.
Pin 1 is located below the first letter of the top side symbolization.
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