ETC BQ71501DCKR

TPS71525
TPS71533
TPS71501
Actual Size
(2,15 mm x 2,3 mm)
SLVS338C – MAY 2001 – REVISED APRIL 2002
HIGH INPUT VOLTAGE, MICROPOWER
SC70/SOT-323 PACKAGED 50-mA LDO LINEAR REGULATORS
FEATURES
D 50-mA Low-Dropout Regulator
D Available in 2.5 V, 3.3 V, and Adjustable
D 24-V Maximum Input Voltage
D Low 3.2-µA Quiescent Current at 50 mA
D 5-Pin SC70/SOT-323 (DCK) Package
D Stable With Any Capacitor (>0.47 µF)
D Over Current Limitation
D –40°C to 125°C Operating Junction
APPLICATIONS
D Battery Management
D Microcontroller
D PDAs and Notebooks
DCK PACKAGE
(TOP VIEW)
Temperature Range
DESCRIPTION
The TPS715xx low-dropout (LDO) voltage regulators
offer the benefits of high input voltage, low-dropout
voltage, low-power operation, and miniaturized
packaging. The devices, which operate over an input
range of 2.5 V to 24 V, are stable with any capacitor
(>0.47 µF). The low dropout voltage and low quiescent
current allow operations at extremely low power levels.
Therefore, the devices are ideal for powering battery
management ICs. Specifically, since the devices are
enabled as soon as the applied voltage reaches the
minimum input voltage, the output is quickly available to
power continuously operating battery charging ICs.
FB/NC
1
GND
2
NC
3
5
OUT
4
IN
The usual PNP pass transistor has been replaced by a
PMOS pass element. Because the PMOS pass element
behaves as a low-value resistor, the low dropout
voltage, typically 415 mV at 50 mA of load current, is
directly proportional to the load current. The low
quiescent current (3.2 µA typically) is stable over the
entire range of output load current (0 mA to 50 mA).
AVAILABLE OPTIONS†
TJ
40°C to 125°C
–40°C
VOLTAGE
PACKAGE
PART NUMBER
25V
2.5
SC70/SOT 323
SC70/SOT-323
(DCK)
TPS71525DCKR
33V
3.3
SC70/SOT-323
SC70/SOT
323
(DCK)
TPS71533DCKR
(Adjustable)
1.2 V–15 V
SC70/SOT 323
SC70/SOT-323
(DCK)
TPS71501DCKR
bq71525DCKR
bq71533DCKR
bq71501DCKR
SYMBOL
AQL
AQI
ARB
† Contact the factory for other voltage options between 1.25 V and 5.85 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
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1
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Ĕ
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 24 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
ESD rating, CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
BOARD
PACKAGE
RθJC
°C/W
Low K‡
High K§
DCK
165.39
RθJA
°C/W
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
396.24
2.52 mW/°C
252 mW
139 mW
101 mW
DCK
165.39
314.74
3.18 mW/°C
318 mW
175 mW
127 mW
‡ The JEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two layer board with 2 ounce copper traces on top of the board.
§ The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground
planes and 2 ounce copper traces on top and bottom of the board.
recommended operating conditions
MIN
Input voltage
voltage, VI (see Note 2)
IO = 10 mA
IO = 50 mA
Continuous output current, IO (see Note 3)
NOM
MAX
2.5
24
3
24
0
50
UNIT
V
mA
Operating junction temperature, TJ
–40
125
°C
NOTES: 2. To calculate the minimum input voltage for your maximum output current, use the following formula:
VI(min) = VO(max) + VDO (max load)
3. Continuous output current is limited by internal protection circuitry, but it is not recommended that the device operate under
conditions beyond those specified in this table for extended periods of time.
2
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TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
electrical characteristics over recommended operating free-air temperature range,
VI = VO(typ) + 1 V, IO = 1 mA, Co = 1 µF, (unless otherwise noted)
PARAMETER
Out ut voltage (100 µA to 50
Output
mA Load) (see Note 4)
TEST CONDITIONS
TPS71501
1.2 V ≤ VO ≤ 15 V
1.2 V ≤ VO ≤ 15 V
TPS71525
TJ = 25°C,
TJ = –40°C to 125°C,
3.5 V < VI < 24 V
TPS71533
TJ = 25°C,
TJ = –40°C to 125°C,
4.3 V < VI < 24 V
TJ = 25°C,
TJ = –40°C to 85°C,
0 < IO < 50 mA
Quiescent current (GND current)
Load regulation
Out ut voltage line regulation (∆VO/VO)
Output
(see Note 4)
Output noise voltage
Output current limit
Power supply ripple rejection
Dropout voltage (see Note 5)
MIN
TJ = 25°C,
TJ = –40°C to 125°C,
TJ = –40°C to 125°C,
TJ = –40°C to 125°C,
3.5 V < VI < 24 V
4.3 V < VI < 24 V
TYP
0.96 VO
MAX
1.04 VO
2.5
2.4
2.6
3.432
3.2
4.2
4.8
IO = 50 mA, VI = 24 V
IO = 100 µA to 50 mA
VO + 1 V < VI ≤ 24 V
TJ = –40°C to 125°C,
TJ = 25°C,
Co = 10 µF,
VO + 1 V < VI ≤ 24 V
BW = 200 Hz to 100 kHz,
IO = 50 mA
VO = 0 V,
TJ = 25°C,
See Note 4
f = 100 kHz,
TJ = 25°C,
TJ = –40°C to 125°C,
IO = 50 mA
IO = 50 mA
µA
A
5.8
22
mV
20
60
mV
µVrms
575
125
Co = 10 µF
V
3.3
3.168
IO = 50 mA
IO = 50 mA
TJ = 25°C,
TJ = 25°C,
UNIT
750
60
mA
dB
415
750
mV
NOTES: 4. The maximum IN voltage is 24 V. There is no minimum output current and the maximum output current is 50 mA.
5. IN voltage equals VO(typ) –100 mV; The TPS71533 input voltage is set to 3.2 V.
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3
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
functional block diagram – adjustable version
VOUT
VIN
Current
Sense
ILIM
_
R1
+
GND
FB
Bandgap
Reference
VIN
R2
Vref = 1.205 V
functional block diagram – fixed version
VOUT
VIN
Current
Sense
ILIM
_
R1
+
GND
Bandgap
Reference
VIN
R2
Vref = 1.205 V
Terminal Functions
TERMINAL
NAME
NO.
FB
1
GND
2
IN
4
NC
1
NC
3
OUT
5
4
I/O
DESCRIPTION
This terminal is the feedback input voltage for the adjustable device.
Ground
I
The IN terminal is the power supply input to the device.
No connection for fixed options devices
No connection
O
The OUT terminal provides the regulated output voltage of the device.
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TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
4.5
3.32
3.315
3.31
3.310
3.305
3.300
3.295
IO = 1 mA
3.30
IO = 50 mA
3.29
3.28
3.27
3.290
0
10
20
30
40
2
–40 –25 –10 5
Figure 3
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
600
18
IO = 1 mA
16
6
5
VI = 4.3 V
VO = 3.3 V
Co = 1 µF
TJ = 25°C
IO = 50 mA
4
3
2
14
12
10
8
6
IO = 1 mA
4
2
1
0
0
100
1k
10 k
f – Frequency – Hz
100 k
100
1k
TPS791501
600
1
IO = 200 mA
V DO – Dropout Voltage – mV
0.9
TJ = 125°C
0.7
TJ = 25°C
0.5
0.4
TJ = –40°C
0.3
0.2
0
3
6
9
VI – Input Voltage – V
Figure 7
200
TJ = –40°C
100
0
10k
100k
1M
10 M
500
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VI = 3.2 V
Co = 1 µF
IO = 50 mA
400
300
200
IO = 10 mA
100
0.1
0
TJ = 25°C
300
0
10
20
30
40
IO – Output Current – mA
Figure 5
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
0.6
TJ = 125°C
400
f – Frequency – Hz
Figure 4
0.8
VI = 3.2 V
CO = 1 µF
500
IO = 50 mA
10
12
15
0
–40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
Figure 8
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50
Figure 6
POWER SUPPLY RIPPLE REJECTION
vs
FREQUENCY
PSRR – Power Supply Ripple Rejection – dB
7
VI = 4.3 V
VO = 3.3 V
Co = 1 µF
V DO – Dropout Voltage – mV
8
20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
OUTPUT IMPEDANCE
vs
FREQUENCY
Zo – Output Impedance –Ω
Hz
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
µ V/
2.5
Figure 2
Figure 1
Output Spectral Noise Density –
3
3.25
–40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free–Air Temperature – °C
50
IO – Output Current – mA
V DO – Dropout Voltage – V
3.5
VI = 4.3 V
Co = 1 µF
3.26
VI = 4.3 V
VO = 3.3 V
Co = 1 µF
4
Quiesecent Current – µ A
VI = 4.3 V
Co = 1 µF
TJ = 25°C
V O – Output Voltage – V
V O – Output Voltage – V
3.320
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
100
VI = 4.3 V
VO = 3.3 V
Co = 10 µF
TJ = 25°C
90
80
70
60
IO = 1 mA
50
40
30
IO = 50 mA
20
10
0
10
100
1k
10k
100k
1M
10 M
f – Frequency – Hz
Figure 9
5
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
POWER UP / POWER DOWN
8
VO = 3.3 V
RL = 66 Ω
6
VO = 3.3 V
IO = 50 mA
Co = 10 µF
100
50
0
4
3
VI
2
VO
1
0
0
2
4
6
8 10 12 14
t – Time – ms
16 18
20
–50
LOAD TRANSIENT RESPONSE
VI = 4.3 V
VO = 3.3 V
Co = 10 µF
400
200
0
-200
5.3
4.3
0
50 100 150 200 250 300 350 400 450 500
∆ V – Change In
O
Output Voltage – mV
V
O
5
V – Input Voltage – V
I
V
– Output Voltage – V
O
V – Input Voltage – V
I
7
LINE TRANSIENT RESPONSE
I O – Output Current – mA
– Output Voltage – mV
TYPICAL CHARACTERISTICS
60
40
20
0
Figure 10
0 100 200 300 400 500 600 700 800 900 100
t – Time – µs
t – Time – ms
Figure 11
Figure 12
APPLICATION INFORMATION
The TPS715xx family of LDO regulators has been optimized for use with battery management ICs. After the
minimum input voltage requirement is met, it is always enabled. The device’s maximum input voltage is 24 V.
It has a dropout voltage of 415 mV at 50 mA, and its quiescent current is 3.2 µA typically. A typical application
circuit is shown in Figure 13.
4
VI
C1
0.1 µF
IN
OUT
3
5
VO
NC
1
+
NC/FB
GND
0.47 µF
2
Figure 13. Typical Application Circuit
external capacitor requirements
Although not required, a 0.047-µF or larger input bypass capacitor, connected between IN and GND and located
close to the device, is recommended to improve transient response and noise rejection. A higher-value
electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the
device is located several inches from the power source.
Like all low-dropout regulators, the TPS715xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 0.47 µF. Any 0.47µ-F capacitor
is suitable. Capacitor values larger than 0.47 µF are acceptable.
6
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TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
APPLICATION INFORMATION
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; restrict the maximum junction
temperature to 125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
P
D(max)
T max * T
A
+ J
R
qJA
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package (see the Dissipation Rating Table).
TA is the ambient temperature.
The regulator dissipation is calculated using:
P
D
ǒ
Ǔ
+ V *V
I
O
I
O
Power dissipation resulting from quiescent current is negligible.
regulator protection
The TPS715xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might
be appropriate.
The TPS715xx features internal current limiting. During normal operation, the TPS715xx limits output current
to approximately 500 mA. When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. Take care not to exceed the power dissipation ratings of the package.
programming the TPS71501 adjustable LDO regulator
The output voltage of the TPS71501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 14. The output voltage is calculated using:
V
O
+V
ref
ǒ1 ) R1
Ǔ
R2
(3)
Where:
Vref = TBD V typ (the internal reference voltage)
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7
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
APPLICATION INFORMATION
programming the TPS71501 adjustable LDO regulator (continued)
Resistors R1 and R2 should be chosen for approximately 1.5-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should
be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VO. The recommended
design procedure is to choose R2 = 1 MΩ to set the divider current at 1.5 µA, and then calculate R1 using:
R1 +
ǒ
V
V
Ǔ
O *1
ref
(4)
R2
TPS71501
VI
0.1 µF
OUTPUT VOLTAGE
PROGRAMMING GUIDE
IN
VO
OUT
R1
0.47 µF
FB
GND
OUTPUT
VOLTAGE
R1
R2
1.8 V
0.499 MΩ
1 MΩ
2.8 V
1.33 MΩ
1 MΩ
5.0 V
3.16 MΩ
1 MΩ
R2
Figure 14. TPS71501 Adjustable LDO Regulator Programming
battery management application
One application for which this device is particularly suited is providing a regulated voltage from a much larger
input voltage, as is often the case of ICs used in portable battery-powered devices. Many of the battery
management ICs currently on the market monitor battery voltages above 20 V. However, the IC’s internal
circuitry and peripheral equipment, like an LED’s, generally need a lower power bus for operation. Some of the
battery management ICs have internal LDO regulator controllers that require five or more external components
in order to provide a regulated output voltage. The TPS715xx family has a maximum input voltage rating of
24 V, provides up to 50 mA of output current, and requires only one external component. Therefore, using one
of the TPS715xx regulators to power battery management ICs is a much simpler, more compact, and less
expensive solution than using onboard LDO regulator controllers. In addition, the TPS715xx family uses only
3.2 µA of quiescent current and does not significantly decrease battery life while the device is inactive.
TI’s bq2060 gas gauge IC was chosen to demonstrate the use of the TPS71533. The bq2060 battery
management IC requires a regulated 3.3 V for normal operation. The bq2060 has a regulator controller output
(REG) that, when used in conjunction with an external JFET (Q2), a bipolar transistor (Q1), two capacitors (C1
and C2), and one resistor (R1), forms a 3.3-V output linear regulator as shown in Figure 15.
8
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TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
APPLICATION INFORMATION
3
BAT+
2
1
Q1
MMBT3904
1 R1
VCC
2
1 kΩ
1
C1
Q2
SST113
D
U1
1
G
S
1 R2
100 kΩ
S1
24
Device
1 R3
2
HDQ16
ESCL
3
ESDA
VCELL4
RBI
RBG
VCELL3
4
5
2
31
2
0.1 µF
2
10 kΩ
1 R4 2
6
7
VOUT
VCC
8
VSS
9
DISP
10
LED1
11
LED2
12
LED3
13
14
LED4
LED5
10 kΩ
SMBC
SMBD
28
27
26
25
24
VCELL2
23
VCELL1
22
SR1
21
SR2
20
SRC
19
TS
18
THon
17
CVon
16
CFC
15
DFC
BQ2060
1
U2
1
2
3
SCL
VSS
SDA
WP
VCC
C2
5
D1
Color
4
D2
Color
24LC01
D3
Color
D4
Color
D5
Color
BAT–
2
.001 µF
R5
330 Ω
R6
330 Ω
R7
330 Ω
R8
330 Ω
R9
330 Ω
1
2
R10
0.030 W
Figure 15. bq2060 Powered With Internal LDO Controller
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9
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
APPLICATION INFORMATION
However, with five external components, this regulator is more complex and costly than using a separate LDO
regulator. Figure 16 shows the TPS71533 and its external output capacitor (C1) providing the regulated 3.3 V
to the bq2060.
U2
TPS71533
1
OUT
2
5
GND
3
IN
4
BAT+
1
C1
1 R1
2
U1
0.47 µF
1
100 kΩ
S1
24
Device
1 R2
3
ESDA
VCELL4
RBI
RBG
VCELL3
4
5
2
31
2
HDQ16
ESCL
2
10 kΩ
1 R3 2
6
7
VOUT
VCC
8
VSS
9
DISP
10
LED1
11
LED2
12
LED3
13
14
LED4
LED5
10 kΩ
SMBC
SMBD
U3
2
3
SCL
VSS
SDA
WP
VCC
5
D1
Green
4
24LC01
D2
Green
D3
Green
D4
Green
D5
Green
BAT–
R4
470 Ω
R5
470 Ω
R6
470 Ω
R7
470 Ω
R8
470 Ω
1
2
R9
0.030 W
Figure 16. bq2060 Powered With TPS71533
10
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27
26
25
24
VCELL2
23
VCELL1
22
SR1
21
SR2
20
SRC
19
TS
18
THon
17
CVon
16
CFC
15
DFC
BQ2060
1
28
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
APPLICATION INFORMATION
In Figure 16, the bq2060 is configured to monitor 4 Li-Ion batteries in series totaling 16.8 V. During either battery
charging or discharging, the maximum current that the bq2060 requires from the TPS71533 occurs when the
user presses the push button (S1) and potentially activates all five LEDs, indicating a fully charged battery. The
LEDs require 3 mA each and remain on for 4 seconds and then off for 2 seconds. Therefore, the bq2060
potentially requires a total of 15 mA for 67% duty cycle and thus the total power dissipated by the TPS71533
would not exceed 136 mW [(16.8 V – 3.3 V) x 15 mA x 67%]. Therefore, power dissipation is not a concern in
this application. When the LEDs are not activated, the bq2060 only requires approximately 200-µA quiescent
current. For more information on the operation of the bq2060, refer to the data sheet (TI literature number
SLUS035). An evaluation module with a similar configuration to the one shown in Figure 16 is also available
(TI literature number SLUU063).
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11
TPS71525
TPS71533
TPS71501
SLVS338C – MAY 2001 – REVISED APRIL 2002
MECHANICAL DATA
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,30
0,15
0,65
5
0,10 M
4
1,40
1,10
1
0,13 NOM
2,30
1,90
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553/B 06/99
NOTES: A.
B.
C.
D.
12
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
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