SY89540U Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination General Description The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates up to 3.2Gbps over temperature and voltage. The SY89540U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC or DC-coupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. The LVDS compatible outputs maintain extremely fast rise/fall times guaranteed to be less than 120ps. The SY89540U features a patent-pending isolation design that significantly improves on channel-tochannel crosstalk performance. The SY89540U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). The SY89540U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at www.micrel.com. Typical Performance OUTPUT SWING (100mV/div.) 2.5Gbps Output Precision Edge® Features • Provides crosspoint switching between any input pairs to any output pair • Patent pending, channel-to-channel isolation design provides superior crosstalk performance • Guaranteed AC performance over temperature and voltage: • DC-to-3.2Gbps throughput – <480ps propagation delay – <120ps rise/fall time – <30ps output-to-output skew • Ultra-low jitter design: – <1psRMS random jitter – <10psPP deterministic jitter – <10psPP total jitter (clock) – <0.7psRMS crosstalk induced jitter • Patent pending 50 input termination, extended CMVR, and VT pin accepts DC- and AC-coupled differential inputs • 350mV LVDS output swing • Power supply 2.5V ±5% • –40°C to +85°C temperature range • Available in 44-pin (7mm x 7mm) MLF™ package • Pb-Free Green package Applications TIME (100ps/div.) • All SONET/SDH channel select applications • All Fibre Channel multi-channel select applications • All Gigabit Ethernet multi-channel select applications Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. April 2005 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Functional Block Diagram I N0 50Ω VT0 0 50Ω /I N0 Vref_AC0 1 Q0 2 /Q 0 3 0 I N1 50Ω VT1 50Ω /I N1 1 Q1 2 /Q 1 Vref_AC1 3 0 I N2 50Ω VT2 50Ω /I N2 Vref_AC2 1 Q2 2 /Q 2 3 0 I N3 50Ω VT3 1 Q3 2 /Q 3 3 50Ω /I N3 Vref_AC3 SIN0 (CMOS/TTL ) SIN1 (CMOS/TTL ) SOUT0 (CM OS/TTL ) SOUT1 (CM OS/TTL ) CONF (CM OS/TTL) L OAD (CMOS/TTL ) April 2005 CO NT RO L 2 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Ordering Information(1) Package Type Temperature Range Package Marking Lead Finish MLF-44 Industrial 89540U Sn-Pb SY89540UMITR MLF-44 Industrial 89540U Sn-Pb SY89540UMG MLF-44 Industrial 89540U with Pb-Free bar-line indicator Pb-Free NiPdAu SY89540UMGTR(2) MLF-44 Industrial 89540U with Pb-Free bar-line indicator Pb-Free NiPdAu Part Number SY89540UMI (2) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electrical only. 2. Tape and Reel ordering option. GND GND VREF_AC3 IN3 VT3 /IN3 SOUT0 SOUT1 GND GND VCC Pin Configuration 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 /Q3 Q3 VCC /Q2 Q2 VCC /Q1 Q1 VCC /Q0 Q0 GND GND VREF_AC0 /IN0 VT0 IN0 SIN0 SIN1 GND GND VCC VREF_AC2 /IN2 VT2 IN2 CONFIG VCC LOAD /IN1 VT1 IN1 VREF_AC1 44-Pin MLF™ (MLF-44) April 2005 3 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Pin Description Pin Number Pin Name Pin Function 17, 15, 10, 8 4, 2 41, 39 IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. 16, 9, 3, 40 VT0, VT1, VT2, VT3 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. 14, 11, 1, 42 VREF_AC0, VREF_AC1, VREF_AC2, VREF_AC3 Reference Voltage: This output biases to VCC–1.2V. It is used when ACcoupling the inputs (IN, /IN). Connect VREF_AC to the VT pin. Bypass each VREF-AC pin with a 0.01µF low ESR capacitor. See "Input Interface Applications" section for more details. 18, 19 SIN0, SIN1 These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs are internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. 38, 37 SOUT0, SOUT1 These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. 5, 7 CONF, LOAD These single-ended TTL/CMOS-compatible inputs control the transfer of the addresses to the internal multiplexers. See "Address Tables" and "Timing Diagram" sections for more details. Note that these inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. Configuration Sequence 1. Load: Loads configuration into buffer, while Configuration Buffer holds existing switch configuration. 2. Configuration: Loads new configuration into the Configuration Buffer and updates switch configuration. Buffer Mode The SY89540U defaults to buffer mode (IN to Q) if the load and configuration control signals are not exercised. 23, 24, 26, 27, 29, 30, 32, 33 Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, 6, 22, 25, 28, 31, 34 VCC 12, 13, 20, 21,35, 36, 43, 44 GND, Exposed pad April 2005 Differential Outputs: These LVDS output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 350mV into 100 across the pair. Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each VCC pin. Ground. GND and EPad must both be connected to the same ground. 4 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC)............................. –0.5V to +4.0V Input Voltage (VIN)..................................... –0.5V to VCC CML Output Voltage (VOUT) .......VCC–1.0V to VCC+5.0V Termination Current(3) Source or sink current on VT..................... ±100mA Input Current Source or sink current on IN, /IN................ ±50mA VREF-AC Current Source or sink current on VREF-AC ................. ±2mA Lead Temperature (soldering, 20sec.)............... 260°C Storage Temperature (Ts) .................–65°C to +150°C Supply Voltage (VCC) ....................+2.375V to +2.625V Ambient Temperature (TA) .................. –40°C to +85°C Package Thermal Resistance(4) MLF™ (JA) Still-air ............................................................... 23°C/W MLF™ (JB) Junction-to-board.............................................. 12°C/W DC Electrical Characteristics(5) TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter Condition Min Typ Max Units VCC Power Supply VCC = 2.5V 2.375 2.5 2.625 V ICC Power Supply Current No load, max. VCC. 200 280 mA RDIFF_IN Differential Input Resistance (IN-to-/IN) 80 100 120 RIN Input Resistance (IN-to-VT, /IN-to-VT) 40 50 60 VIH Input HIGH Voltage (IN, /IN) VCC–1.6 VCC V VIL Input LOW Voltage (IN, /IN) 0 VIH–0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 1a. 100 1700 mV VDIFF_IN Differential Input Voltage |IN, /IN| See Figure 1b. 200 IN-to-VT Maximum Input Voltage |IN-to-VT| VREF-AC Reference Voltage Note 6 VCC–1.3 mV VCC–1.2 1.28 V VCC–1.1 V Notes: 1. Permanent device damage may occur if ratings in the “Absolute Maximum Ratings” section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to limited drive capability use for input of the same package only. 4. Assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. JB uses a 4-layer JA in still-air unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIH (min) not lower than 1.2V. April 2005 5 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U LVDS Outputs DC Electrical Characteristics VCC = 2.5V ±5%, TA = –40°C to +85°C, RL = 100 across Q and /Q, unless otherwise noted. Symbol Parameter Condition Min Typ Max Units VOH Output HIGH Voltage (Q, /Q) 1.475 V VOL Output LOW Voltage (Q, /Q) VOUT Output Voltage Swing (Q, /Q) See Figure 1a. 250 350 mV VDIFF_OUT Differential Output Voltage Swing |Q – /Q| See Figure 1b. 500 700 mV VOCM Output Common Mode Voltage (Q, /Q) See Figure 4b. 1.125 1.275 V VOCM Change in Common Mode Voltage (Q, /Q) See Figure 4b. –50 +50 mV Max Units VCC V 0.8 V 30 µA 0.925 V LVTTL/CMOS DC Electrical Characteristics VCC = 2.5V ±5%, TA = –40°C to +85°C, unless otherwise noted. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current IIL Input LOW Current April 2005 Condition Min 2.0 –125 VIL = 0V –300 6 Typ µA M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U AC Electrical Characteristics(7) VCC = 2.5V ±5%, TA = –40°C to +85°C, RL = 100 across each output pair, unless otherwise noted. Symbol Parameter Condition Min Typ fMAX Maximum Operating Frequency NRZ Data 3.2 4 Gbps tPD Propagation Delay Clock, VOUT 200mV 4 GHz IN-to-Q 280 CONFIG-to-Q 350 tPD Tempco tS 380 Max Units 480 160 Set-up Time SIN-to-LOAD SOUT-to-LOAD LOAD-to-CONFIG CONFIG-to-LOAD 800 fs/°C 800 800 800 950 ps th Hold Time LOAD-to-SIN, LOAD-to-SOUT 800 ps tPW Minimum LOAD and CONFIG Pulse Width 800 ps tSKEW Output-to-Output Skew Part-to-Part Skew Note 8 Note 9 30 150 ps ps tJITTER Data Random Jitter (RJ) Deterministic Jitter (DJ) Note 10 Note 11 1 10 psRMS psPP Clock Cycle-to-Cycle Jitter Total Jitter (TJ) Note 12 Note 13 1 psRMS psPP Crosstalk-Induced Jitter Note 14 0.7 psRMS Rise/Fall Times At full output swing (20% to 80%) 120 ps tr, tr 40 80 Notes: 7. High frequency AC-parameters are guaranteed by design and characterization. 8. Output to output skew is measured between two different outputs under identical transitions. Input voltage swing is 100mV. 9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. RJ is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps. 11. DJ is measured at 2.5Gbps/3.2Gpbs, with both K28.5 and 223–1 PRBS pattern 12. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn –Tn-1 where T is the time between rising edges of the output signal. 13. TJ definition: with an ideal clock input of frequency < fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 14. Crosstalk induced jitter is defined as the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs. April 2005 7 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Single-Ended and Differential Swing VIN, VOUT 350mV (typical) VDIFF_IN, VDIFF_OUT 700mV (typical) Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagram Input Address SIN[1:0] Output Address SOUT[1:0] t s (SIN-LOAD) LOAD t h (LOAD-SIN/SOUT) t s (CONFIG-LOAD) t PW t s (SOUT-LOAD) t s (LOAD-CONFIG) CONFIG t PW /IN[3:0] IN[3:0] t PD (CONFIG-Q) t PD /Q[3:0] Invalid** Valid** Q[3:0] **Invalid and Valid refers to configuration being changed. All outputs with unchanged configuration remain valid. Figure 2. Timing Diagram Truth Tables Input Select Address Table Output Select Address Table SIN1 SIN0 Input SOUT1 SOUT0 Output 0 0 IN0 0 0 Q0 0 1 IN1 0 1 Q1 1 0 IN2 1 0 Q2 1 1 IN3 1 1 Q3 April 2005 8 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Typical Operating Characteristics TEMPERATURE (¡C) CHANNEL-to-CHANNEL SKEW (ps) FREQUENCY (MHz) 16 335 900 20 40 60 80 100 120 340 1000 345 -40 -20 0 345 800 350 350 700 5600 5000 4400 3800 3200 2600 2000 800 200 50 1400 100 355 355 600 150 360 500 200 360 365 400 250 365 300 AMPLITUDE (ps) 300 370 Input Voltage Swing vs. Propagation Delay 200 370 PROPAGATION DELAY (ps) 350 Propagation Delay vs. Temperature 100 Amplitude vs. Frequency OUTPUT PROPAGATION DELAY (ps) VCC = 2.5, VIN = 100mV, at 25°C. INPUT VOLTAGE SWING (ps) Channel-to-Channel Skew, Relative to Ch0 14 12 10 8 6 4 2 0 0 1 2 3 4 CHANNEL (ps) April 2005 9 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Functional Characteristics VCC = 2.5, VIN = 100mV, at 25°C. Clock Pattern OUTPUT SWING (80mV/div.) 1.25GHz Output OUTPUT SWING (80mV/div.) 200MHz Output TIME (600ps/div.) TIME (100ps/div.) OUTPUT SWING (80mV/div.) 2.5GHz Output TIME (50ps/div.) Data Pattern OUTPUT SWING (100mV/div.) 3.2Gbps Output OUTPUT SWING (100mV/div.) 1.25Gbps Output TIME (200ps/div.) April 2005 TIME (80ps/div.) 10 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Output Stage Internal Termination Input and Output Stage Internal Termination On a nominal 1.25V common mode above ground, LVDS specifies a small swing of 350mV, typical. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum to keep EMI low. VCC IN VOUT 50Ω VOH, VOL VT 100Ω ±1% VOH, VOL 50Ω /IN GND GND Figure 3. Simplified Differential Input Stage Figure 4a. LVDS Differential Measurement 50Ω 50Ω VCOM V∆COM GND Figure 4b. LVDS Common Mode Measurement April 2005 11 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Input Interface Applications VCC VCC VCC IN IN IN LVPECL CML LVPECL /IN VCC SY89540U 0.1µF GND RP RP GND VT VT GND VREF-AC VREF-AC VCC GND NC VT NC VREF-AC Note: For 3.3V, RP = 100Ω. For 2.5V, RP = 50Ω. Note: For 3.3V, RP = 50Ω. For 2.5V, RP = 19Ω. Figure 5a. LVPECL Interface (DC-Coupled) SY89540U SY89540U 0.1µF NC RP /IN /IN VCC Figure 5b. LVPECL Interface (AC-Coupled) Figure 5c. CML Interface (DC-Coupled) VCC IN IN CML LVDS /IN VCC GND /IN SY89540U SY89540U 0.1µF VT GND VREF-AC Figure 5d. CML Interface (AC-Coupled) NC VT NC VREF-AC Figure 5e. LVDS Interface Related Product and Support Documentation Part Number Function Data Sheet Link SY58540U Ultra Precision 4x4 CML Crosspoint Switch w/Internal I/O Termination http:///www.micrel.com/product-info/products/sy89540u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml MLF™ Application Note www.amkor.com/products/notes_papers/MLF_AppNote.pdf April 2005 12 M9999-042505 [email protected] or (408) 955-1690 Micrel, Inc. SY89540U Package Information 44-Pin MLF™ (MLF-44) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. April 2005 13 M9999-042505 [email protected] or (408) 955-1690