LFTVS7-1F3 Low forward voltage Transil™, transient voltage suppressor Features ■ Low forward voltage: 1.05 V @ 850 mA ■ Peak pulse power (8/20 µs): 350 W ■ Very low clamping factor VCL/VBR ■ Unidirectional device ■ Fast response time ■ Very thin package: 0.605 mm ■ RoHS compliant Flip Chip (4 bumps) Figure 1. Pin configuration (bump side) Complies with the following standards: ■ A IEC 61000-4-2 level 4 – ± 15 kV (air discharge) – ± 8 kV (contact discharge) B 1 2 Description The LFTVS7-1F3 is a single line diode designed specifically for the protection of integrated circuits in portable equipment and miniaturized electronics devices subject to ESD and EOS transient overvoltages. Figure 2. Device configuration A1 and A2 B1 and B2 TM: Transil is a trademark of STMicroelectronics April 2008 Rev 2 1/8 www.st.com Characteristics 1 LFTVS7-1F3 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Test condition Value Peak pulse power dissipation (10/1000 µs pulse) PPP IFSM Tj Tstg Table 2. Peak pulse power dissipation (8/20 µs pulse) Non repetitive surge peak forward current 75 W Tj initial = Tamb 350 tp = 10 ms Tj initial = Tamb 11 A 125 °C -55 to +150 °C Maximum operating junction temperature Storage temperature range Electrical characteristics (Tamb = 25 °C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current αT Voltage temperature coefficient VF Forward voltage drop I IF Symbol Test conditions VF VCL VBR VRM V IRM Slope = 1/Rd Min. Typ. IPP Max. 7 Unit VBR IR = 15 mA V IRM VRM = 5.5V 500 nA VCL IPP = 1 A(1) 10 V VF IF = 850 mA 1.05 αT Cline 6 VR = 0 V, VOSC = 30 mV, F = 1 MHz 1. 8 / 20 µs pulse waveform 2/8 Unit 320 V 10-4 / °C pF LFTVS7-1F3 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tj initial] / PPP[Tj initial=25°C] Peak pulse power versus exponential pulse duration (typical value) PPP(W) 1.1 10000 Tj initial = 25° C 1.0 0.9 0.8 1000 0.7 0.6 0.5 0.4 100 0.3 0.2 0.1 Tj(°C) tp(µs) 10 0.0 0 25 Figure 5. 50 75 100 125 1 150 Clamping voltage versus peak pulse current (typical values) Figure 6. IPP(A) 10 100 1000 Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj=25°C] 10.0 10 tp = 10/1000 µs VR = 5.5 V Tj initial = -30° C Tj initial = 25° C Tj initial = 85° C 1.0 Tj(°C) VCL(V) 1 0.1 5 10 Figure 7. Forward voltage drop versus peak forward current (typical values) 25 50 Figure 8. 75 100 125 150 Junction capacitance versus reverse voltage applied (typical values) Capacitance(pF) IFM(A) 1.E+02 800 Tj initial = 25° C 1.E+01 600 Tj initial = 85° C 1.E+00 400 Tj initial = -30° C 200 1.E-01 VFM(V) Voltage(V) 0 1.E-02 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 1.1 2.2 3.3 4.4 5.5 3/8 Application information Figure 9. LFTVS7-1F3 Breakdown voltage versus initial Figure 10. Frequency response junction temperature (typical value) 0 VBR(V) 9.0 -10 8.0 -20 -30 7.0 -40 Tj(° C) F/Hz 6.0 -50 -40 -15 10 35 60 85 Figure 11. ESD response to IEC 61000-4-2 (+8 kV contact discharge) 100k Figure 13. Application schematic VBUS DD+ GND 4/8 100M 1G X: 20ns/div Y: 10V/div Application information USB CONNECTOR 10M Figure 12. ESD response to IEC 61000-4-2 (-8 kV contact discharge) X: 20ns/div Y: 10V/div 2 1M LFVS7-1F3 LFTVS7-1F3 3 Ordering information scheme Ordering information scheme Figure 14. Ordering information scheme LF TVS 7 - 1 F3 Low forward voltage Transient voltage suppressor Breakdown voltage 7 = 7 VMIN Number of lines 1 = single line Package F = Flip Chip 3: lead free, pitch = 400 µm Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 15. Flip Chip dimensions 0.77 mm ± 30 µm 400 µm ± 40 185 µm ± 10 400 µm ± 40 4 605 µm ± 55 205 µm ± 40 185 µm ± 10 0.77 mm ± 30 µm 255 µm ± 40 5/8 Package information LFTVS7-1F3 Figure 16. Foot print recommendations Figure 17. Marking Dot xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum x x z y ww Solder stencil opening: 220 µm recommended Figure 18. Flip Chip tape and reel specifications Dot identifying Pin A1 location 3.5 ± 0.1 Note: xxz yww All dimensions in mm 0.87 xxz yww xxz yww 8 ± 0.3 0.87 0.71 ± 0.05 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 4 ± 0.1 User direction of unreeling More information is available in the application notes: AN2348: “400 µm Flip Chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" 6/8 LFTVS7-1F3 5 Ordering information Ordering information Table 3. 6 Ordering information Order code Marking Package Weight Base qty Delivery mode LFTVS7-1F3 EJ Flip Chip 0.86 mg 5000 Tape and reel (7”) Revision history Table 4. Document revision history Date Revision Changes 01-Mar-2007 1 Initial release. 16-Apr-2008 2 Updated ECOPACK statement. Updated Figure 14, and Figure 15. Reformatted to current standards. Changed VF from 1.2 to 1.05 V. 7/8 LFTVS7-1F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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