ESDLIN1524BJ TRANSIL™ diode for ESD protection Features ■ Max peak pulse power 160 W (8/20 µs) ■ Asymmetrical bidirectional device ■ Stand-off voltage: 15 and 24 V ■ Low clamping factor VCL/VBR ■ Complies with the following standards : – IEC 61000-4-2 level 4 (> 15 kV air discharge, > 8 kV contact discharge) – IEC 61000-4-5; Ipp= 3 A (8/20 µs) – HBM MIL STD 833, class 3 (> 4 kV) ■ 2 1 SOD-323 Configuration Low Leakage current The ESDLIN1524BJ is an asymmetrical TRANSIL diode designed specifically for protecting one automotive LIN bus line against electrostatic discharge (ESD). The SOD-323 is a very small package which allows space saving on high density printed circuit board . Pin Transil diodes provide high overvoltage protection by clamping action and have instantaneous response to transient overvoltages. Table 1. Description 1 Cathode 1 (15 V reverse stand-off voltage) 2 Cathode 2 (24 V reverse stand-off voltage) Absolute maximum ratings (limiting values) Tamb = 25° C Symbol Parameter PPP Peak pulse power dissipation 8/20 µs Tstg Tj Storage temperature range Operating junction temperature range TL 2 2 1 1 Description (1) Tj initial = Tamb Maximum lead temperature for soldering during 10 s Value Unit 160 W -65 to +175 -40 to 150 °C 260 °C 1. For a surge greater than maximum values, the diode will fail in short-circuit Table 2. ESD Maximum ratings Symbol ESD Parameter Electrostatic discharge capability Conditions Value IEC 61000-4-2 (contact discharge) 23 HBM MIL STD 833 10 Unit kV TM: TRANSIL is a trademark of STMicroelectronics. September 2006 Rev 2 1/7 www.st.com 7 Characteristics ESDLIN1524BJ 1 Characteristics Table 3. Electrical characteristics (Tamb = 25° C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current @ VRM I IPP V C LV B R V R M IR Breakdown current @ VBR IPP Peak pulse current C IR IR M V IR M IR V R MV B R V C L IPP Junction capacitance VBR @ IR (1) IRM @VRM Types nA Typ Max 1 C (2) αT(3) pF 10-4/°C Typ Max Max V V ESDLIN1524BJ(15V) VCL max @ IPP 8/20 µs 50 mA Min V A V A Typ Max 15 17.1 18.9 20.3 5 25 1 35 5 8.8 16 ESDLIN1524BJ(24V) 1 50 24 25.4 27.8 30.3 5 40 1 50 20 3 9.6 1. Pulse test: tp < 50 ms 2. VR = 0 V, F= 1 MHz 3. ∆VBR = αT x (Tamb -25) x VBR(25° C) Figure 1. Relative variation of peak pulse power versus initial junction temperature Figure 2. Peak pulse power versus exponential pulse duration PPP(W) PPP[Tj initial] / PPP [Tj initial=25°C] 1.1 1.E+03 Tj initial =25 °C 1.0 0.9 0.8 0.7 0.6 1.E+02 0.5 0.4 0.3 0.2 0.1 TJ(°C) tP(µs) 0.0 1.E+01 0 2/7 25 50 75 100 125 150 175 1 10 100 ESDLIN1524BJ Figure 3. Characteristics Junction capacitance versus line voltage (typical values), 15 V side Figure 4. Junction capacitance versus line voltage (typical values), 24 V side C(pF) C(pF) 20 20 F=1 MHz VOSC=30mVRMS TJ=25°C 15 V side 18 16 16 14 14 12 12 10 10 8 8 6 6 4 4 2 F=1 MHz VOSC=30 mVRMS TJ=25 °C 24 V side 18 2 VLINE(V) 0 VLINE(V) 0 0 Figure 5. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 12 14 16 18 20 22 24 Clamping test conditions and results 2 ± 1kV ESD Air discharge Voltage probe V 500Ω TEST BOARD 1 Ground plane V:20V/d V:20V/d ESD test configuration t: 50 ns/d Remaining voltage after +1 kV ESD voltage waveform (IEC 61000-4-2 conditions) t: 50 ns/d Remaining voltage after -1 kV ESD voltage waveform (IEC 61000-4-2 conditions) 3/7 Placement and PCB layout recommendations 2 ESDLIN1524BJ Placement and PCB layout recommendations Figure 6. illustrates recommendations for the placement and layout of the PCB for optimum benefit of the ESDLIN1524BJ. Figure 6. Placement and PCB layout recommendations LIN Node Voltage regulator Connector Vbat Gnd MCU LIN 24 LIN Transceiver 15 ESDLIN1524BJ located as close as possible to the connector With Ground wire With Ground plane LIN GND 4/7 Vbat Connector Connector Vbat LIN GND ESDLIN1524BJ 3 Ordering information scheme Ordering information scheme ESDLIN 15 24 B J ESDLIN protection Stand-off voltage 1 15 = 15 V Stand-off voltage 2 24 = 24 V Bidirectional Package J = SOD-323 4 Package information Table 4. SOD-323 dimensions Dimensions H A1 Ref. Millimeters Min. b A E A D c Q1 Max. Inches Min. 1.17 Max. 0.046 A1 0 0.1 0 0.004 b 0.25 0.44 0.01 0.017 c 0.1 0.25 0.004 0.01 D 1.52 1.8 0.06 0.071 E 1.11 1.45 0.044 0.057 H 2.3 2.7 0.09 0.106 L 0.1 0.46 0.004 0.02 Q1 0.1 0.41 0.004 0.016 L 5/7 Ordering information Figure 7. ESDLIN1524BJ SOD-323 footprint (dimensions in millimeters) 3.20 0.54 1.06 1.08 1.06 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5 6 6/7 Ordering information Part number Marking Package Weight Base qty Delivery mode ESDLIN1524BJ 24 SOD-323 5 mg 3000 Tape and reel Revision history Date Revision Changes 28-Aug-2006 1 Initial release. 22-Sep-2006 2 Added Figure 6 Placement and layout recommendations. ESDLIN1524BJ Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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