STS1HNK60 N-CHANNEL 600V - 8Ω - 0.3A SO-8 SuperMESH™Power MOSFET TYPE STS1HNK60 ■ ■ ■ ■ ■ VDSS RDS(on) ID Pw 600 V < 8.5 Ω 0.3 A 2W TYPICAL RDS(on) = 8 Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED GATE CHARGE MINIMIZED NEW HIGH VOLTAGE BENCHMARK SO-8 DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS SWITCH MODE LOW POWER SUPPLIES (SMPS) ■ LOW POWER, LOW COST CFL (COMPACT FLUORESCENT LAMPS) ■ LOW POWER BATTERY CHARGERS ■ ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STS1HNK60 S1HNK60 SO-8 TAPE & REEL August 2003 1/8 STS1HNK60 ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit Drain-source Voltage (VGS = 0) 600 V Drain-gate Voltage (RGS = 20 kΩ) 600 V Gate- source Voltage ± 30 V ID Drain Current (continuous) at TC = 25°C 0.3 A ID Drain Current (continuous) at TC = 100°C 0.19 A Drain Current (pulsed) 1.2 A IDM () PTOT Total Dissipation at TC = 25°C Derating Factor dv/dt (1) Tj Tstg 2 W 0.016 W/°C 3 V/ns -65 to 150 °C 62.5 °C/W Peak Diode Recovery voltage slope Operating Junction Temperature Storage Temperature ( ) Pulse width limited by safe operating area (1) ISD ≤0.3A, di/dt ≤100A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. THERMAL DATA Rthj-amb Thermal Resistance Junction-ambient Max ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol 2/8 Parameter Test Conditions Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 30 V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V, ID = 0.5 A V(BR)DSS Min. Typ. Max. 600 2.25 Unit V 1 50 µA µA ±100 nA 3 3.7 V 8 8.5 Ω STS1HNK60 ELECTRICAL CHARACTERISTICS (CONTINUED) DYNAMIC Symbol gfs (1) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. VDS > ID(on) x RDS(on)max, ID = 0.5 A VDS = 25V, f = 1 MHz, VGS = 0 Typ. Max. Unit 1 S 156 23.5 3.8 pF pF pF SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 300 V, ID = 0.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 6.5 5 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 480 V, ID = 1 A, VGS = 10V, RG = 4.7Ω 7 1.1 3.4 10 nC nC nC Typ. Max. Unit SWITCHING OFF Symbol Parameter Test Conditions Min. td(off) tf Turn-off Delay Time Fall Time VDD = 300 V, ID = 0.5 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 19 25 ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time VDD = 480V, ID = 1.0 A, RG = 4.7Ω, VGS = 10V (Inductive Load see, Figure 5) 24 25 44 ns ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) trr Qrr IRRM Test Conditions Forward On Voltage ISD = 0.3 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 0.3 A, di/dt = 100 A/µs VDD = 25 V, Tj = 150°C (see test circuit, Figure 5) Min. Typ. Max. Unit 0.3 1.2 A A 1.6 229 377 3.3 V ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3/8 STS1HNK60 Safe Operating Area Thermal Impedance Output Characteristics Transfer Characteristics Transconductance 4/8 Static Drain-source On Resistance STS1HNK60 Gate Charge vs Gate-source Voltage Normalized Gate Threshold Voltage vs Temp. Source-drain Diode Forward Characteristics Capacitance Variations Normalized On Resistance vs Temperature Normalized BVDSS vs Temperature 5/8 STS1HNK60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STS1HNK60 SO-8 MECHANICAL DATA mm DIM. MIN. TYP. A a1 MIN. TYP. 1.75 0.1 0.003 0.009 1.65 0.65 MAX. 0.068 0.25 a2 a3 inch MAX. 0.064 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 0.244 c1 45 (typ.) e 1.27 0.050 e3 3.81 0.150 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8 (max.) 0016023 7/8 STS1HNK60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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