STP30NS15LFP N-CHANNEL 150V - 0.085 Ω - 10A TO-220FP MESH OVERLAY™ POWER MOSFET TYPE STP30NS15LFP ■ ■ ■ VDSS RDS(on) ID 150 V <0.1Ω 10 A TYPICAL RDS(on) = 0.085Ω EXTREMELY HIGH dv/dt CAPABILITY 100% AVALANCHE TESTED DESCRIPTION Using the latest high voltage MESH OVERLAY™ process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding performances. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. 3 1 2 TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SWITCHING “S” CAPACITOR ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Drain-source Voltage (VGS = 0) Unit 150 V Drain-gate Voltage (RGS = 20 kΩ) 150 V Gate- source Voltage ± 15 V ID Drain Current (continuous) at TC = 25°C 10 A ID Drain Current (continuous) at TC = 100°C 7 A IDM(•) Ptot EAS(1) dv/dt (2) Tstg Tj Drain Current (pulsed) 40 A Total Dissipation at TC = 25°C 30 W Derating Factor 0.2 W/°C Single Pulse Avalanche Energy 300 mJ Peak Diode Recovery voltage slope 2.4 V/ns -55 to 175 °C Storage Temperature Operating Junction Temperature (•) Pulse width limited by safe operating area. July 2003 . Value (1) Starting T j = 25 oC, ID = 15A, VDD= 75V (2) ISD ≤35A, di/dt ≤300A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX. 1/9 STP30NS15LFP THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max Typ 5 62.5 300 °C/W °C/W °C ELECTRICAL CHARACTERISTICS (Tcase = 25 °C unless otherwise specified) OFF Symbol Parameter Test Conditions V(BR)DSS Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 15V Min. Typ. Max. 150 Unit V 1 10 µA µA ±100 nA ON (1) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 5 V ID = 250 µA Min. Typ. Max. Unit 1 2 3 V 0.085 0.1 0.1 0.112 Ω Ω Typ. Max. Unit ID = 5 A ID = 5 A DYNAMIC Symbol 2/9 Parameter Test Conditions gfs (*) Forward Transconductance VDS = 20 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 ID = 7 A Min. 6 S 1080 170 105 pF pF pF STP30NS15LFP ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time ID = 5 A VDD = 75 V RG = 4.7 Ω VGS = 4.5 V (Resistive Load, Figure 1) 25 95 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=120V ID=10A VGS=5V (see test circuit, Figure 2) 40 7.5 20 54 nC nC nC Typ. Max. Unit ns ns SWITCHING OFF Symbol Parameter Test Conditions Min. td(off) tf Turn-off Delay Time Fall Time ID = 5 A VDD = 75 V RG = 4.7Ω, VGS = 5 V (Resistive Load, Figure 1) 55 30 ns ns tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time ID = 10 A Vclamp = 120 V RG = 4.7Ω, VGS = 4.5 V (Inductive Load, Figure 3) 15 30 50 ns ns ns SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 10 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100A/µs ISD = 10 A Vr = 30 V Tj = 150°C (Inductive Load, Figure 3) trr Qrr IRRM Test Conditions Min. Typ. VGS = 0 160 950 12 Max. Unit 10 40 A A 1.3 V ns nC A (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (•)Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/9 STP30NS15LFP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STP30NS15LFP Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature . . 5/9 STP30NS15LFP Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 3: Test Circuit For Diode Recovery Behaviour 6/9 Fig. 2: Gate Charge test Circuit STP30NS15LFP TO-220FP MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L3 L3 L6 F2 H G G1 ¯ F F1 L7 1 2 3 L2 L4 7/9 STP30NS15LFP TO-220FP(023Y) MECHANICAL DATA DIM. A B C D E F F1 F2 G G1 H L1 L2 L3 L4 L5 L6 L7 L8 M N Dia 8/9 MIN. 4.4 2.5 1 2.4 0.4 0.75 1.15 1.15 4.68 2.24 10 18.4 mm. TYP MAX. 4.6 2.7 1.4 2.75 0.7 1 1.7 1.7 5.48 2.84 10.4 19.2 MIN. 0.173 0.009 0.039 0.094 0.015 0.029 0.045 0.045 0.184 0.088 0.393 0.724 16 29 15.3 MAX. 0.181 0.106 0.055 0.108 0.027 0.039 0.066 0.066 0.215 0.111 0.409 0.755 0.629 30 16.1 1.14 0.60 16.4 9.3 23.6 5.4 3.29 3.2 0.625 0.354 0.885 0.181 0.090 3.4 15.9 9 22.5 4.6 2.29 3 inch TYP. 1.18 0.63 0.133 0.665 0.366 0.929 0.212 0.129 STP30NS15LFP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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