STMICROELECTRONICS SPDC12L00010

SPDC12L00010
10 A DC/DC converter module
Preliminary Data
Features
■
MTBF 1 000 000 (TA = 25 °C)
■
10 A max output current
■
Input voltage range from 1.8 V to 14 V
■
Supply voltage range from 4.5 V to 14 V
■
Fixed or adjustable output voltage
down to 0.6 V
■
Fixed frequency voltage mode control
■
Adjustable switching frequency
■
Soft-start and inhibit
■
Selectable UVLO threshold (5 V or 12 V bus)
■
Master/slave synchronization with 180° phase
shift
■
Pre-bias start-up capability
■
Selectable source/sink or source only
capability after soft-start
■
Power Good output with programmable delay
■
Over voltage protection with selectable
latched/not-latched mode
■
■
Applications
■
Laptop
■
Blade servers
■
RAID systems
■
Network routers
■
Cellular base stations
■
Industrial equipment
■
Test instrumentation
Thermal shut-down
■
Medical diagnostic equipment
Operating temperature range -40 °C ÷ 85 °C
■
Points of load regulation
Table 1.
Device summary
Order code
SPDC12L00010
October 2008
Output voltage
Input voltage
Output ripple
Efficiency
[V]
[V]
[mVpp]
[%]
0.6 ÷ 5
1.8 ÷ 14
40
70 ÷ 93
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Notes
Progr. output
voltage
1/24
www.st.com
24
Contents
SPDC12L00010
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
2.1
Pin connection and mechanical data (dimensions in mm) . . . . . . . . . . . . . 5
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3
Thermal de-rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/24
5.1
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Auxiliary voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5
Multiple units synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.6
Power good signal and power good delay . . . . . . . . . . . . . . . . . . . . . . . . 14
5.7
Oscillator setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.8
Current sink-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.9
Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.10
Program setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.11
Voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.12
Output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.13
Additional loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.14
Output over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.15
Current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.16
Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.17
Signal ground and power ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.18
Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPDC12L00010
6
7
Contents
5.19
Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.20
Phase connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
PCB footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
Description
1
SPDC12L00010
Description
The ST SPDC12L00010 high density 10 A DC-DC converter is a complete step-down power
supply. A single LGA package includes ST switching controller, power FETs, inductor and all
the support components. SPDC12L00010 operates over a wide input voltage range of 1.8 V
to 14 V, supporting an output range of 0.6 V to 5 V. High level of integration and synchronous
rectification allows the SPDC12l00010 to deliver up to 10 A continuous current at up to 93%
efficiency, without external heat sink or airflow.
The device is a complete stand alone surface mount power supply, that can be handled and
assembled like a standard integrated circuit. Moreover its low profile design permits the
SPDC12L00010 to be soldered onto the back side of a printed circuit board, freeing up
valuable board space.
SPDC12L00010 is self protected against over voltage and short circuit conditions. A built in
adjustable soft-start and inhibit guarantee correct functionality whatever the load is. Pre-bias
start up capability is in place as well Power Good output with programmable delay to avoid
false signals.
The device is packaged in a thermally enhanced, compact (15 x 15 mm) and low profile (3
mm) over molded land grid array (LGA) package, suitable for automated assembly by
standard surface mount equipment. The SPDC12L00010 is Pb-Free and RoHS compliant.
4/24
SPDC12L00010
Pin settings
2
Pin settings
2.1
Pin connection and mechanical data (dimensions in mm)
Figure 1.
Pin connection
AM00542v1
2.2
Pin description
Table 2.
Pin description
Name Function
Description
VAUX
Auxiliary voltage.
Internally regulated 5 V voltage. It is used to supply the internal drivers and the
voltage reference.
K11
OS
Oscillator set.
Connecting a resistor from this pin to SGND or to VAUX, the switching frequency
can be increased or decreased.
In OVP status the pin is pulled to 4.5 V (latched mode only).
L2
VSENSE
L3
VCC
J11
Voltage sense.
Using this pin it is possible to recover the voltage drop on Vout track.
VCC.
Controller voltage supply pin. The operative voltage range for the internal
controller is 4.5 V to 14 V
5/24
Pin settings
SPDC12L00010
Table 2.
Pin description (continued)
Name Function
L4
Power Good.
This pin is an open collector output, with a 10 kΩ pull-up resistor connected to
VAUX.
It is pulled low if the output voltage is not within specified thresholds
(90%-110%).
L5
PGDLY
Power Good delay.
A capacitor connected between this pin and SGND, introduce a delay between
the internal PG comparator and the external signal rising edge. No delay can be
introduced on the falling edge of PG signal.
L6
SYNC
Synchronization.
This is the master/slave pin. Two or more devices can be synchronized
connecting the SYNC pins together.
Program.
This pin allows following settings:
- Enable/disable the current sink mode capability after soft-start;
- Enable/disable the OVP latch mode;
- Setting UVLO threshold for 5 V or 12 V bus.
L7
PRG
L8
SGND
L9
FB
L10
COMP
Compensation.
This pin is connected to the error amplifier output.
L11
SS_INL
Soft-start_inhibit low
The soft-start time is programmed connecting an external capacitor from this pin
to SGND;
This pin can be used to inhibit the module.
Bank 1
VIN
Bank 2
PGND
Return for input/output voltage source.
Bank 3
VOUT
Regulated power output.
See Section 5.19 on page 18 for mandatory condition.
Bank 4
6/24
PG
Description
PH
Signal ground.
All references are referred to these pins, internally connected to PGND.
Feed-back.
This pin is connected to the error amplifier inverting input.
DC input voltage.
See Section 5.18 on page 18 for mandatory condition.
Phase
This pins area is foreseen for module power losses dissipation;
see Section 5.20 on page 19 for details.
SPDC12L00010
Maximum ratings
3
Maximum ratings
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
VK11
OS to SGND and PGND
-0.3 to 6
V
VL2
VSENSE to SGND and PGND
-0.3 to 18
V
VL3
VCC to SGND and PGND
-0.3 to 18
V
VL4
PG to SGND and PGND
-0.3 to 18
V
VL5
PGDLY to SGND and PGND
-0.3 to 6
V
VL6
SYNC to SGND and PGND
-0.3 to 6
V
VL7
PRG to SGND and PGND
-0.3 to 6
V
VL9
FB to SGND and PGND
-0.3 to 6
V
VL10
COMP to SGNG and PGND
-0.3 to 6
V
VL11
SS_INL to SGND and PGND
-0.3 to 6
V
Vi
VIN to SGND and PGND
-0.3 to 18
V
Vo
VOUT to SGND and PGND
-0.3 to 18
V
Io
Maximum output current
Int. limited
A
Value
Unit
Thermal data
Table 4.
Symbol
Table 3. Thermal data
Parameter
TSTG
Storage temperature range
-40 ÷ 105
°C
TOP
Operating temperature range
-40 ÷ 85
°C
7/24
Maximum ratings
3.3
SPDC12L00010
Thermal de-rating
The thermal de-rating is obtained reducing the maximum output current, to limit the module
temperature to the maximum allowable value.
Since a lot of parameters affect the module power dissipation, the best way to get a precise
thermal de-rating is to measure the module temperature in the final application condition.
For this purpose, the case top side must be monitored at the central point T1 (see Figure 2);
the maximum temperature allowable value at T1 is 125 °C.
Figure 2.
Measurement points for thermal de-rating (top side)
AM00543v1
All data reported in the following tables are valid for free air condition and module placed on
25 cm2, 4 layers, 1.6 mm FR4 printed circuit board.
Table 5.
Symbol
Io
Io
Io
8/24
Thermal de-rating for Vout = 5.0 V
Parameter
Output current
Output current
Output current
Test condition
Value
VIN = 8 V TA = 75 °C
TBD
VIN = 8 V TA = 80 °C
TBD
VIN = 8 V TA = 85 °C
TBD
VIN = 10 V TA = 70 °C
TBD
VIN = 10 V TA = 75 °C
TBD
VIN = 10 V TA = 80 °C
TBD
VIN = 10 V TA = 85 °C
TBD
VIN = 12 V TA = 60 °C
TBD
VIN = 12 V TA = 65 °C
TBD
VIN = 12 V TA = 70 °C
TBD
VIN = 12 V TA = 75 °C
TBD
VIN = 12 V TA = 80 °C
TBD
VIN = 12 V TA = 85 °C
TBD
Unit
A
A
A
SPDC12L00010
Maximum ratings
Table 5.
Symbol
Io
Table 6.
Thermal de-rating for Vout = 5.0 V (continued)
Parameter
Output current
Parameter
Io
Output current
Io
Io
Value
VIN = 14 V TA = 50 °C
TBD
VIN = 14 V TA = 55 °C
TBD
VIN = 14 V TA = 60 °C
TBD
VIN = 14 V TA = 65 °C
TBD
VIN = 14 V TA = 70 °C
TBD
VIN = 14 V TA = 75 °C
TBD
VIN = 14 V TA = 80 °C
TBD
VIN = 14 V TA = 85 °C
TBD
Unit
A
Thermal de-rating for Vout = 3.3 V
Symbol
Io
Test condition
Output current
Output current
Output current
Test condition
Value
VIN = 8 V TA = 80 °C
TBD
VIN = 8 V TA = 85 °C
TBD
VIN = 10 V TA = 75 °C
TBD
VIN = 10 V TA = 80 °C
TBD
VIN = 10 V TA = 85 °C
TBD
VIN = 12 V TA = 70 °C
TBD
VIN = 12 V TA = 75 °C
TBD
VIN = 12 V TA = 80 °C
TBD
VIN = 12 V TA = 85 °C
TBD
VIN = 14 V TA = 65 °C
TBD
VIN = 14 V TA = 70 °C
TBD
VIN = 14 V TA = 75 °C
TBD
VIN = 14 V TA = 80 °C
TBD
VIN = 14 V TA = 85 °C
TBD
Unit
A
A
A
A
9/24
Maximum ratings
Table 7.
Thermal de-rating for Vout = 2.5 V
Symbol
Parameter
Io
Output current
Io
Io
Table 8.
Output current
Output current
Test condition
Value
VIN = 10 V TA = 80 °C
TBD
VIN = 10 V TA = 85 °C
TBD
VIN = 12 V TA = 75 °C
TBD
VIN = 12 V TA = 80 °C
TBD
VIN = 12 V TA = 85 °C
TBD
VIN = 14 V TA = 70 °C
TBD
VIN = 14 V TA = 75 °C
TBD
VIN = 14 V TA = 80 °C
TBD
VIN = 14 V TA = 85 °C
TBD
Unit
A
A
A
Thermal de-rating for Vout = 1.8 V
Symbol
Parameter
Io
Output current
Io
Output current
Io
Output current
Table 9.
10/24
SPDC12L00010
Test condition
Value
VIN = 10 V TA = 80 °C
TBD
VIN = 10 V TA = 85 °C
TBD
VIN = 12 V TA = 80 °C
TBD
VIN = 12 V TA = 85 °C
TBD
VIN = 14 V TA = 80 °C
TBD
VIN = 14 V TA = 85 °C
TBD
Unit
A
A
A
Thermal de-rating for Vout = 1.2 V
Symbol
Parameter
Io
Output current
Test condition
Value
VIN = 14 V TA = 80 °C
TBD
VIN = 14 V TA = 85 °C
TBD
Unit
A
SPDC12L00010
Electrical characteristics
4
Electrical characteristics
Table 10.
Electrical characteristics
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
Vr
Ripple voltage
VIN = 12 V, Io = 10 A,
Co = 2x330 μF
BW = 20 MHz
Io
Output current
VIN = 1.8 ÷ 14 V
Iol
Current limit
VIN = 1.8 ÷ 14 V
12
A
Iq
Total quiescent current
VCC = 12 V, Io = 0 A
65
mA
Iqst-by
Total stand-by quiescent current
VSS_INL < 0.5 V
5
mA
ICCq
VCC quiescent current
VCC = 12 V, Io = 0 A,
OS = open, VSS_INL > 0.5 V
35
mA
ICCqst-by VCC stand-by quiescent current
VCC = 12 V, Io = 0 A,
OS = open, VSS_INL < 0.5 V
5
mA
fs
Switching frequency
VCC = 12 V, Io = 10 A,
TA = 0 ÷ 85 °C
VFB
Feedback voltage
(Reference voltage)
TA = -40 ÷ 85 °C
VAUX
Auxiliary voltage
VCC = 5.5 ÷ 14 V,
IAUX = 1 ÷ 100 mA
VSS_INL Inhibit threshold
ISS_INL
Soft-start current
40
0
mVpp
10
A
678
729
780
kHz
0.593
0.6
0.605
V
4.5
5
5.5
V
0.5
V
Device OFF
VSS_INL = 2 V
7
10
13
VSS_INL = 0 ÷ 0.5 V
20
30
45
Power Good voltage low
IPG = -5 mA
VPGhth
Power Good high threshold (VFB/0.6)
VFB rising
108
110
112
%
VPGlth
Power Good low threshold (VFB/0.6)
VFB falling
88
90
92
%
VOVhth
Overvoltage high threshold (VFB/0.6)
VFB rising
120
%
VOVlth
Overvoltage low threshold (VFB/0.6)
VFB falling
117
%
VPG
VCConth
VCC turn-on threshold
VCCoffth
VCC turn-off threshold
0.5
μA
V
5 V BUS, VIN > 1.7 V
4.0
4.2
4.4
12 V BUS, VIN > 1.7 V
8.3
8.6
8.9
5 V BUS, VIN > 1.7 V
3.6
3.8
4.0
12 V BUS, VIN > 1.7 V
7.4
7.7
8.0
V
V
VINhth
VIN high threshold
VIN rising
1.1
1.25
1.47
V
VINlth
VIN low threshold
VIN falling
0.9
1.05
1.27
V
11/24
Application information
5
Application information
5.1
Input voltage
SPDC12L00010
There are two voltage supply pins:
VCC (pin L3), for controller voltage supply;
VIN (bank 1), for power circuit voltage supply.
VCC and VIN can be connected and supplied together;
if VIN is lower than 4.5 V, VCC must be supplied separately.
The recommended maximum operating DC input voltage is 14 V.
5.2
Auxiliary voltage
VAUX (pin J11) pin must be used to supply PRG and OS setting resistors.
No capacitor is required.
5.3
Inhibit function
SS_INL (pin L11) allows putting the device in stand-by mode.
With SS_INL lower than 0.5 V, the device is disabled and the current consumption is
reduced to 5 mA, for VIN = 12 V.
With SS_INL higher than 0.5 V the device is enabled.
Since SS_INL has soft-start function, it is mandatory to implement the inhibit function using
an open collector device (i.e. small signal transistor), to not influence the module behavior
(see Figure 3).
Figure 3.
Inhibit function
AM00544v1
12/24
SPDC12L00010
5.4
Application information
Soft-start
The soft-start phase begins when both VCC and VIN raise above their turn-on thresholds,
otherwise the SS_INL pin is internally shorted to SGND.
A ramp is generated at SS_INL pin during start-up, charging the external capacitor CSS with
an internal current generator.
The initial value for this current is 30 μA and it charges the capacitor up to 0.5 V, after that, it
is reduced to 10 μA until the final charge value approximately 4 V.
In the meanwhile, the controller internal voltage reference raises to its final value, following
the SS_INL pin voltage slope.
During soft-start, the module provides a constant current protection, limiting the output
current at the maximum value, without entering in HICCUP mode.
If there is not current limitation, the output voltage slope follows the SS_INL pin slope.
The output voltage rise time, can be set choosing proper CSS value.
The soft-start phase ends when the SS_INL pin voltage reaches 3.5 V.
A capacitor CSS = 3 3 nF is present on the module, to perform a minimum soft-start time,
suitable for Co = 10000 μF max. output capacitor;
in this condition and with 10 A output current resistor load, the output voltage rise time is
around 5ms, but the complete soft-start time is around 10ms.
Using the minimum output capacitor Co = 660 μF and with 10 A resistor load, the output
voltage rise time is around 2 ms.
5.5
Multiple units synchronization
Using more than one unit on the same circuit, it is possible to synchronize the switching
frequency oscillators, connecting all SYNC (pin L6) together.
The device with the higher switching frequency will be the Master, while the other will be the
Slaves.
The best way to synchronize two or more devices is to set same switching frequency, in any
case, the switching frequencies can differ for a maximum of 50% of the lowest one.
Using and external clock signal, to synchronize one or more devices working at a different
switching frequency, it is recommended to follow the below formula:
fsw ≤ fext ≤ 1.3fsw
The phase shift between master and slaves is approximately 180°.
13/24
Application information
5.6
SPDC12L00010
Power Good signal and Power Good delay
The output voltage is monitored by FB (pin L9), if it is not within ± 10% (typ.) of the
programmed value, the PG (pin L4) output is forced low.
The PG signal can be delayed by adding an external capacitor on PGDLY (pin L5), the delay
can be calculated with the following formula:
PGdelay = 0.5 x CPGDLY(pF) [μs]
5.7
Oscillator setting
The switching frequency is internally fixed to 729 kHz, this value can be slightly varied using
an external resistor ROS connected between OS (pin K11) and SGND (L8) or VAUX (pin
J11).
Since the OS pin is maintained at fixed voltage (typ. 1.2), the frequency is
increased/decreased proportionally to the current sunk/sourced from/into the pin.
In particular, connecting ROS to SGND the frequency is increased according the following
formula:
fSW = 729 + (9.88x106/ROS) [kHz]
Connecting ROS to VAUX the frequency is reduced according to the following formula:
fSW = 729 - (30.1x106/ROS) [kHz]
5.8
Current sink-mode
Connecting a proper resistor (see par. Section 5.10 on page 15) from PRG (pin L7) to VAUX
(pin J11), it is possible to select the sink-mode operation, that means to allow the output
current to reverse its polarity into the converter output inductor.
If the sink-mode is enabled, the converter can sink current from the load after soft-start;
If the sink-mode is disabled, the converter never sinks current.
Note:
14/24
When output low current operation is required (Iout < 2 A), sink-mode operation is
recommended, this condition improves output voltage transient response and reduces
output voltage ripple.
SPDC12L00010
5.9
Application information
Under voltage lock out
Connecting a proper resistor (see par. Section 5.10) from PRG (pin L7) to VAUX (pin J11), it
is possible to select two different thresholds for UVLO:
4.2 V/3.8 V for 5 V input range;
8.6 V/7.7 V for 12 V input range.
5.10
Program setting
Connecting a resistor from PRG (pin L7) to VAUX (pin J11), it is possible to select different
operation modes, according to the following table:
Table 11.
Program setting
RPRG
UVLO.
OVP
Sink-mode
Not latched
Not
Not latched
Yes
6.2 kΩ
Latched
Not
4.3 kΩ
Latched
Yes
2.7 kΩ
Not latched
Not
Not latched
Yes
1.2 kΩ
Latched
Not
0Ω
Latched
Yes
n.c.
11 kΩ
5 V range
1.8 kΩ
12 V range
5.11
Voltage sensing
Using VSENSE (pin L2) it is possible to recover the voltage drop on VOUT PCB track.
Connect VSENSE in a point closed to the load (see Figure 4).
Using VSENSE connection, it will not recover the voltage drop on PGND PCB track.
Leaving VSENSE floating, the output voltage will be sensed at VOUT (bank 3).
Figure 4.
Voltage sensing
15/24
Application information
5.12
SPDC12L00010
Output voltage programming
Adding a resistor Rx between FB (pin L9) and SGND (L8) or between FB and VSENSE (pin
L2), it is possible to change the output voltage.
Connecting the resistor to SGND the output voltage increase (see Figure 5 a);
Connecting the resistor to VSENSE the output voltage decrease (see Figure 5 b).
Calculate the resistor for increasing output voltage with the following formula:
Rx = 0.6 / (VOUT – 1.2)
[kΩ] valid for VOUT > 1.2 V
Calculate the resistor for decreasing output voltage with the following formula:
Rx = (VOUT – 0.6) / (1.2 – VOUT) [kΩ] valid for 0.6 < VOUT < 1.2 V
The module output voltage is 1.2 V with Rx = n.c.
Figure 5.
5.13
Output voltage programming
Additional loop compensation
If required by particular load condition, it is possible to change the feedback loop
compensation, adding a pole with an external R-C network between FB (pin L9) and COMP
(pin L10) (see Figure 6 a), or adding a zero with an external R-C network between FB and
VSENSE (pin L2) (see Figure 6 b).
Figure 6.
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Additional loop compensation
SPDC12L00010
5.14
Application information
Output over voltage protection
The device provides OVP:
when the voltage sensed on FB (pin L9) reaches a value greater than 20% of reference, the
on module low side driver is turned ON and the converter stop switching operation.
If the OVP not latched mode has been set, the on module low side MOSFET is kept ON, as
long as the over voltage condition is detected.
If OVP latched mode has been set, the low side MOSFET is turned ON and the OS (pin
K11) is forced high (4.5 V typ.), until VCC is toggled.
It must be taken in account that there is an electrical network between the output terminal
and FB, therefore the voltage at this pin is not a perfect replica of output voltage.
If the converter is set to sink current, the low side MOSFET could be turned ON before the
output voltage exceeds the over voltage threshold (109% typ.), because the error amplifier
will change its balance in advance.
If the sink-mode is disabled, the low side MOSFET will be turned ON only when the OVP
operate, in this case a delay between the output voltage rising and the FB rising can appear
and the OVP can operate late (126% typ.).
5.15
Current limitation
The device realizes the over current protection sensing the current on board high side
MOSFET and on board low side MOSFET, therefore two current limits are set:
peak current limit and valley current limit.
The peak current protection is active when the high side MOSFET is turned ON, the valley
current protection is enabled when the low side MOSFET is turned ON.
After soft-start is completed, if an over current occurs, the device enters in HICCUP mode:
both high side and low MOSFETs are turned OFF;
the soft-start capacitor is discharged with a 10 μA constant current;
when the voltage on SS_INL (pin L11) reaches 0.5 V the soft-start phase restart.
During the soft-start phase the OCP provides a constant current protection.
5.16
Thermal shutdown
When the controller junction temperature reaches 150 ± 10 °C, the device shutdown.
Both MOSFET are turned OFF and the soft-start capacitor is discharged.
The device does not restart until the junction temperature goes down to 120 °C and until the
voltage on the soft-start capacitor reaches 0.5 V.
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Application information
5.17
SPDC12L00010
Signal ground and power ground
SGND (L8) and PGND (bank 2) are connected together on the module.
Connect to SGND the capacitor for PGDLY and SS_INL, the resistor for FB and OS.
Connect to PGND the return for SS_INL.
It is important to not create a ground loop between SGND, PGND and other GND present on
the application circuit (see Figure 7).
Figure 7.
5.18
Signal ground and power ground
Input capacitors
The input capacitor present on the module is not able to sustain the input RMS current.
Connect 2 x 2.2 μF 16 V X7R ceramic capacitor (Cin) closed to the input pins VIN and
PGND (bank 1 and bank 2), to satisfy minimum functional requirement.
Connect proper low impedance capacitors to reduce the input ripple current, according to
the application requirement.
5.19
Output capacitors
The output capacitors present on the module are able to sustain output RMS current.
Connect 2 x 330 μF POSCAP SANYO capacitor (Co) or equivalent, closed to the output pins
VOUT and PGND (bank 3 and bank 2), to guarantee output voltage stability and specified
voltage ripple.
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SPDC12L00010
5.20
Application information
Phase connection
On the module bottom, there is an area relative to PH (bank 4) connection:
this area is internally connected to the high side MOSFET source and to the low side
MOSFET drain;
this electrical point is used to dissipate heat generated by the two MOSFETs.
Connect PH (bank 4), to an insulated copper area on the mother board, to ensure proper
heat sink.
Since the PH signal contains very fast voltage transients, it is recommended to take in
account possible inducted noise on mother board, i.e.: it is advised against to lead under the
module printed circuit board tracks with susceptible signals.
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Package mechanical data
6
SPDC12L00010
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Figure 8.
Package mechanical data
AM00542v1
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SPDC12L00010
6.1
Package mechanical data
Soldering
Soldering phase has to be execute with care: in order to avoid undesired melting
phenomenon, particular attention has to be take on the set up of the peak temperature.
Here following some suggestions for the temperature profile based on
IPC/JEDEC J-STD-020C, July 2004 recommendations.
Table 12.
Soldering
Profile feature
Average ramp up rate (TSMAX to TP)
PB free assembly
3 °C / sec max
Preheat
Temperature min (TS min)
Temperature max (TS max)
Time (tS min to tS max) (tS)
150 °C
200 °C
60 – 100 sec
Time maintained above:
Temperature TL
Time tL
217 °C
40 – 70 sec
Peak temperature (Tp)
240 + 0 °C
Time within 5 °C of actual peak temperature (tP)
10 – 20 sec
Ramp down rate
Time from 25 °C to peak temperature
Figure 9.
6 °C / sec
8 minutes max
Soldering
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Package mechanical data
6.2
PCB footprint
Use Figure 10 as suggested PCB footprint.
Figure 10. PCB footprint for SPDC12L00010 (dimensions in mm)
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SPDC12L00010
SPDC12L00010
7
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
17-Oct-2008
1
Changes
First release
23/24
SPDC12L00010
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