STMICROELECTRONICS ST72681/R21

ST72681
USB 2.0 high-speed Flash drive controller
Features
■
USB 2.0 interface compatible with mass
storage device class
– Integrated USB 2.0 PHYSupports USB
high speed and full speed
– Suspend and Resume operations
TQFP48 7x7
■
Clock management
– Integrated PLL for generating core and
USB 2.0 clock sources using an external
12 MHz crystal oscillator
■
Data protection
– Write protect switch control
– Public/private partitions support
■
Production tool device configurability:
– USB vendor ID/product ID (VID/PID), serial
number and USB strings with foreign
language support
– SCSI strings
– One or two LED outputs
– Adjustable NAND Flash bus frequency to
reach highest performance
■
Code update in the NAND Flash memory
USB 2.0 low-power device compliant
– Less than 100 mA during write operation
with two NAND Flash devices
– Less than 500 µA in suspend mode
■
TQFP48 7x7 ECOPACK® package
■
Development support
– Complete reference design including
schematics, BOM and gerber files
■
AutoRun CDROM partition support
■
■
Bootability support (HDD mode)
Supports Windows (Vista, XP, 2000, ME),
Linux and MacOS. Drivers available for
Windows 98 SE
■
Mass storage controller interface (MSCI)
– Supports all types of NAND Flash devices
including ST, Hynix, Samsung, Toshiba,
Micron, Renesas
– Reed-Solomon encoder/decoder on-the-fly
correction (4 bytes of a 512-byte block)
– Flash identification support
– Up to 12 MB/s for read and 8 MB/s for write
operations in single channel
– Up to 4 NAND devices supported in a
single channel
■
Embedded ST7 8-bit MCU
■
Supply management
– 3.3 V operation
– Integrated 3.3-1.8 V voltage regulator
■
Table 1.
Device summary
Orderable part numbers
Features
ST72681/R20
USB interface
Number of NAND devices supported
R/W speed
ST72681/R21
USB 2.0 high speed
(1)
up to 1
up to 4
11MB/s and 7MB/s
12MB/s and 8MB/s
Operating voltage
3.0 to 3.6 V
Operating temperature
0 to +70 °C
Package
TQFP48 7x7 / Die form
1. Number of NAND devices supported in a single channel.
August 2007
Rev 5
1/32
www.st.com
1
Contents
ST72681
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
NAND interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
NAND support table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
NAND error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1
4.2.2
4.3
Management of bad NAND blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1
4.3.2
4.3.3
4.4
5
Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
BOT / SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
5.4
2/32
BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1
5.3.2
5.3.3
5.3.4
7
LUT usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
NAND interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2.1
5.2.2
5.2.3
6
Bad block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Late fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.1
4.5
Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1
LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2
Read only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ST72681
Contents
7.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.2.1
7.2.2
7.2.3
7.3
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8.1
7.9
Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 20
Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 21
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.7.1
7.7.2
7.8
General timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6.1
7.6.2
7.6.3
7.7
RUN and SUSPEND modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply and clock managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5.1
7.5.2
7.6
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.4.1
7.4.2
7.5
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.3.1
7.4
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Other communication interface characteristics . . . . . . . . . . . . . . . . . . . . 26
7.9.1
7.9.2
MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Universal serial bus interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
Introduction
1
ST72681
Introduction
The ST72681 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed
interface including PHY and function supports USB 2.0 mass storage device class.
The mass storage controller interface (MSCI) combined with the Reed-Solomon
encoder/decoder on-the-fly correction (4-byte on 512-byte data blocks) provides a flexible,
high transfer rate solution for interfacing a wide of range NAND Flash memory device types.
The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz
frequency for the USB 2.0 PHY.
The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data
and patch code are stored in internal RAM.
I/O ports provide functions for EEPROM connection, LEDs and write protect switch control.
The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital
part of the circuit.
Figure 1.
Device block diagram
12 MHz
OSC
8-bit
CPU
USB 2.0 USB 2.0
Function
PHY
3.3 V to 1.8 V
voltage
regulator
4/32
ROM
RAM
Mass
Storage
Controller
Interface
ReedSolomon
Error
Correction
GPIO
NAND
I/F
ST72681
Pin description
Figure 2 shows the TQFP48 package pinout, while Table 2, Table 3, Table 4, and Table 5
give the pin description.
The legend and abbreviations used in these tables are the following:
●
Type
–
I = input
–
O = output
–
S = supply
●
Input level: A = Dedicated analog input
●
In/Output level
●
–
CT = CMOS 0.3VDD/0.7VDD with input trigger
–
TT= TTL 0.8V / 2V with Schmitt trigger
Output level
–
D8 = 8mA drive
–
D4 = 4mA drive
–
D2 = 2mA drive
48-pin TQFP package pinout
VSS_1
VDD33_1
NC(1)
NAND D[0]
NAND D[1]
NAND D[2]
NAND D[3]
NAND D[4]
NAND D[5]
NAND D[6]
NAND D[7]
NAND RnB
Figure 2.
VDDA
OSCIN
OSCOUT
VSSA
RREF
VSSC
VDDC
VDD3
USBDP
USBDM
VSSBL
VDDBL
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
ST72681
NAND WP
READ ONLY
EEPROM SCL
VSS_2
VDD33_2
NC(1)
NC(1)
RESET
LED2
LED1
NAND ALE/EEPROM SDA
VSS_3
VDDOUSB
VSS_4
VDD33_4
NAND CE4
NAND CE3
NAND CE2
NAND CE1
NAND RE
NAND WE
NAND CLE
NC(1)
VDD33_3
2
Pin description
1. Must remain NOT connected in the application.
5/32
Pin description
Pin
Pin name
48
VSS_1
S
Ground
47
VDD33_1
S
I/Os and regulator supply voltage
33
VSS_2
S
Ground
32
VDD33_2
S
I/Os and regulator supply voltage
25
VSS_3
S
Ground
24
VDD33_3
S
I/Os and regulator supply voltage
14
VSS_4
S
Ground
15
VDD33_4
S
I/Os and regulator supply voltage
13
VDDOUSB
S
USB2 PHY, OSC and PLL power supply output (1.8 V)
Description
USB 2.0 interface
Pin
Pin name
Type
Table 3.
12
VDDBL
S
Supply voltage for buffers and deserialization flip flops (1.8 V)
11
VSSBL
S
Ground for buffers and deserialization flip flops (1.8 V)
10
USBDM
I/O USB2 DATA -
9
USBDP
I/O USB2 DATA +
8
VDD3
S
Supply voltage for the FS compliance (3.3 V)
7
VDDC
S
Supply voltage for DLL & XOR tree (1.8 V)
6
VSSC
S
Ground for DLL & XOR tree (1.8 V)
5
RREF
I/O
Description
Ref. resistor for integrated impedance process adaptation
(11.3 kOhms 1% pull down)
USB 2.0 and core clock system
Pin
Pin name
Type
Table 4.
6/32
Power supply
Type
Table 2.
ST72681
4
VSSA
S
Ground for osc & PLL (1.8 V)
3
OSCOUT
O
12 MHz oscillator output
2
OSCIN
I
12 MHz oscillator input
1
VDDA
S
Supply voltage for osc & PLL (1.8 V)
Description
ST72681
Pin description
Table 5.
General Purpose I/O Ports / Mass Storage I/Os
Pin
Pin name
Type
Input
Outputs
Level
45
NAND D[0]
I/O
TT
D4 NAND Data [0]
44
NAND D[1]
I/O
TT
D4 NAND Data [1]
43
NAND D[2]
I/O
TT
D4 NAND Data [2]
42
NAND D[3]
I/O
TT
D4 NAND Data [3]
41
NAND D[4]
I/O
TT
D4 NAND Data [4]
40
NAND D[5]
I/O
TT
D4 NAND Data [5]
39
NAND D[6]
I/O
TT
D4 NAND Data [6]
38
NAND D[7]
I/O
TT
D4 NAND Data [7]
26
NAND ALE
I/O
TT
D8 NAND Address Latch Enable
22
NAND CLE
O
TT
D8 NAND Command Latch Enable
21
NAND WE
O
TT
D8 NAND WRite Enable
20
NAND RE
O
TT
D8 NAND read enable
19
NAND CE1
O
TT
D4 NAND Chip Enable 1
18
NAND CE2
O
TT
D4 NAND Chip Enable 2
17
NAND CE3
O
TT
D4 NAND Chip Enable 3
16
NAND CE4
O
TT
D4 NAND Chip Enable 4
37
NAND RnB
I
TT
D2 NAND Ready/Busy
36
NAND WP
O
TT
D2 NAND Write Protect
35
READ ONLY
I
TT
D2 Read -only switch (“0”: Read/Write; “1”: Read only)
34
EEPROM SCL
O
TT
D2 EEPROM serial clock
28
LED2
O
TT
D8 Green LED (USB access)
27
LED1
O
TT
D8 Red LED (NAND memory access)
Main function
(after reset)
7/32
Application schematics
3
ST72681
Application schematics
Figure 3.
Application schematic
V33
On BoardFlash1
USB_V5
U1
On BoardFlash2
5
Vout
GND
1
C18
100nF
C20
100nF
C21
100nF
N A N D _RnB
N A N D _RE
N A N D _CE1
N A N D _CE2
NAND_W P
R_Toshiba_config
NAND_RnB2
R7
0
D3
D2
D1
D0
D7
D6
D5
D4
N A N D _CE3
N A N D _CE4
N A N D _CLE
N A N D _A LE
N A N D _W E
N A N D _W P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C19
100nF
U2
NAND_W P
U3
N A N D _FLA SH _TSO P48
V33
GND
N A N D _CE4
2
Vout
N C /#R ES
NC
NC
NC
NC
NC
NC
RB4
I/O 7
RB3
G N D /R B 2
I/O 6
I/O 5
#R /B
I/O 4
#R E
NC
#C E
#C E2
NC
NC
N C /PR E
V CC
V CC
V SS
V SS
NC
#C E3
NC
#C E4
C LE
NC
I/O 3
A LE
I/O 2
#W E
I/O 1
#W P
NC
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
Vin
AM E8800_SOT23
NC
N C /#R ES
NC
NC
NC
NC
RB4
NC
I/O 7
RB3
I/O 6
G N D /R B 2
I/O 5
#R /B
#R E
I/O 4
#C E
NC
NC
#C E2
NC
N C /PR E
V CC
V CC
V SS
V SS
#C E3
NC
#C E4
NC
NC
C LE
I/O 3
A LE
#W E
I/O 2
I/O 1
#W P
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
NC
Decoupling capacitors to be located close to U2,U3, U4 & U5 V33 inputs
UU1
3
V33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
C5
220nF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
C3
10nF
D7
D6
D5
D4
LD3985M33R_SOT235L
N A N D _RnB2
N A N D _RnB
N A N D _RE
INHIBIT BYPASS
V33
N A N D _CLE
N A N D _A LE
N A N D _W E
N A N D _W P
+ C4
4.7uF
4
N A N D _FLA SH _TSO P48
3
Vin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
D3
D2
D1
D0
1
V33
V33
R_Multi_CE_config
R_Single_CE_config
R8
0
NAND_CE2
R9
0
R_Dual_CE_config
NAND_CE3
D [7..0]
R10
Decoupling capacitors to be located close to U1 V33 inputs
0
V33
On BoardFlash3
On BoardFlash4
V33
R3
4.7K
C6
10nF
C7
10nF
C8
10nF
C9
10nF
C10
10nF
V33
V33
D3
D2
D1
D0
D7
D6
D5
D4
D7
D6
D5
D4
C2
100nF
1uF
USB CON
C17
RESET
NAND_W P
100nF
R1
LED2
LED1
V33
220
LED1
R2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N A N D _FLA SH _TSO P48
N C /#R ES
NC
NC
NC
NC
NC
NC
RB4
RB3
I/O 7
G N D /R B 2
I/O 6
#R /B
I/O 5
#R E
I/O 4
#C E
NC
NC
#C E2
NC
N C /PR E
V CC
V CC
V SS
V SS
NC
#C E3
#C E4
NC
NC
C LE
A LE
I/O 3
#W E
I/O 2
#W P
I/O 1
NC
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
N A N D _FLA SH _TSO P48
NAND_W P
V33
GREEN L ED
LED2
V33
220
C14
10nF
C13
10nF
C12
10nF
C11
470nF
V33
V33
N A N D _CE4
N A N D _CE3
N A N D _CE2
N A N D _CE1
N A N D _RE
N A N D _W E
N A N D _CLE
VBUS
DD+
GND
1
2
3
4
Read Only
V33
On Board Flash 2-4 only available on ST72681 /R21
V18_USB
J1
RO
RED LED
13
14
15
16
17
18
19
20
21
22
23
24
C1
S1
36
35
34
33
32
31
30
29
28
27
26
25
U5
N A N D _CLE
N A N D _A LE
N A N D _W E
N A N D _W P
USB_V5
NAND W P
READ ONL Y
EEPROM SCL
VSS_2
VDD33_2
NC
NC
RESET
LED2
LED1
NAND AL E
VSS_3
U4
N A N D _RnB
N A N D _RE
N A N D _CE4
V33
DP
DM
VDDA
OSCIN
OSCOUT
VSSA
RREF
VSSC
VDDC
VDD3
USBDP
USBDM
VSSBL
VDDBL
N A N D _CLE
N A N D _A LE
N A N D _W E
N A N D _W P
R5
11.3K 1%
N A N D _RnB
N A N D _RE
N A N D _CE3
500
N A N D _A LE
1
2
3
4
5
6
7
8
9
10
11
12
CRYSTAL 12M H_NX4025DA
R6
10K
NC
N C /#R ES
NC
NC
NC
NC
RB4
NC
RB3
I/O 7
G N D /R B 2
I/O 6
#R /B
I/O 5
#R E
I/O 4
NC
#C E
#C E2
NC
NC
N C /PR E
V CC
V CC
V SS
V SS
#C E3
NC
NC
#C E4
C LE
NC
A LE
I/O 3
#W E
I/O 2
#W P
I/O 1
NC
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
V SS_1
V D D 33_1
NC
D [0]
D [1]
D [2]
D [3]
D [4]
D [5]
D [6]
D [7]
R nB
1
NAND
NAND
NAND
NAND
NAND
NAND
NAND
NAND
NAND
3
C16
18pF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ST72681_QF
P48
2
V D D O U SB
V SS_4
V D D 33_4
N A N D C E4
N A N D C E3
N A N D C E2
N A N D C E1
N A N D RE
NAND W E
N A N D C LE
NC
V D D 33_3
18pF
4
N A N D _W P
U?
XT1
C15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R4
V18_USB
48
47
46
45
44
43
42
41
40
39
38
37
V18_USB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D0
D1
D2
D3
D4
D5
D6
D7
D3
D2
D1
D0
NAND_RnB
V33
ST72681/R20 only supports single NAND Flash Chip Enable configuration (one NAND
device with one Chip Enable signal). Note that pins NAND_RnB2, NAND_CE2, NAND_CE3
and NAND_CE4 should remain unconnected.
ST72681/R21 can support up to four NAND Flash Chip Enable signals. The application can
use one of the following configurations:
8/32
●
One NAND device with four Chip Enable signals; NAND_CE1, NAND_CE2,
NAND_CE3 and NAND_CE4 are used.
●
One NAND device with two Chip Enable signals; NAND_CE1 and NAND_CE2 are
used.
●
One NAND device with one Chip Enable signal; only NAND_CE1 is used.
●
Two NAND devices with two Chip Enable signals; NAND_CE1 and NAND_CE2 are
used to select the first NAND device and NAND_CE3 and NAND_CE4 to select the
second NAND device.
●
Two NAND devices with one Chip Enable signal; NAND_CE1 and NAND_CE2 are
used to select is used to select the first NAND device and the 2nd NAND device,
respectively.
●
4 NAND devices with 1Chip Enable signal; NAND_CE1 selects the first NAND device,
NAND_CE2 the 2nd NAND device, NAND_CE3 to select the third, and NAND_CE4 to
select the fourth NAND device.
ST72681
NAND interface
4
NAND interface
4.1
NAND support table
Table 6.
Known NAND compatibility guide for R20 and R21 devices
NAND name
Samsung K9F1G08U
Samsung K9F2G08U
Samsung K9F4G08U
Samsung K9K4G08U
Samsung K9W4G08U
Samsung K9K8G08U
Samsung K9W8G08U
Samsung K9WAG08U
Samsung K9NBG08U
Samsung K9G4G08U
Samsung K9L8G08U
Samsung K9HAG08U
Samsung K9MBG08U
Toshiba TH58NVG0S3
Toshiba TH58NVG1S3
Toshiba TH58NVG2S3
Toshiba TH58NVG1D4
Toshiba TH58NVG2D4
Toshiba TH58NVG3D4
ST NAND01GW3B
ST NAND02GW3B
ST NAND04GW3B
ST NAND08GW3B
ST NAND04GW3C
Hynix HY27UF081G2M
Hynix HY27UG082G2M
Hynix HY27UG084G2M
Hynix HY27UH084G5M
Hynix HY27UH088G2M
Hynix HY27UT084G2M
Hynix HY27UU088G5M
Micron 29F2G08AA
Micron 29F4G08BA
Micron 29F8G08FA
Note:
NAND size (Mbytes or Gbytes)
and type
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
512 MB; SLC2K; Dual CE
1 GB; SLC2K; Single CE
1 GB; SLC2K; Dual CE
2 GB; SLC2K; Dual CE
4 GB; SLC2K; Quad CE
512 MB; MLC2K; Single CE
1 GB; MLC2K; Single CE
2 GB; MLC2K; Dual CE
4 GB; MLC2K; Quad CE
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
256 MB; MLC2K; Single CE
512 MB; MLC2K; Single CE
1 GB; MLC2K; Single CE
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
1 GB; SLC2K; Single CE
512 MB; MLC2K; Single CE
128 MB; SLC2K; Single CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
512 MB; SLC2K; Dual CE
1 GB; SLC2K; Single CE
512 MB; MLC2K; Single CE
1 GB; MLC2K; Dual CE
256 MB; SLC2K; Single CE
512 MB; SLC2K; Single CE
1 GB; SLC2K; Dual CE
Number of NAND devices
supported
R20 device
R21 device
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
1, 2, 3 or 4
1 or 2
1 or 2
1
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
1
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
1, 2, 3 or 4
1, 2, 3 or 4
1 or 2
This list is provided as a guide only as it is not possible to automatically guarantee support
for all the additions and updates across the listed ranges of manufacturers’ devices.
9/32
NAND interface
4.2
ST72681
NAND error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error
occurrence depends on the Flash cell type (MLC or SLC).
The ST72681 embeds hardware and firmware mechanisms to correct the errors.
4.2.1
Hardware error correction
The ST72681 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly
manages 512-byte data packets on the NAND I/O system.
Based on a data packet contents, the cell generates an 80-bit Error Correction Code (ECC)
consisting of 8 words each containing 10 bits.
During write operations to NAND memory, the 512-bytes of data and the ECC are stored
together in the same page. The ECC is stored in the corresponding Redundant Area (RA),
using 10 bytes.
During read operations, the 512-bytes of data and the 8 ECC words are read back and are
passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4
symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC).
The hardware cell gives 3 possible results:
4.2.2
■
No error detected: the data packet can be used as it is.
■
Correctable error detected: the corrected data are available in a specific 512-byte buffer
in the Reed-Solomon cell and are ready to use.
■
Uncorrectable error detected: data corruption is not repairable.
Firmware error management
The firmware defines the error correction possibilities with the corrected data packet.
When data is not repairable, the block is considered as bad and replaced by another one.
See below for further information.
4.3
Management of bad NAND blocks
NAND device manufacturers deliver their products with factory-marked bad blocks. This
marking depends on the manufacturer and the NAND type (page size, memory technology,
etc.). The ST72681 supports all bad block markings currently available on the market.
4.3.1
Bad block identification
During firmware initialization, the MCU scans the entire NAND configuration to identify bad
blocks.
A bad block is defined as follows:
10/32
■
5 different Block Status bytes are considered: 4 Status bytes from page 0 and 1 from an
other page (page 127 for MLC NAND; page 1 for SLC NAND).
■
The considered block is declared bad if 1 of these 5 bytes contains 4 bits or more at 0.
ST72681
4.3.2
NAND interface
Bad block replacement
The firmware works with groups of 1024 blocks, called zones. A complete NAND
configuration can contain several zones.
Each zone is described in a Look Up Table (LUT) containing 1024 entries. A LUT is
composed of 3 parts: used blocks, free blocks and bad blocks.
●
The “bad blocks” part contains as many entries as the number of bad blocks identified
in that zone.
●
The “used blocks” part can have a size of 1000, 900 or 500 entries. This size is
configurable and also depends on the number of identified bad blocks.
●
The “free blocks” part contains the remaining entries.
The used blocks part is used to do a correspondence between NAND blocks and logical
address ranges.
This system allows all bad blocks to be masked from the Host. As a result, bad blocks are
never seen. Only a range of logical addresses are visible which correspond to the sum of
the used blocks part of all zones.
4.3.3
Late fail block
During normal application life, defects can appear in the NAND memory. Under certain
conditions, these defects are not correctable and the corresponding block is declared as
“bad”.
In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by
new blocks from the “free blocks” part.
4.4
Wear levelling
During normal application life, the NAND is written and erased (by block) many times. The
NAND device is guaranteed for a limited number of writes (about 100 000 cycles). As a
consequence, the controller must keep write/erase operations to a minimum for any
individual block.
A method to limit these cycles is to use a “Wear Levelling” scheme between all NAND
blocks.
4.4.1
LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free
blocks which are used in the “wear levelling” scheme.
During write command treatment, the firmware calculates the zones, blocks and pages for
data write access. In a block write operation, the firmware applies the following scheme to
avoid block wearing:
●
The least recently-used block is chosen from the free block part of the LUT.
●
Valid data from the old block is copied to the new block.
●
New data from the write command is written to the new block.
●
The old block is erased.
●
The LUT is updated after identifying the new block in the used block part and the old
block in the free block part.
11/32
NAND interface
ST72681
Using this scheme, a logical address range doesn’t correspond to a constant block. A write
command repeated several times to the same logical address writes physically into different
blocks.
This method shares the wearing evenly across all blocks of the concerned zone.
4.5
NAND interface configuration
Applications based on ST72681 can be configured through a dedicated PC software tool.
The NAND RE and WE signals frequencies can be independently configured to 30 MHz, 20
MHz, 15 MHz, 12 MHz and 10 MHz.
The logical size reduction factor can be configured to 90% or 50% in the event of having too
many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
12/32
ST72681
Mass storage implementation
5
Mass storage implementation
5.1
USB characteristics
The ST72681 is compliant with USB 2.0 specification.
It is able to operate in both high speed and full speed modes using a bidirectional control
endpoint 0 and a bidirectional bulk endpoint 2.
It automatically recognizes the speed to use on the bus by a process of negotiation with
USB Host.
5.2
BOT / SCSI implementation
5.2.1
BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is
implemented. It allows the device to be recognized by the host as a mass-storage USB
device.
5.2.2
SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage
operations.
The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4
revision 7a (SCSI Primary Commands 4).
5.2.3
Bootability specification
The USB Mass Storage Specification for Bootability revision 1.0 is implemented.
It allows the PC host to boot the operating system from the USB mass storage application.
In this case, the Host uses BOT LUN 0 (logical unit number).
A specific tool must be used to format the logical drive in order to make it bootable by
programming the correct information.
5.3
Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device.
In this case, up to 3 different drives are available: public drive, additional drive and private
drive.
Public and additional drives can be configured as removable drive, hard disk drive or CDROM drive.
13/32
Mass storage implementation
5.3.1
ST72681
Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is
declared as a removable drive.
The public drive is mandatory and can not be removed from the configuration. By
customization (using PC software), it can be declared as a removable drive, a CD-ROM
drive or a hard disk drive.
This drive is the LUN 0 in BOT commands.
5.3.2
Private drive
The Private drive is optional. Its type is “removable drive” and is not configurable.
This drive is protected by password and cannot be directly accessed through the PC
operating system. A PC software tool is necessary to send a command with the password to
unlock the device. The device is then open and accessible by the PC operating system until
reset or reception of a new command to lock the drive.
This drive is the LUN 1 in BOT commands.
5.3.3
Additional drive
The additional drive is optional. Its type can be “removable drive”, “hard disk drive” or “CDROM drive”.
This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if
the private drive option is active.
5.3.4
CD-ROM considerations
When a drive is declared as CD-ROM, the ST72681/R21 manages this drive with a logical
block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a
CDFS partition on this CD-ROM. See the ‘ST7268x Production Tool User Manual’ for more
information.
Note that the ST72681/R20 doesn’t consider the CD-ROM partition as a specific case. The
logical block size is 512 bytes and any file system can be used.
In both cases, the CD-ROM partition allows the use of the autorun operating system feature.
During device connection, the CD-ROM partition is recognized and the host tries to run the
application corresponding to the ‘autorun.inf’ file present into this CD-ROM partition.
5.4
Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters,
additional customizable information includes:
14/32
●
USB parameters: VID, PID, all string information
●
SCSI parameters: strings for inquiry commands
ST72681
Human interface implementation
6
Human interface implementation
6.1
LED behavior
The application is designed to manage 2 LEDs. This behavior is configurable through PC
dedicated software: ‘ST7268x Production Tool’.
By default, LED 1 responds to NAND access activity and LED 2 responds to USB activity.
Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and
NAND activity.
6.2
Read only switch
The READ ONLY pin of the ST72681 is an input pin to be connected to VDD or GND
depending on the behavior of the device.
●
When this pin is connected to GND, no limitations are applied on the PC command
received.
●
When this pin is connected to VDD or unconnected, the firmware filters all accesses to
the NAND which modify the NAND state (write, erase, etc.) and returns an error to the
PC.
15/32
Electrical characteristics
ST72681
7
Electrical characteristics
7.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the Devices with an ambient temperature at TA = 25°C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3Σ).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25°C and VDD33 = 3.3V. They are
given only as design guidelines and are not tested.
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4.
Figure 4.
Pin loading conditions
DEVICE PIN
CL
7.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5.
Figure 5.
Pin input voltage
DEVICE PIN
VIN
16/32
ST72681
7.2
Electrical characteristics
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the Device. This is a stress rating only and functional operation of the Device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
7.2.1
Voltage characteristics
Table 7.
Voltage characteristics
Symbol
Ratings
VDD33 - VSS
VIN (1) (2)
Input voltage on any other pin
VESD(HBM)
VESD(MM)
Supply voltage
Maximum value
Unit
4.0
V
VSS - 0.3 to
VDD33 + 0.3
V
Electro-static discharge voltage (Human Body Model) See Section 7.6.3 on
page 21
Electro-static discharge voltage (Machine Model)
1. Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must
not be directly tied to VDD33 or VSS.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN > VDD33 while a negative injection is
induced by VIN < VSS.
7.2.2
Current characteristics
Table 8.
Current characteristics
Symbol
IVDD33
IVSS
Ratings
Maximum value
Total current into VDD33 power lines (source) (1)
Total current out of VSS ground lines (sink)
(1)
Unit
200
200
Output current sunk by any I/O (type D2)
25
Output current sunk by any I/O (type D4)
35
Output current sunk by any I/O (type D8)
50
Output current source by any I/Os and control pin
-25
mA
IIO
(2)
1. All power supply (VDD33) and ground (VSS) lines must always be connected to the external supply.
2. Refer to Table 5: General Purpose I/O Ports / Mass Storage I/Os for the output drive capability of each of
the I/Os.
7.2.3
Thermal characteristics
Table 9.
Symbol
Thermal characteristics
Ratings
TSTG
Storage temperature range
TJMAX
Maximum junction temperature
Value
Unit
-65 to +150
°C
120
°C
17/32
Electrical characteristics
ST72681
7.3
Operating conditions
7.3.1
General operating conditions
Table 10.
General operating conditions
Symbol
fCPU
VDD33
TA
Figure 6.
Parameter
Conditions
Min
Max
Unit
0
30
MHz
3.0
3.6
V
0
70
°C
Internal clock frequency
Power supply
Ambient temperature range
Guaranteed functionality range
fCPU [MHz]
FUNCTIONALITY
GUARANTEED
IN THIS AREA
30
FUNCTIONALITY
NOT GUARANTEED 15
IN THIS AREA
6
3
SUPPLY VOLTAGE [VDD33]
0
2.5 2.7
2.0
7.4
Supply current characteristics
7.4.1
RUN and SUSPEND modes
Table 11.
Symbol
7.4.2
3.6
RUN and SUSPEND modes
Parameter
Supply current in RUN mode
IDD
3.3
3.0
Conditions
fOSC = 12 MHz
Supply current in SUSPEND mode VDD33 = 3.3V, TA = +25°C
Min.
Typ.
Max. Unit
15
25
35
mA
60
90
190
µA
Supply and clock managers
Table 12.
Supply and clock managers
Symbol
Parameter
IDD(CK)
Supply current of crystal oscillator (3)
Conditions
Typ. (1)
Max. (2)
Unit
1000
2000
µA
1. Typical data are based on TA = 25°C and fCPU = 12 MHz.
2. Not tested in production, guaranteed by characterization.
3. Data based on characterization results done with the external components specified in Section 7.5.2:
Crystal oscillator, not tested in production.
18/32
ST72681
7.5
Electrical characteristics
Clock and timing characteristics
Subject to general operating conditions for VDD33, fOSC, and TA.
7.5.1
General timings
Table 13.
General timing characteristics
Symbol
Parameter
tc(INST)
Instruction cycle time
tv(IT)
Interrupt reaction time
tv(IT) = Δtc(INST) + 10
Conditions
Min.
Typ. (1)
Max.
Unit
2
3
12
tCPU
133
200
800
ns
10
22
tCPU
0.666
1.466
µs
fCPU = 15 MHz
(2)
fCPU = 12 MHz
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles
required to finish executing the current instruction.
7.5.2
Crystal oscillator
The ST72681 internal clock is supplied from a crystal oscillator. All the information given in
this paragraph are based on characterization results with specified typical external
components. In the application the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer
to the crystal manufacturer for more details (frequency, package, accuracy...).
Table 14.
Crystal oscillator characteristics
Symbol
Parameter
Conditions
fOSC
Oscillator frequency
CKACC
Total crystal oscillator accuracy abs. value + temp + aging
αOSC
Crystal oscillator duty cycle (1)
Min.
Typ.
Max.
12
45
50
Unit
MHz
±60
ppm
55
%
1. The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal
manufacturer for more details.
Figure 7.
Typical application with a crystal oscillator
VDDA
CL
OSCIN
CRYSTAL
CL
Device
OSCOUT
RsOscout (1)
1. Depending on the crystal oscillator power dissipation, a serial resistor RsOscout may be added. Refer to the
crystal oscillator manufacturer for more details.
Table 15.
Typical CL and RS values by crystal oscillator
Supplier
Typical crystal oscillator
CL (pF)
RsOscout (Ω)
NDK
AT51 or AT41
16
560
19/32
Electrical characteristics
7.6
ST72681
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.6.1
Functional EMS (electro magnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
■
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
■
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD33 and
VSS33 through a 100pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 16.
Symbol
20/32
EMC characterization and optimization values
Parameter
Conditions
Level/
Class
VFESD
VDD33 = 3.3V, TA = +25°C, fOSC = 12 MHz
Voltage limits to be applied on any I/O
complies with IEC 1000-4-2
pin to induce a functional disturbance
specifications
4B
VFFTB
Fast transient voltage burst limits to be
VDD33 = 3.3V, TA = +25°C, fOSC = 12 MHz
applied through 100pF on VDD33 and
complies with IEC 1000-4-4
VSS33 pins to induce a functional
specifications
disturbance
4A
ST72681
7.6.2
Electrical characteristics
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 17.
Symbol
SEMI
Electromagnetic interference
Parameter
Peak level
Conditions(1)
Monitored
Frequency Band
Max vs.
[fOSC@12 MHz]
0.1 MHz to 30 MHz
VDD33 = 3.3V, TA = +25°C,
30 MHz to 130 MHz
complies with SAE J 1752/3
130 MHz to 1 GHz
specifications
SAE EMI Level
Unit
20
25
dBµV
25
4
-
1. Refer to Application Note AN1709 for data on other package types.
7.6.3
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electro-static discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard.
Table 18.
Symbol
Absolute Maximum Ratings
Ratings
Conditions
VESD(HBM) Electro-static discharge voltage (Human Body Model) TA = +25°C
Max.(1) Unit
2000
V
1. Data based on characterization results, not tested in production.
Static and dynamic latch-up
■
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test complies with EIA/JESD 78 IC latch-up specifications. For more details,
refer to the application note AN1181.
■
DLU: Electro-static discharges (one positive then one negative test) are applied to each
pin of 3 samples when the micro is running to assess the latch-up performance in dynamic
mode. Power supplies are set to the typical values, the oscillator is connected as near as
possible to the pins of the micro and the component is put in reset mode. This test
complies with IEC1000-4-2 and SAEJ1752/3 specifications. For more details, refer to the
application note AN1181.
21/32
Electrical characteristics
Table 19.
Symbol
LU
DLU
ST72681
Electrical sensitivity values
Parameter
Class (1)
Conditions
Static latch-up class
TA = +25°C
A
Dynamic latch-up class
VDD33 = 3.3V, fOSC = 12 MHz, TA = +25°C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
7.7
I/O port pin characteristics
7.7.1
General characteristics
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Table 20.
Symbol
VIL
General I/O port pin characteristics
Parameter
Conditions
Typ.
Max.
Unit
0.16 x
VDD33
Input low level voltage
TTL ports
VIH
Input high level voltage
Vhys
Schmitt trigger voltage hysteresis (1)
IL
Min.
Input leakage current
IL5V
5V tolerant input leakage current
RPU
Weak pull-up equivalent resistor (2)
400
mV
VSS ≤ VIN ≤ VDD33,
standard I/Os
1
VSS ≤ VIN ≤ VDD33
10
VIN = 5V, 25°C
VIN = VSS
V
0.85 x
VDD33
30
VDD33 =
3.3V
32
50
75
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested
in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on
characterization results, tested in production at VDD33 max.
Figure 8.
Typical VIL and VIH standard I/Os
Vil/Vih (V)
2.5
Vil/Vih (V)
2
1.5
1
0.5
0
2.7
2.8
2.9
3
3.1
3.2
Vdd (V)
22/32
3.3
3.4
3.5
µA
3.6
kΩ
ST72681
Electrical characteristics
Figure 9.
Typical RPU vs. VDD33 with VIN=VSS
I/Os pullup resistance
I/Os pullup resistance (kOhms)
60
55
50
45
40
35
30
2.7
2.8
2.9
3
3.1
3.2
Vdd (V)
3.3
3.4
3.5
3.6
Figure 10. Two typical Applications with unused I/O Pin
VDD33
10kΩ
Device
10kΩ
UNUSEDUNUSED
I/O PORT
I/O PORT
10kΩ
UNUSED I/O PORT
DeviceDevice
Output driving current
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Table 21.
Symbol
VOL (1)
Output driving current
Parameter
Conditions
Output low level voltage for a D2 I/O pin when 8
pins are sunk at same time (see Figure 11)
IIO = 2 mA
300
Output low level voltage for a D4 I/O pin when 8
pins are sunk at same time (see Figure 12)
IIO = 4 mA
400
IIO = 8 mA
500
IIO = 2 mA
600
Output high level voltage for a D4 I/O pin when 8
pins are sourced at same time (see Figure 15 )
IIO = 4 mA
600
Output high level voltage for a D8 I/O pin when 8
pins are sourced at same time (see Figure 16)
IIO = 8 mA
600
Output low level voltage for a D8 I/O pin when 8
pins are sunk at same time (see Figure 13 )
Output high level voltage for a D2 I/O pin when 8
pins are sourced at same time (see Figure 14)
VDD33VOH (2)
VDD33 = 3.3V
7.7.2
Min.
Max.
Unit
mV
mV
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 7.2.2: Current
characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 7.2.2:
Current characteristics and the sum of IIO (I/O ports and control pins) must not exceed IVDD33. True open
drain I/O pins do not have VOH.
23/32
Electrical characteristics
ST72681
Figure 11. Typical VOL at VDD33 = 3.3V (I/O D2)
140
Vol 2mA (mV)
120
100
80
60
40
20
0
0
1
2
3
4
Iol (mA)
Figure 12. Typical VOL at VDD33 = 3.3V (I/O D4)
140
Vol 4mA (mV)
120
100
80
60
40
20
0
0
1
2
3
4
5
6
Iol (mA)
Figure 13. Typical VOL at VDD33 = 3.3V (I/O D8)
140
Vol 8mA (mV)
120
100
80
60
40
20
0
0
2
4
6
8
10
Iol (mA)
Figure 14. Typical VDD33-VOH vs. VDD33 (I/O D2)
Voh 2mA (mV)
200
150
100
50
0
0
1
2
3
4
Ioh (mA)
Voh 4mA (mV)
Figure 15. Typical VDD33-VOH vs. VDD33 (I/O D4)
180
160
140
120
100
80
60
40
20
0
0
1
2
3
Ioh (mA)
24/32
4
5
6
ST72681
Electrical characteristics
Voh 8mA (mV)
Figure 16. Typical VDD33-VOH vs. VDD33 (I/O D8)
180
160
140
120
100
80
60
40
20
0
0
2
4
6
8
10
Ioh (mA)
7.8
Control pin characteristics
7.8.1
Asynchronous RESET pin
TA = 0 to +55 °C unless otherwise specified.
Table 22.
Symbol
VIL
RESET pin characteristics
Parameter
Conditions
0.85 x
VDD33
Vhys
Schmitt trigger voltage hysteresis1)
RON
Pull-up equivalent resistor
450
VDD33 = 3.3V
20
VDD33 = 2V
duration (4)
External reset pulse
tiw(RSTL)
Internal reset pulse duration
80
2.5
(3)
tew(RSTL)
40
Unit
V
mV
100
External reset pulse hold time (2)
Filtered glitch duration
Max.
0.16 x
VDD33
Input high level voltage
tg(RSTL)
Typ.
Input low level voltage (1)
VIH
teh(RSTL)
Min.
kΩ
µs
200
ns
2
tCPU
500
µs
1. The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1:
Asynchronous RESET pin. Otherwise the reset will not be taken into account internally.
2. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short
pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production,
guaranteed by design.
3. The reset network protects the device against parasitic resets.
4. The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator
at power-up. Not tested in production, guaranteed by design.
Figure 17. Typical RON on RESET pin
NRESET pullup (kOhms)
100
90
80
70
60
50
40
2
2.5
3
3.5
Vdd (V)
25/32
Electrical characteristics
ST72681
7.9
Other communication interface characteristics
7.9.1
MSCI parallel interface
Figure 18. Timing diagrams for input mode (with max load on CTRL signal = 50 pF)
CTRL
external
DATA
DATA(i)
ext device
DATA(i+1)
tDS
tDS is the setup time for data sampling
Figure 19. Timing diagrams for output mode (with max CTRL signal = 50 pF, DATA)
CTRL
external
DATA
DATA(i)
external
DATA(i+1)
tDO
tDO is the data output time for data sampling
Table 23.
MSCI Parallel Interface: DC Characteristics
Conditions
Parameter
tDS
Data Setup Time
11
ns
tDO
Data Output time
6
ns
CCTRL
CTRL line capacitance
50
pF
CDATA
Data line capacitance
50
pF
1. Data based on design simulation and not tested in production.
26/32
Min.
Typ. (1)
Symbol
Max.
Unit
ST72681
7.9.2
Electrical characteristics
Universal serial bus interface (USB)
Table 24.
DC characteristics
Symbol
Parameter
IDDsuspend
Suspend current
RPU
Pull-up resistor (2)
Conditions
VDD33 = 3.3V, Powerdown
mode, 25°C (1)
Min.
Typ.
Max.
Unit
60
90
190
uA
1.5
kΩ
Full speed mode
VTERM
Termination voltage
0.8
2.0
V
VOH
High level output voltage
2.8
3.6
V
VOL
Low level output voltage
0.8
V
2.0
V
Crossover voltage
VCRS
1.3
High speed mode
VHSOH
HS data signalling high
400
mV
VHSOL
HS data signalling low
5
mV
1. The values provided do not take into account the current through both the 1.5kΩ pull-up resistor (on the
device-side) and the 15kΩ pull-down resistor (on the host-side).
2. Not tested in production, guaranteed by characterization.
Table 25.
Timing characteristics
Symbol
Parameter
Conditions
Min.
Max.
Unit
Full speed mode
tFR
Rise time
CL= 50 pF
4
20
ns
tFF
Fall time
CL= 50 pF
4
20
ns
Rise time
500 (1)
ps
Fall time
500 (1)
ps
480.24
Mb/s
High speed mode
tHSR
tHSF
tHSDRAT
HS data rate
479.76
1. Not tested in production, guaranteed by characterization.
Table 26.
USB High Speed Transmit Waveform requirements
Unit Interval (UI)
Voltage Level (DP - DN)
Time
-
2.082 to 2.084 ns
Level 1
475 mV
-
Level 2
-475 mV
-
Point 1
0V
5% UI
Point 2
0V
95% UI
Point 3
300 mV
35% UI
Point 4
300 mV
65% UI
Point 5
-300 mV
35% UI
Point 6
-300 mV
65% UI
27/32
Electrical characteristics
Figure 20. USB signal eye diagram
28/32
ST72681
ST72681
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 21. 48-pin low profile quad flat package outline
D
A
D1
A2
A1
b
E1
e
E
c
L1
L
Table 27.
θ
48-pin low profile quad flat package dimensions
inches(1)
mm
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
1.60
A1
0.05
A2
1.35
1.40
b
0.17
0.22
C
0.09
Max.
0.063
0.15
0.002
0.006
1.45
0.053
0.055
0.27
0.007
0.009
0.20
0.004
0.057
0.011
0.008
D
9.00
0.354
D1
7.00
0.276
E
9.00
0.354
E1
7.00
0.276
e
0.50
0.020
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
Number of Pins
N
48
1. Values in inches are converted from mm and rounded to 3 decimal digits.
29/32
Device ordering information
9
ST72681
Device ordering information
Table 28.
Feature comparison table
Features added in the
ST72681/R21 versus ST72681/R20
Support for up to 4 NAND Flash devices
Firmware revision R21 upgrades the number of
supported NAND Flash devices from 1 to 4 in a
single channel.
Continued AutoRun CDROM partition support
AutoRun runs a program when the USB Flash Drive
is inserted into a computer.
Table 29.
Ordering information
Package
Operating
voltage
Temperature
range
ST72681/R20
TQFP48 7x7mm
3.0V to 3.6V
0°C to +70°C
ST72681/R21 (latest firmware revision)
TQFP48 7x7mm
3.0V to 3.6V
0°C to +70°C
Part number
30/32
Description
ST72681
10
Revision history
Revision history
Table 30.
Document revision history
Date
27-May-2005
18-Nov-2005
06-Feb-2006
09-Jan-2007
30-Aug-2007
Revision
Changes
1.0
Changed status of the document
Changed description on 1st page
Removed unconnected pins in Table 5 on page 7
Changed Table 4 on page 6
Changed pin 5 description in Table 3 on page 6
Changed section 3 on page 7
Changed Figure 3 on page 8 and Figure 4
2.0
Electrical Characteristics section added, Section 4 on page 9
Additional features listed on front page
Status of document changed to Datasheet
Application schematics modified, Figure 4 removed
Section 4.6 (Memory Characteristics) removed
VDDOUSB marked as O (output) in Table 2 on page 6
3.0
Additional features listed on front page
Application schematics modified, Figure 3 on page 8
Feature comparison table added for R20 firmware update, Table 28
Figure 3 on page 8 updated, with note added
4.0
Additional features listed on front page related to firmware release
R21. Application schematics updated for R21, Figure 3 on page 8
Feature comparison table added for R21 firmware update, Table 28
IDDsuspend values and note updated, Table 24
5.0
Updated information in Table 6: Known NAND compatibility guide for
R20 and R21 devices on page 9.
Added Section 4.2: NAND error correction on page 10, Section 4.3:
Management of bad NAND blocks on page 10, Section 4.4: Wear
levelling on page 11 and Section 4.5: NAND interface configuration
on page 12.
Added Section 5: Mass storage implementation on page 13 and
Section 6: Human interface implementation on page 15.
Added internal clock frequency (fCPU) value in Table 10: General
operating conditions on page 18.
31/32
ST72681
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32/32