STP130NH02L N-channel 24V - 0.0034Ω - 120A - TO-220 STripFET™ Power MOSFET for DC-DC conversion Features Type VDSS RDS(on) ID STP130NH02L 24V <0.0044Ω 90(1) 1. Value limited by wire bonding ■ RDS(on) *Qg industry’s benchmark Low ■ Conduction losses reduced ■ Switching losses reduced ■ Low Threshold device 3 1 2 TO-220 Description These devices utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. It is ideal in high performance DC-DC converter applications where efficiency is to be achieved at very high output currents. Internal schematic diagram Application ■ Switching application Order code Part number Marking Package Packaging STP130NH02L P130NH02L TO-220 Tube April 2007 Rev 7 1/14 www.st.com 14 Contents STP130NH02L Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 ................................................ 8 STP130NH02L 1 Electrical ratings Electrical ratings Table 1. Symbol Vspike(1)) VDS VDGR Parameter Value Unit Drain-source voltage rating 30 V Drain-source voltage (VGS = 0) 24 V Drain-gate voltage (RGS = 20 kΩ) 24 V ± 20 V VGS Gate- source voltage ID(2) Drain current (continuous) at TC = 25°C 90 A ID(2) Drain current (continuous) at TC = 100°C 90 A Drain current (pulsed) 360 A Total dissipation at TC = 25°C 150 W 1 W/°C 900 mJ -55 to 175 °C IDM (3) Ptot Derating factor EAS (4) Tstg Tj Single pulse avalanche energy Storage temperature Max. operating junction temperature 1. Guaranteed when external Rg=4.7 Ω and tf < tfmax 2. Value limited by wire bonding 3. Pulse width limited by safe operating area 4. Starting TJ = 25°C, ID = 45A, VDD = 10V Table 2. Rthj-case Rthj-amb Tl Thermal data Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose 1.0 62.5 300 °C/W °C/W °C 3/14 Electrical characteristics 2 STP130NH02L Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 25mA VGS= 0 IDSS IGSS Gate body leakage current VGS = ±20V (VDS = 0) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V , ID = 45A gfs (1) V 1 10 µA µA ±100 µA 1 V 0.0034 0.0044 0.005 0.008 VGS = 5V, ID = 22.5A Unit Ω Ω Dynamic Parameter Test conditions Forward transconductance VDS = 10V, ID = 45A Min. Typ. Max. Unit 55 S 4450 1126 141 pF pF pF Crss Input capacitance Output capacitance Reverse transfer capacitance td(on) tr td(off) tf Turn-on delay time Rise time Off voltage rise time Fall time VDD = 10V, ID = 45A, RG = 4.7Ω, VGS = 10V (see Figure 13) 14 224 69 40 ns ns ns ns Rg Gate input resistance f = 1MHz gate DC bias=0 test signal level=20mV open drain 1.6 Ω Qg Total gate charge Gate-source charge Gate-drain charge VGS =10V (see Figure 14) 69 13 9 Qoss (2) Output charge VDS = 16V, VGS = 0 27 ns Qgls (3) Third-quadrant gate charge VDS < 0, VGS= 10V 64 ns Ciss Coss Qgs Qgd VDS = 15V, f = 1MHz, VGS = 0 VDD=10V, ID = 90A 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 2. Qoss = Coss* ∆VIN, Coss = Cgd + Cds. See power losses calculation 3. Gate charge for synchronous operation. 4/14 Max. 24 VDS = Max rating, TC=125°C VGS(th) Symbol Typ. VDS = Max rating, Zero gate voltage drain current (VGS = 0) Table 4. Min. 93 nC nC nC STP130NH02L Electrical characteristics Table 5. Symbol ISD ISDM VSD (1) trr Qrr IRRM Source drain diode Parameter Test conditions Min. Typ. Source-drain current Source-drain current (pulsed) Forward on voltage ISD = 45A, VGS = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 90A, di/dt = 100A/µs, VDD = 15V, TJ =150°C 47 58 2.5 Max. Unit 90 360 A A 1.3 V ns nC A 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 5/14 Electrical characteristics STP130NH02L 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/14 STP130NH02L Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized BVDSS vs temperature 7/14 Test circuit 3 STP130NH02L Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/14 Figure 18. Switching time waveform STP130NH02L 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/14 Package mechanical data STP130NH02L TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 10/14 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP130NH02L 5 Appendix A Appendix A Figure 19. Buck converter: power losses estimation The power losses associated with the FETs in a synchronous buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is removed to allow for a safer working junction temperature. ● The low side (SW2) device requires: ● Very low RDS(on) to reduce conduction losses ● Small Qgls to reduce the gate charge losses ● Small Coss to reduce losses due to output capacitance ● Small Qrr to reduce losses on SW1 during its turn-on ● The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source ● voltage to avoid the cross conduction phenomenon; ● The high side (SW1) device requires: ● Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate ● Small Qg to have a faster commutation and to reduce gate charge losses ● Low RDS(on) to reduce the conduction losses. 11/14 Appendix A STP130NH02L Table 6. Power losses calculation High side switching (SW1) Low side switch (SW2) R DS(on)SW1 * I 2L * δ R DS(on)SW2 * I 2L * (1 − δ ) Pconduction Vin * (Q gsth(SW1) + Q gd(SW1) ) * f * Pswitching Recovery (1) Not applicable Conductio n Not applicable IL Ig Zero Voltage Switching Vin * Q rr(SW2) * f Pdiode Vf(SW2) * I L * t deadtime * f Pgate(QG) Q g(SW1) * Vgg * f Q gls(SW2) * Vgg * f PQoss Vin * Q oss(SW1) * f Vin * Q oss(SW2) * f 2 2 1. Dissipated by SW1 during turn-on Table 7. Parameters meaning Parameter d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction Pswitching 12/14 Meaning On state losses On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses PQoss Output capacitance losses STP130NH02L 6 Revision history Revision history Table 8. Revision history Date Revision Changes 14-Mar-2005 4 Preliminary document 24-Mar-2005 5 New package inserted (TO-220) 19-Jun-2006 6 New template, no content change 13-Apr-2007 7 Package removed (D2PAK) 13/14 STP130NH02L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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