STMICROELECTRONICS STE2001DIE1

STE2001
65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
PRODUCT PREVIEW
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65 x 128 bits Display Data RAM
Configurable matrix: 65 x 128 or 33 x 128
Programmable (65/33) MUX rate
Row by Row Scrolling
Automatic data RAM Blanking procedure
Selectable Input Interface:
• I2C Bus Fast and Hs-mode (read and write)
• Parallel Interface (write only)
• Serial Interface (write only)
Fully Integrated Oscillator requires no external
components
Fully Integrated Configurable LCD bias voltages
generator with:
• Selectable (5X, 4X, 3X, 2X) multiplication factor
• Effective sensing for High Precision Output
• Four selectable temperature compensation
coefficients
Designed for chip-on-glass (COG) applications
Programmable bottom row pads mirroring and
top row pads mirroring for compatible with both
TCP and COG applications
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Low Power Consumption, suitable for battery
operated systems
Logic Supply Voltage range from 1.9 to 5V
High Voltage Generator Supply Voltage range
from 2.4 to 4.5V
Display Supply Voltage range from 4.5 to 9V
DESCRIPTION
The STE2001 is a low power CMOS LCD controller
driver. Designed to drive a 65 rows by 128 columns
graphic display, provides all necessary functions in a
single chip, including on-chip LCD supply and bias
voltages generators, resulting in a minimum of externals components and in a very low power consumption. The STE2001 features three standard interfaces
(Serial, parallel, I2C) for ease of interfacing with the
host µcontroller.
Type
Ordering Number
Bumped Wafers
STE2001DIE1
Bumped Dice on Waffle Pack
STE2001DIE2
Figure 1. Block Diagram
OSC
CO to C127
R0 to R64
COLUMN
DRIVERS
ROW
DRIVERS
DATA
LATCHES
SHIFT
REGISTER
TIMING
GENERATOR
OSC
CLOCK
BIAS VOLTAGE
GENERATOR
VLCDIN
VLCDSENSE
HIGH VOLTAGE
GENERATOR
VLCDOUT
65 x 128
RAM
SCROLL
LOGIC
RESET
RES
TEST_0_13
VDD1,2,3
DATA
REGISTER
VSS1,2
TEST
DISPLAY
CONTROL
LOGIC
INSTRUCTION
REGISTER
BSY_FLG
SEL1,2
I2CBUS
SAO
SCL
SDA_IN
PARALLEL
SDA_OUT
DB0 to DB7 E
PD/C
SERIAL
SCE
SDIN
SCLK
SD/C
October 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
D00IN1137
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STE2001
PIN DESCRIPTION
N°
Pad
Type
R0 to R64
1 to 16
145 to 177
257 to 272
O
LCD Row Driver Output
C0 to C127
17 to 144
O
LCD Column Driver Output
VSS1,2
227 to 238
GND
VDD1
186 to 191
Supply
IC Positive Power Supply
VDD2,3
192 to 201
Supply
Internal Generator Supply Voltages.
VLCDIN
246 to 251
Supply
LCD Supply Voltages for the Column and Row Output Drivers.
VLCDOUT
239 to 244
Supply
Voltage Multiplier Ouput
VLCDSENSE
245
Supply
Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine
Tuning
SEL1,2
183, 184
I
Interface Mode Selection
SDA_IN
223
I
I2C Bus Data In
SDA_OUT
222
O
I2C Bus Data Out
SCL
224
I
I2C bus Clock
SA0
225
I
I2C Slave Address LSB
OSC
185
I
External Oscillator Input
RES
221
I
Reset Input. Active Low.
DB0 to
DB7
211 to 218
I
Parallel Interface 8 Bit Data Bus
E
220
I
Parallel Interface Data Latch Signal. Data are Latched on the Falling EDGE.
PD/C
219
I
Parallel Interface Data/Command Selector
SDIN
207
I
Serial Interface Data Input
SCLK
210
I
Serial Interface Clock
SCE
209
I
Serial Interface ENABLE. When Low the Incoming Data are Clocked In.
SD/C
208
I
Serial Interface Data/Command selection
BSYFLG
206
O
Active Procedure Flag. Notice if There is an ongoing Internal Operation. Active
Low.
T1 to T13
178 to 181
202 to 205
226
252 to 256
I/O
Test Pads.
2/36
Function
Ground pads. VSS1 is GND for V DD1, VSS2 for VDD2 and VDD3
STE2001
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD1
Supply Voltage Range
- 0.5 to + 6.5
V
VDD2,3
Supply Voltage Range
- 0.5 to + 5
V
LCD Supply Voltage Range
- 0.5 to + 10
V
ISS
Supply Current
- 50 to +50
mA
Vi
Input Voltage (all input pads)
-0.5 to VDD2,3 + 0.5
V
Iin
DC Input Current
- 10 to + 10
mA
Iout
DC Output Current
- 10 to + 10
mA
Ptot
Total Power Dissipation (Tj = 85°C)
300
mW
Po
Power Dissipation per Output
30
mW
Tj
Operating Junction Temperature
-40 to + 85
°C
Storage Temperature
- 65 to 150
°C
VLCD
Tstg
ELECTRICAL CHARACTERISTICS
DC OPERATION
(VDD1 = 1.9 to VDD2,3 + 0.5V; VDD2,3 = 2.4 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 9V; Tamb =-40 to 85°C; unless otherwise
specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1.9
VDD2,3
+ 0.5
V
Tamb =-20 to 85°C
1.8
VDD2,3
+ 0.5
V
Supply Voltages
VDD1
Supply Voltage
VDD2,3
Supply Voltage
LCD Voltage Internally
generated
2.4
4.5
V
VLCDIN
LCD Supply Voltage
LCD Voltage Supplied externally
4.5
9
V
VLCDOUT
LCD Supply Voltage
Internally generated; note 1
4.5
9
V
Supply Current
VDD = 2.8V; V LCD = 7.6V; 4x
charge pump; fsclk = 0;
Tamb = 25°C; note 3.
8
15
µA
Voltage Generator Supply
Current
with VOP = 0 and PRS = 0
with external VLCD = 7.6V
10
15
µA
VLCD =7.6V; VDD =2.8V;
fsclk = 0; Tamb = 25°C; no display
load; 4x charge pump; note 3,6
Fosc = 0
70
115
µA
I(VDD1)
I(VDD2,3)
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STE2001
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
I(VDD1,2,3)
Total Supply Current
VLCD = 7.6V; V DD =2.8V;
4x charge pump; fsclk = 0; Tamb
= 25°C; no display load; note 3,6
Fosc = 0
80
125
µA
I(VLDCIN)
External LCD Supply Voltage
Current
VDD =2.8V; V LCD =7.6V;no
display load; fsclk = 0;
Tamb = 25°C; note 3. Fosc = 0
15
25
µA
Logic Inputs
VIL
Logic LOW voltage level
VIN = Vih (tp < 10µs)
VSS
0.3
VDD
V
VIH
Logic HIGH Voltage Level
VIN = Vil (tp < 10µs)
0.7
VDD
VDD2,3
+ 0.5
V
Iin
Input Current
Vin = VSS1 or VDD1
-1
1
µA
Column and Row Driver
Rrow
ROW Output Resistance
12
20
kohm
R col
Column Output resistance
12
20
kohm
Vcol
Column Bias voltage accuracy
-100
100
mV
Vrow
Row Bias voltage accuracy
-100
100
mV
-300
300
mV
No load
LCD Supply Voltage
VLCD
TC
LCD Supply Voltage accuracy;
Internally generated
VDD = 2.8V; V LCD = 7.6V;
fsclk=0; Tamb=25 C;
no display load; note 2, 3, 6 & 7
Temperature coefficient
00
-550
PPM/°C
01
-1350
PPM/°C
10
-1650
PPM/°C
11
-2650
PPM/°C
Notes: 1.
2.
3.
4.
5.
6.
The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load.
Internal clock
When fsclk = 0 there is no interface clock.
Power-down mode. During power-down all static currents are switched-off.
If external VLCD, the display load current is not transmitted to I DD
Tolerance depends on the temperature; (typically zero at Tamb = 27°C), maximum tolerance values are measured at the temperature range limit.
7. For TC0 to TC3
AC OPERATION
(VDD1 = 1.9 to VDD2,3 + 0.5V; VDD2,3 = 2.4 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 9V; Tamb =-40 to 85°C; unless otherwise
specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
20
38
70
kHz
20
38
100
kHz
INTERNAL OSCILLATOR
FOSC
Internal Oscillator frequency
FEXT
External Oscillator frequency
4/36
VDD = 2.8V;
STE2001
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
FFRAME
Frame frequency
fosc or fext = 38 kHz; note 1
TVHRL
Vdd1 to RES Low
note 2 and 10; CVLCD = 1µF
Tw(RES)
RES LOW pulse width
note 3
Reset Pulse Rejection
Tamb = 25°C; note 11
Reset Pulse Rejection
note 11
TSTART
Reset Pulse vs. Device Ready
Min.
Typ.
Max.
73
0
Unit
Hz
5
600
ms
ns
µs
370
200
1
µs
ms
0
TVDD
I2C BUS INTERFACE (See note 4)
FSCL
SCL Clock Frequency
Fast Mode ; VDD1 =4.5V
DC
VDD1 =18V; Tamb = -20 to 70°C
High Speed Mode; Cb=100pF
(max); note 6; VDD1 =4.5V
DC
High Speed Mode; Cb=400pF
(max); note 6 ; VDD1 =4.5V
DC
400
kHz
400
kHz
3.4
MHz
1.7
MHz
TSCLL
Cb=100pF
160
ns
TSCLH
Cb=100pF
160
ns
TSCLL
Cb=400pF
320
ns
TSCLH
Cb=400pF
320
ns
TSU;DAT
Cb=100pF
30
ns
THD;DAT
Cb=100pF
30
ns
TSU;DAT
Cb=400pF
30
ns
THD;DAT
Cb=400pF
30
ns
TSU;STA
Cb=100pF
Note 8
170
ns
TSU;STA
Cb=400pF
Note 8
330
ns
THD;STA
Cb=100pF
Note 8
170
ns
THD;STA
Cb=400pF
Note 8
330
ns
TSU;STO
Cb=100pF
Note 8
170
ns
TSU;STO
Cb=400pF
Note 8
330
ns
TrCL
Cb=100pF
Note 5, 8
25
ns
TrCL
Cb=400pF
Note 5, 8
50
ns
TrCL1
Cb=100pF
Note 5, 8
30
ns
TrCL1
Cb=400pF
Note 5, 8
120
ns
TrDA
Cb=100pF
Note 5, 8
30
ns
TrDA
Cb=400pF
Note 5, 8
120
ns
TfCL
Cb=100pF
Note 5, 8
25
ns
TfCL
Cb=400pF
Note 5, 8
50
ns
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STE2001
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
TfDA
Cb=100pF
25
ns
TfDA
Cb=400pF
120
ns
Cb
Capacitive load for SDAH and
SCLH
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
100
note 5
T SW
400
pF
400
pF
10
ns
PARALLEL INTERFACE
TCY(EN)
Enable Cycle Time
VDD = 4.5V; Write
125
ns
TW(EN)
Enable Pulse width
VDD = 4.5V; Write
60
ns
TSU(A)
Address Set-up Time
VDD = 4.5V; Write
30
ns
TH(A)
Address Hold Time
VDD = 4.5V; Write
50
ns
TSU(D)
Data Set-Up Time
VDD = 4.5V; Write
30
ns
TH(D)
Data Hold Time
VDD = 4.5V; Write
50
ns
SERIAL INTERFACE
FSCLK
Clock Frequency
VDD = 4.5V
8
MHz
VDD1 = 1.8V
5
MHz
Clock Cycle SCLK
VDD = 4.5V
125
ns
TPWH1
SCLK pulse width HIGH
VDD = 4.5V
70
ns
TPWL1
SCLK Pulse width LOW
VDD = 4.5V
70
ns
TCYC
TS2
SCE setup time
50
ns
TH2
SCE hold time
50
ns
SCE minimum high time
60
ns
60
ns
TPWH2
TH5
SCE start hold time
TS3
SD/C setup time
60
ns
TH3
SD/C hold time
40
ns
TS4
SDIN setup time
40
ns
TH4
SDIN hold time
40
ns
Note 8
f osc
Notes: 1. F frame = ---------520
2. RES may be LOW or HIGH before VDD1 goes HIGH.
3. If T w(RES) is longer than 500ns (typical) a reset may be generated.
4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V IL and VIH with
an input voltage swing of VSS to VDD
5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification.
6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with T SW
7. Cb is the capacitive load for each bus line.
8. T H5 is the time from the previous SCLK positive edge to the negative edge of SCE
9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
10.C VLCD is the filterin g capacitor on VLCDOUT
11.If T w(RES) is shorter than max. value a reset pulse is rejected.
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STE2001
CIRCUIT DESCRIPTION
Supplies Voltages and Grounds
VDD2 and VDD3 are supply voltages to the internal voltage generator (see below). They must be externally connected.
If the internal voltage generator is not used, these should be connected to VDD1 pad. VDD1 supplies the rest of the IC.
This supply voltage could be different form VDD2 and VDD3. VDD1 must be lower than VDD2,3 + 0.5V.
Internal Supply Voltage Generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply voltage generation. The multiplyin g factor can be programmed to be: X5; X4; X3; X2, using the ’set CP Multiplica tion’
Command. The output voltage (VLCDOUT) is tightly controlled through the VLCDSENSE pad. For this voltage, four different temperature coefficient s(TC, rate of change with temperature) can be programmed using the bits TC1 and TC0.
This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the V
LCDIN
and VLCDOUT pads must be connected together. An external supply could be connected to VLCDIN to supply the LCD
without using the internal generator. In such event the VLDCOUT and VLCDSENSE must be connected to GND and the
internal voltage generator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition).
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the Displa y System.
When used the OSC pad must be connectedto VDD1 pad. An external oscilla torcould be used and fed into the OSC pin.
Display Data RAM
The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to
Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal)
and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX = 0 and V = 0), having the column with address X = 0 located on the left of the memory map.
The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer is modified to jump to next row. X restarts from X = 0 (Fig.2).
• Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map.
The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next column and Y restarting from Y = 0. (Fig. 3).
• Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory
map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer
is modified to jump to next row. X restarts from X = 0 (fig. 4).
• Mirrored Vertical (MX =1 and V = 1), having the column with address X = 0 located on the right of the memory map.
The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to
jump to next column and Y restarting from Y = 0. (Fig. 5).
After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y) = (0;0). Data
bytes in the memory could have the MSB either on top (D0 = 0, Fig. 6) or on the bottom (D0 = 1, Fig. 7).
Mux 65 Mode
The STE2001 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis
is enabled setting to a logic one the MY bit. This function is achieve d reading the matrix from physical row 63 to 0,
since the relation between the physical memory rows and the output row drivers is only dependent on the memory
reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn’t affect the content of
the memory map. It is only related to the visualizatio nprocess (Fig. 8 & Fig. 9).
It is also possible to modify the why with which row drivers are connected with DDRAM memory. A flip along y-axis of
each sub-block can be applied on both the Row Pads located on the Interface Side (the edge of the chip where the
Interface Pads are located), setting the TRS bit to a logic one, and on the Row Pads located on the other edge, setting
the BRS bit to a logic one.
Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic
data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
7/36
STE2001
Figure 2. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)
0
1
2
3
124
125
126
127
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
D00IN1138
Figure 3. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
1
2
3
124
125
126
127
0
1
2
3
4
5
6
7
8
D00IN1139
Figure 4. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)
127
126
125
124
3
2
1
0
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
D00IN1140
Figure 5. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)
127
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
126
125
124
3
0
1
2
3
4
5
6
7
8
D00IN1141
8/36
2
1
0
STE2001
Figure 6. Data RAM Byte organization with D0 = 0
MSB
0
1
2
3
124
125
126
127
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
LSB
D00IN1142
Figure 7. Data RAM Byte organization with D0 = 1
LSB
0
1
2
3
124
125
126
127
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
MSB
D00IN1143
Figure 8. Output drivers rows and physical memory rows correspondence with MY =0
ROW DRIVER PHYSICAL MEMORY ROW
0
0
1
2
3
4
5
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
R 60
R 61
R 62
R 63
R 64
ROW 60
ROW 61
ROW 62
ROW 63
ROW 64
R
R
R
R
R
R
1
2
3
124
125
126
127
D00IN1144
Figure 9. Output drivers rows and physical memory rows correspondence with MY =1
ROW DRIVER
PHYSICAL MEMORY ROW
0
R 63
R 62
R 61
R 60
R 59
R 58
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
R3
R2
R1
R0
R 64
ROW 60
ROW 61
ROW 62
ROW 63
ROW 64
1
2
3
124
125
126
127
D00IN1145
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STE2001
MUX 33 Mode
When using the 1:33 MUX ratio (MUX bit Set), the memory map is changed so that the only ”active” row drivers
are the ones related to Bank4 to Bank7.
When writing data RAM, as for Mux 65, four addressing mode are provided. The memory matrix is written as in
mux 65 mode so the user must take care of updating X and Y pointers to fill the memory matrix in the correct
way.
In MUX 33 mode only the MUX 33 memory logic matrix is read. The MY bit control the reading process. If MY
is set to a logic zero the row reading sequence is 0-1-2..........33 (fig.11). If MY is set to a logic one the reading
sequence is 32....1-33 (Fig 12).
The icon row (BANK8) is always the last being output either MY bit is a logic one or zero.
The functions related to bit TRS is the same as in MUX 65 mode.
In fig. 11 is shown the output drivers pad connection for MUX 33 mode. Note that the unused BANK 0-3 row
drivers become columns drivers.
If a 33x128 LCD matrix is driven, the output row drivers R0-R15 and R32-R47 must be floating.
Figure 10. Physical 65x128 memory matrix and 33x128 correspondence
0 1
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
14 15 16 17 18
109 110 111 112 113
126 127
NOT USED
C120
C121
C122
C123
C124
C125
C126
C127
C0
C1
C2
C3
C4
C5
C6
C7
D00IN1146
R16-R23
R24-R31
R48-R55
R56-R63
R64
D00IN1147
10/36
STE2001
Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0
ROW DRIVER
MUX 33 PHYSICAL MEMORY ROW
0 1
R16
to
R23
R24
to
R31
R48
to
R55
R56
to
R63
Row 0
to
Row 7
Row 8
to
Row15
Row 16
to
Row 23
Row 24
to
Row 31
R64
Row 32
2 3
4 5
6 7
120 121 122 123 124 125 126 127
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
D00IN1148
Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1
ROW DRIVER
MUX 33 PHYSICAL MEMORY ROW
0 1
R16
to
R23
R24
to
R31
R48
to
R55
R56
to
R63
Row 0
to
Row 7
Row 8
to
Row15
Row 16
to
Row 23
Row 24
to
Row 31
R64
Row 32
2 3
4 5
6 7
120 121 122 123 124 125 126 127
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
D00IN1148
Instruction Set
Two different instructions formats are provided:
- With D/C set to LOW
commands are sent to the Control circuitry.
- With D/C set to HIGH
the Data RAM is addressed Instructions have the syntax summarized in Table.1.
Reset (RES)
At power-on, all internal registers and RAM content are not defined. A Reset pulse must be applied on RES pad
(active low) to initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with
the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode.
The Default configurations is:
- Horizontal addressing (V = 0)
- Normal instruction set (H = 0)
- Normal display (MX = MY = TRS =BRS = 0)
- MUX 65 mode (MUX = 0)
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STE2001
- Display blank (E = D = 0)
- Address counter X[6: 0] = 0 and Y[3 : 0] = 0
- Temperature coefficient (TC[1 : 0] = 0)
- Bias system (BS[2 : 0] = 0)
- VOP = 0
- Power Down (PD = 1)
To clear the RAM content a MEMORY BLANK instruction should be executed.
Power Down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are OFF
(VLCDOUT output is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal Oscillator is in
off state. An external clock can be provided. The RAM contents is not cleared.
Charge Pump Factor
The desired Charge Pump Multiplication Factor can be programmed though the S1 and S0 bits, as follows:
S1
S0
Multiplication Factor
0
0
2X
0
1
3X
1
0
4X
1
1
5X
At Reset the X2 factor is selected.
Bias Levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to
be (Fig. 14):
n+3
n+2
2
1
V LCD , ------------- VLCD , ------------- VLCD , ------------- VL CD , ------------- V LCD ,V SS
n+4
n+4
n+4
n+4
Figure 13. Bias level Generator
R
VLCD
n+3
·VLCD
n+4
R
n+2
·VLCD
n+4
nR
2
·VLCD
n+4
R
1
·VLCD
n+4
R
VSS
12/36
D00IN1150
STE2001
thus providing an 1/(n+4) ratio, with n calculated from:
n=
m–3
For m = 65, n = 5 and an 1/9 ratio is set.
For m = 33, n =3 and an 1/7 ratio is set.
The STE2001 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:
BS2
BS1
BS0
n
0
0
0
7
0
0
1
6
0
1
0
5
0
1
1
4
1
0
0
3
1
0
1
2
1
1
0
1
1
1
1
0
The following table Bias Level for m = 65 and m = 33 are provided:
Symbol
m = 65 (1/9)
m = 33 (1/7)
V1
V LCD
VLCD
V2
8/9*VLCD
6/7* VLCD
V3
7/9*VLCD
5/7* VLCD
V4
2/9*V VLCD
2/7* VLCD
V5
1/9 *VLCD
1/7* VLCD
V6
VSS
VSS
LCD Voltage Generation
The LCD Voltage at reference temperature (To = 35°C) can be set using the VOP register content according to
the following formula:
VLCD(T=To) = VLCDo = (Ai+VOP · B)
(i=0,1)
with the following values:
Symbol
Value
Unit
Note
Ao
2.90
V
PRS = 0
A1
6.91
V
PRS = 1
B
0.034
V
To
35
°C
Note that the two PRS value produces two adjacent ranges for VLCD. If the register and PRS bit are set to zero
13/36
STE2001
the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing
Rate. A general expression for this is:
For MUX Rate m = 65 the ideal VLCD is:
1+ m
V LCD = ------------------------------------⋅ Vth
1
2 ⋅  1 – ---------
m
VLCD(to) = 6.85 · Vth
than:
( 6.85 ⋅ Vth – Ai )
V o p = ----------------------------------------0.03
Temperature Coefficient
As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there’s the need
to vary the LCD Voltage with temperature. The STE2001 provides the possibility to change the VLCD in a linear
fashion against temperature with four different Temperature Coefficient selectable through the TC0 and TC1
bits.
TC1
TC0
Value
Unit
0
0
-550
PPM/°C
0
1
-1350
PPM/°C
1
0
-1650
PPM/°C
1
1
-2650
PPM/°C
Figure 14. VLCD Slopes Cross Point with Different TC
VLCD
D01IN1256/mod
14/36
35ºC
TEMP
STE2001
Figure 15.
VLCD
B
A1
A0+B
A0
00h 01h 02h 03h 04h 05h
7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h
PRS=0
7Ch 7Dh 7Eh 7Fh
VO
D01IN1257
PRS=1
Finally, the VLCD voltage at a given (T) temperature can be calculated as:
VLCD(T) = VLCDo · [1 + (T-To) · TC]
Memory Blanking Procedure
This instruction allows to fill the memory with ”blank” patterns, in order to delete patterns randomly generated
in memory when starting up the device. This instruction substitutes (128X9) single ”write” instructions. It is possible to program ”Memory Blanking Procedure” only under the following conditions:
- X address = 0
- Y address = 0
- V bit
=0
- PD bit
=0
- MX bit
=0
The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is running). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be programmed for a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking
procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel
interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I2C interface).
Checker Board Procedure
This instruction allows to fill the memory with ”checker-board” pattern. It is mainly intended to developers, who
can now simply obtain complex module test configuration by means of a single instruction. It is possible to program ”Checker Board Procedure” only under the following conditions:
- X address = 0
- Y address = 0
- V bit
=0
- PD bit
=0
- MX bit
=0
15/36
STE2001
The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running.
Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for
a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure
will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last
SCLK rising edge for the Serial interface, last SCL rising edge for the I2C interface).
Scroll
The STE2001 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing
the correspondence between the rows of the logical memory map and the output row drivers. The scroll function
doesn’t affect the data ram content. It is only related to the visualization process. The information output on the
drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on).
Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every
scrolling command the offset between the memory address and the memory scanning pointer is increased or
decreased by one. The offset range is between 0 to 63 in mux 65 mode and 0-31 in mux 33 mode. After the
64th scrolling command in mux 65 mode and after the 32th in mux 33 mode, the offset between the memory
address and the memory scanning pointer is again zero (Cyclic Scrolling). Bank8 is always accessed last in
each frame, and so isn’t scrolled.
If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If
the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up.
Bus Interfaces
To provide the widest flexibility and ease of use the STE2001 features three different methods for interfacing
the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic
LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be
connected to GND. If I/O pins voltage is lower than VDD interfaces could sink more current than expected.
All interfaces are working while the STE2001 is in Power Down.
SEL2
SEL1
Interface
Note
0
0
I2C
0
1
Serial
Write only
1
1
Parallel
Write only
1
0
Not Used
Read and Write; Fast and
High Speed Mode
I2C Interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and
High Speed Mode (3.4MHz).
This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data
signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive
supply voltage via an active or passive pull-up.
The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line
while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the
START condition.
16/36
STE2001
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High,
defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable
for the duration of the High period of the clock signal. The data on the line may be changed during the Low period
of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data
bytes transferred between the start and the stop conditions is not limited. The information is transmitted bytewide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called ”transmitter”, the receiving device that gets the signals
is called ”receiver”. The device that controls the message is called ”master”. The devices that are controlled by
the master are called ”slaves”
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level
put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a
master receiver must generate an acknowledge after the reception of each byte that has been clocked out of
the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge
clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an endof-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP
condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass
(COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system
SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin
Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2001 will not be able
to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid
LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2001 is able to detect the special sequence
”S00001xxx”. After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without
detecting the master code.
Figure 16. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
D00IN1151
STOP
CONDITION
17/36
STE2001
Figure 17. Acknowledgment on theI2C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
8
MSB
9
LSB
DATA OUTPUT
BY RECEIVER
D00IN1152
Figure 18. I2C-bus timings
Sr
Sr P
tfDA
trDA
SDAH
tHD;DAT
tSU;STA
tSU;DAT
t HD;STA
SCLH
tfCL
trCL
trCL1
trCL1
(1)
tHIGH tLOW
RES
(1)
tLOW tHIGH
tSTART
= MCS current source pull-up
= Rp resistor pull-up
D00IN1153
Communication Protocol
The STE2001 is an I2C slave. The access to the device is bi-directional since data write and status read are allowed.
Two are the devic e addresses availabl e for the device. Both have in common the first 6 bits (011110). The least significa nt bit of the slave address is set by connecting the SA0 input to a logic 0 or to a logic 1.
To start the communication between the bus master and the slav e LCD driver, the master must initiate a START condition. Followin g this, the master sends an 8-bit byte, shown in Fig. 18, on the SDA bus line (Most signif icant bit first).
This consists of the 7-bit Device select Code, and the 1-bit Read/Write Designator (R/W).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the2IC-bus transfer.
Writing Mode.
If the R/W bit is set to logic 0 the STE2001 is set to be a receiver. After the slaves acknowledge one or more
command word follows to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values,
the second is a data byte (fig 18). The Co bit is the command MSB and defines if after this command will follow
one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0
Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/
C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following
data byte will be stored in the data RAM at the location specified by the data pointer.
E very byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2001 Display
RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every
byte written and in the end points to the last RAM location written.
Every byte must be acknowledged by all addressed units.
Reading Mode.
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent
during the last write access, is set to a logic 0, the byte read is the status byte.
18/36
STE2001
Figure 19. communication protocol
WRITE MODE
STE2001 ACK
STE2001 ACK
S
S 0 1 1 1 1 0 A 0 A 1 DC Control Byte A
0
R/W Co
SLAVE ADDRESS
STE2001 ACK
DATA Byte
A 0 DC Control Byte A
Co
COMMAND WORD
STE2001 ACK
LAST
CONTROL BYTE
STE2001 ACK
DATA Byte
A P
N> 0 BYTE
MSB........LSB
READ MODE
STE2001 ACK
MASTER
S
S 0 1 1 1 1 0 A 1 A
0
P
R/W
D01IN1247
S R
0 1 1 1 1 0 A /
0 W
STE2001
SLAVE ADDRESS
C D 0 0 0 0 0 0 A
o C
CONTROL BYTE
SERIAL INTERFACE
The STE2001 serial Interface is a unidirectional link between the display driver and the application supervisor.
It consists of four lines: one for data signals (SDIN), one for clock signals (SCLK), one for the peripheral enable
(SCE) and one for mode selection (SD/C).
The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral
power consumption is zero.
The STE2001 is always a slave on the bus and receive the communication clock on the SCLK pin from the master. The STE2001 is only able to receive data.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.
While SCE pin is high the serial interface is kept in reset.
SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the
eighth SCLK clock pulse during every byte transfer.
If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte
at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
19/36
STE2001
Figure 20. Serial bus protocol - one byte transmission
SCE
D/C
SCLK
SDIN
MSB
LSB
D00IN1159
Figure 21. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
Figure 22. RESET effect on the serial interface
tS2
tH2
tPWH2
SCE
tH5
tS3
tH3
t(H5)
D/C
tCYC
tPWL1
tWH1
tS2
SCLK
tS4
tH4
SDIN
RES
20/36
tSTART
D00IN1161
STE2001
Parallel Interface
The STE2001 parallel Interface is a unidirectional link between the display driver and the application supervisor.
It consists of ten lines: eight data lines (from DB7 to DB0) and two control lines. The control lines are: enable
(E) for data latch and PD/C for mode selection.
The data lines and the control line values are internally latched on E rising edge (fig. 23).
Figure 23. Parallel interface timing
PD/C
tW(en)
tSU(A)
th(A)
E
tSU(D) tHO(D)
tCY(en)
DB0-DB7
RES
tSTART
D00IN1162
Table 1. Instruction Set
Instruction
D/C R/W
Description
B7
B6
B5
B4
B3
B2
B1
B0
H=0 or H=1
NOP
0
0
0
0
0
0
0
0
0
0
No Operation
Function Set
0
0
0
0
1
MX
MY
PD
V
H
Power Down Management; Entry
Mode; Extended Instruction Set
Read Status Byte
0
1
PD
D
E
MX
MY
DO
( I2C interface only )
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data to RAM
Memory Blank
0
0
0
0
0
0
0
0
0
1
Starts Memory Blank Procedure
Scroll
0
0
0
0
0
0
0
0
1
DIR
Scrolls by one Row UP or DOWN
VLCD Range Setting
0
0
0
0
0
0
0
1
0
PRS VLDC programming range selection
Display Control
0
0
0
0
0
0
1
D
0
E
Select Display Configuration
Set CP Factor
0
0
0
0
0
1
0
0
S1
S0
Charge Pump Multiplication Factor
Set RAM Y
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set Horizontal (Y) RAM Address
Set RAM X
0
0
1
X6
X5
X4
X3
X2
X1
X0
Set Vertical (X) RAM Address
TRS BRS
H=0
H=1
Checker Board
0
0
0
0
0
0
0
0
0
1
Starts Checker Board Procedure
Multiplex Select
0
0
0
0
0
0
0
0
1
MUX
Selects MUX factor
TC Select
0
0
0
0
0
0
0
1
Output Address
0
0
0
0
0
0
1
DO
Bias Ratios
0
0
0
0
0
1
0
BS2 BS1 BS0
Reserved
0
0
0
1
X
X
X
Set VOP
0
0
1
X
TC1 TC0 Set Temperature Coefficient for VLDC
TRS BRS
X
X
OP6 OP5 OP4 OP3 OP2 OP1 OP0
Set Row Order on Output Pads
Set desired Bias Ratios
Not to be used
VOP register Write instruction
21/36
STE2001
Table 2. Explanations of Table 6 symbols
RESET
STATE
BIT
0
1
DIR
Scroll by one down
Scroll by one up
H
Use basic instruction set
Use extended instruction set
0
PD
Device fully working
Device in power down
1
V
Horizontal addressing
Vertical addressing
0
MX
Normal X axis addressing
X axis address is mirrored.
0
MY
Image is displayed not vertically mirrored
Image is displayed vertically mirrored
0
TRS
No top rows mirroring
Top rows mirroring (row pads 16-31 & 48-64)
0
BRS
No bottom rows mirroring
Bottom rows mirroring (row pads 0-15 & 32-47)
0
DO
MSB on TOP
MSB on BOTTOM
0
PRS
VLCD = 2.94V
V LCD = 6.75V
0
MUX
1:65 multiplexing ratio
1:33 multiplexing ratio
0
Table 3.
D
E
DESCRIPTION
RESET STATE
0
0
display blank
1
0
normal mode
D=0
0
1
all display segments on
E=0
1
1
inverse video mode
Table 4.
S1
S0
DESCRIPTION
0
0
Multiplication Factor 2X
0
1
Multiplication Factor 3X
1
0
Multiplication Factor 4X
1
1
Multiplication Factor 5X
RESET STATE
0
Table 5.
TC1
TC0
0
0
VLCD temperature Coefficient 0
0
1
VLCD temperature Coefficient 1
1
0
VLCD temperature Coefficient 2
1
1
VLCD temperature Coefficient 3
22/36
DESCRIPTION
RESET STATE
00
STE2001
Table 6.
BS2
BS1
BS0
DESCRIPTION
0
0
0
Bias Ratio equal to 7
0
0
1
Bias Ratio equal to 6
0
1
0
Bias Ratio equal to 5
0
1
1
Bias Ratio equal to 4
1
0
0
Bias Ratio equal to 3
1
0
1
Bias Ratio equal to 2
1
1
0
Bias Ratio equal to 1
1
1
1
Bias Ratio equal to 0
RESET STATE
000
Figure 24. Application Schematic Using an External LCD Voltage Generator
I/O
VDD2,3
VDD
32
VDD1
100nF
VSS
VSS2
128
65 x 128
DISPLAY
VSS1
1µF
VLCDSENSE
33
VLCDOUT
VLCD
VLCDIN
D00IN1157
Figure 25. Application Schematic using the Internal LCD Voltage Generator and two separate supplies
I/O
VDD2
VDD2,3
VDD1
100nF
VSS
VDD1
32
100nF
VSS2
128
65 x 128
DISPLAY
VSS1
1µF
VLCDSENSE
33
VLCDOUT
VLCDIN
D00IN1158
23/36
STE2001
Figure 26. Application Schematic using the Internal LCD Voltage Generator and a single supply
I/O
VDD
32
VDD2,3
VDD1
100nF
VSS
128
VSS2
65 x 128
DISPLAY
VSS1
1µF
33
VLCDSENSE
VLCDOUT
VLCDIN
D00IN1156
Figure 27. Pad Configuration with I2C interface
TEST_13
TEST_12
TEST_11
TEST_10
TEST_8
VSS2
VSS1
STE2001
TEST 9
SA0
SCL
SDAIN
SDAOUT
RES
GND
VDD1/GND/VSSOUT
µP
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
VDD1
SCLK
SCE
SD/C
SDIN
BSY_FLG
TEST_7
TEST_6
TEST_5
TEST_4
VDD3
VDD2
VDD1
OSCIN
SEL1
SEL2
GND/VSSOUT
VSSOUT
TEST_3
TEST_2
TEST_1
TEST_0
D01IN1261
24/36
STE2001
Figure 28. Pad Configuration with Parallel interface
TEST_13
TEST_12
TEST_11
TEST_10
TEST_8
VSS2
VSS1
TEST 9
SA0
SCL
SDAIN
SDAOUT
STE2001
GND
VDD1/GND/VSSOUT
VDD1
µP
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
SCLK
SCE
SD/C
SDIN
VDD1
BSY_FLG
TEST_7
TEST_6
TEST_5
TEST_4
VDD3
VDD2
VDD1
OSC
SEL1
SEL2
GND/VSSOUT
VDD1
VSSOUT
TEST_3
TEST_2
TEST_1
TEST_0
D01IN1262
Figure 29. Pad Configuration with Serial interface
TEST_13
TEST_12
TEST_11
TEST_10
TEST_8
VSS2
VSS1
TEST 9
SA0
SCL
SDAIN
SDAOUT
GND
VDD1/GND/VSSOUT
VDD1
µP
STE2001
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
VDD1
SCLK
SCE
SD/C
SDIN
BSY_FLG
TEST_7
TEST_6
TEST_5
TEST_4
VDD3
VDD2
VDD1
OSCIN
SEL1
SEL2
VDD1
GND/VSSOUT
VSSOUT
TEST_3
TEST_2
TEST_1
TEST_0
D01IN1263
25/36
STE2001
Figure 30. Power OFF Timing Diagram
VDD2/3
tVDD
VDD1
RES
INPUTS
D01IN1264
Figure 31. Power OFF Sequence
POWER OFF SEQUENCE
SET by Software (PD=0) or (Vop=0 & PRS=[0;0])
Force Active Input Lines Low
REMOVE VDD1
REMOVE VDD2/3
END OF POWER OFF SEQUENCE
D01IN1265
26/36
STE2001
Figure 32. Power-Up & RESET timing diagram
VDD2/3
tVDD
VDD1
tW(RES)
RES
INPUTS
D01IN1189
Figure 33. Power-Up & RESET timing diagram
VDD2/3
t
tVDD VHRL
VDD1
tW(RES)
RES
INPUTS
D01IN1190
Figure 34. Power Up Sequence
POWER UP SEQUENCE
Set Active Input lines low
Apply VDD2/3
Apply VDD1
Apply a RESET Pulse
END OF POWER UP SEQUENCE
(STE2001 in Reset State)
D01IN1266
27/36
STE2001
Figure 35. Chip Mechanical Drawing
ROW 0
ALIGNEMENT MARK
ROW 16
STE2001
ROW 15
ALIGNEMENT MARK
ROW 31
COL 0
TEST
VLCDIN
VLCDSENSE
VLCDOUT
VSS2
VSS1
TEST
SA0
SCL
SDAIN
SDAOUT
RES
COL 63
(0,0)
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
Y
COL 64
X
SCLK
SCE
SD/C
SDIN
BSY_FLG
TEST
VDD2
VDD3
VDD1
OSC
SEL1
SEL2
VSSOUT
TEST
COL 127
ROW 47
ROW 32
ALIGNEMENT MARK
ALIGNEMENT MARK
ROW 64
ROW 48
D01IN1191
28/36
STE2001
Figure 36. Improved ALTH & PLESKO Driving Method
VLCD
V2
V3
∆V1(t)
∆V2(t)
ROW 0
R0 (t)
V4
V5
VSS
VLCD
V2
V3
ROW 1
R1 (t)
V4
V5
VSS
VLCD
V2
V3
COL 0
C0 (t)
V4
V5
VSS
VLCD
V2
V3
COL 1
C1 (t)
V4
V5
VSS
VLCD - VSS
V3 - VSS
Vstate1(t)
VLCD - V2
0V
V3 - VSS
V4 - V5
0V
VSS - V5
V4 - VLCD
VSS - VLCD
VLCD - VSS
V3 - VSS
Vstate2(t)
VLCD - V2
0V
V3 - VSS
V4 - V5
0V
VSS - V5
V4 - VLCD
VSS - VLCD
..... 64 0 1 2 3 4 5 6 7 8 9 .......
0 1 2 3 4 5 6 7 8 9 .......
FRAME n
∆V1(t) = C1(t) - R0(t)
∆V2(t) = C1(t) - R1(t)
..... 64
FRAME n + 1
D00IN1154
29/36
STE2001
Figure 37. DATA RAM to display Mapping
DISPLAY DATA RAM
GLASS
TOP VIEW
bank
0
bank
1
DISPLAY DATA RAM = ”1”
DISPLAY DATA RAM = ”0”
bank
2
LCD
bank
3
bank
7
bank
8
ICOR ROW
D00IN1155
Table 7. Test Pin Configuration
30/36
Test Numb.
Pin
TEST_0
TEST_1
TEST_2
TEST_3
GND
GND
GND
GND
TEST_4
TEST_5
TEST_6
TEST_7
OPEN
OPEN
OPEN
OPEN
T8
T9
OPEN
OPEN
TEST_10
TEST_11
TEST_12
TEST_13
OPEN
OPEN
OPEN
OPEN
STE2001
Table 8. Mechanical Dimensions
Table 9. Pad Coordinates (continued)
2.12mmX12.5mm
NAME
PAD
X (µm)
Y(µm)
Pad Pitch
70 µm
C13
30
-3,681.8
-898.2
Pad Size
62µm X 100 µm
C14
31
-3,611.8
-898.2
C15
32
-3,541.8
-898.2
C16
33
-3,471.8
-898.2
C17
34
-3,401.8
-898.2
C18
35
-3,331.8
-898.2
C19
36
-3,261.8
-898.2
C20
37
-3,191.8
-898.2
C21
38
-3,121.8
-898.2
C22
39
-3,051.8
-898.2
C23
40
-2,981.8
-898.2
C24
41
-2,911.8
-898.2
C25
42
-2,841.8
-898.2
C26
43
-2,771.8
-898.2
C27
44
-2,701.8
-898.2
C28
45
-2,631.8
-898.2
C29
46
-2,561.8
-898.2
C30
47
-2,491.8
-898.2
C31
48
-2,421.8
-898.2
C32
49
-2,351.8
-898.2
C33
50
-2,281.8
-898.2
C34
51
-2,211.8
-898.2
C35
52
-2,141.8
-898.2
C36
53
-2,071.8
-898.2
C37
54
-2,001.8
-898.2
C38
55
-1,931.8
-898.2
C39
56
-1,861.8
-898.2
C40
57
-1,791.8
-898.2
C41
58
-1,721.8
-898.2
C42
59
-1,651.8
-898.2
C43
60
-1,581.8
-898.2
C44
61
-1,511.8
-898.2
C45
62
-1,441.8
-898.2
C46
63
-1,371.8
-898.2
C47
64
-1,301.8
-898.2
C48
65
-1,231.8
-898.2
C49
66
-1,161.8
-898.2
Die Size
Bump Dimensions
50µmX88µmX17.5
WFS Thickness
500µm
Table 9. Pad Coordinates
NAME
PAD
X (µm)
Y(µm)
R0
1
-5,994
-898.2
R1
2
-5,924
-898.2
R2
3
-5,854
-898.2
R3
4
-5,784
-898.2
R4
5
-5,714
-898.2
R5
6
-5,644
-898.2
R6
7
-5,574
-898.2
R7
8
-5,504
-898.2
R8
9
-5,434
-898.2
R9
10
-5,364
-898.2
R10
11
-5,294
-898.2
R11
12
-5,224
-898.2
R12
13
-5,154
-898.2
R13
14
-5,084
-898.2
R14
15
-5,014
-898.2
R15
16
-4,944
-898.2
C0
17
-4,591.8
-898.2
C1
18
-4,521.8
-898.2
C2
19
-4,451.8
-898.2
C3
20
-4,381.8
-898.2
C4
21
-4,311.8
-898.2
C5
22
-4,241.8
-898.2
C6
23
-4,171.8
-898.2
C7
24
-4,101.8
-898.2
C8
25
-4,031.8
-898.2
C9
26
-3,961.8
-898.2
C10
27
-3,891.8
-898.2
C11
28
-3,821.8
-898.2
C12
29
-3,751.8
-898.2
31/36
STE2001
Table 9. Pad Coordinates (continued)
Table 9. Pad Coordinates (continued)
NAME
PAD
X (µm)
Y(µm)
NAME
PAD
X (µm)
Y(µm)
C50
67
-1,091.8
-898.2
C87
104
1,785.44
-898.2
C51
68
-1,021.8
-898.2
C88
105
1,855.44
-898.2
C52
69
-951.8
-898.2
C89
106
1,925.44
-898.2
C53
70
-881.8
-898.2
C90
107
1,995.44
-898.2
C54
71
-811.8
-898.2
C91
108
2,065.44
-898.2
C55
72
-741.8
-898.2
C92
109
2,135.44
-898.2
C56
73
-671.8
-898.2
C93
110
2,205.44
-898.2
C57
74
-601.8
-898.2
C94
111
2,275.44
-898.2
C58
75
-531.8
-898.2
C95
112
2,345.44
-898.2
C59
76
-461.8
-898.2
C96
113
2,415.44
-898.2
C60
77
-391.8
-898.2
C97
114
2,485.44
-898.2
C61
78
-321.8
-898.2
C98
115
2,555.44
-898.2
C62
79
-251.8
-898.2
C99
116
2,625.44
-898.2
C63
80
-181.8
-898.2
C100
117
2,695.44
-898.2
C64
81
175.44
-898.2
C101
118
2,765.44
-898.2
C65
82
245.44
-898.2
C102
119
2,835.44
-898.2
C66
83
315.44
-898.2
C103
120
2,905.44
-898.2
C67
84
385.44
-898.2
C104
121
2,975.44
-898.2
C68
85
455.44
-898.2
C105
122
3,045.44
-898.2
C69
86
525.44
-898.2
C106
123
3,115.44
-898.2
C70
87
595.44
-898.2
C107
124
3,185.44
-898.2
C71
88
665.44
-898.2
C108
125
3,255.44
-898.2
C72
89
735.44
-898.2
C109
126
3,325.44
-898.2
C73
90
805.44
-898.2
C110
127
3,395.44
-898.2
C74
91
875.44
-898.2
C111
128
3,465.44
-898.2
C75
92
945.44
-898.2
C112
129
3,535.44
-898.2
C76
93
1,015.44
-898.2
C113
130
3,605.44
-898.2
C77
94
1,085.44
-898.2
C114
131
3,675.44
-898.2
C78
95
1,155.44
-898.2
C115
132
3,745.44
-898.2
C79
96
1,225.44
-898.2
C116
133
3,815.44
-898.2
C80
97
1,295.44
-898.2
C117
134
3,885.44
-898.2
C81
98
1,365.44
-898.2
C118
135
3,955.44
-898.2
C82
99
1,435.44
-898.2
C119
136
4,025.44
-898.2
C83
100
1,505.44
-898.2
C120
137
4,095.44
-898.2
C84
101
1,575.44
-898.2
C121
138
4,165.44
-898.2
C85
102
1,645.44
-898.2
C122
139
4,235.44
-898.2
C86
103
1,715.44
-898.2
C123
140
4,305.44
-898.2
32/36
STE2001
Table 9. Pad Coordinates (continued)
Table 9. Pad Coordinates (continued)
NAME
PAD
X (µm)
Y(µm)
NAME
PAD
X (µm)
Y(µm)
C124
141
4,375.44
-898.2
TEST_3
178
4,640.52
898.2
C125
142
4,445.44
-898.2
TEST_2
179
4,500.68
898.2
C126
143
4,515.44
-898.2
TEST_1
180
4,360.84
898.2
C127
144
4,585.44
-898.2
TEST_0
181
4,221
898.2
R47
145
4,943.84
-898.2
VSSOUT
182
4,151
898.2
R46
146
5,013.84
-898.2
SEL2
183
4,011.16
898.2
R45
147
5,083.84
-898.2
SEL1
184
3,871.32
898.2
R44
148
5,153.84
-898.2
OSC
185
3,731.48
898.2
R43
149
5,223.84
-898.2
VDD1_1
186
3,661.48
898.2
R42
150
5,293.84
-898.2
VDD1_2
187
3,591.48
898.2
R41
151
5,363.84
-898.2
VDD1_3
188
3,521.48
898.2
R40
152
5,433.84
-898.2
VDD1_4
189
3,451.48
898.2
R39
153
5,503.84
-898.2
VDD1_5
190
3,381.48
898.2
R38
154
5,573.84
-898.2
VDD1_6
191
3,311.48
898.2
R37
155
5,643.84
-898.2
VDD3_1
192
3,223.08
898.2
R36
156
5,713.84
-898.2
VDD3_2
193
3,153.08
898.2
R35
157
5,783.84
-898.2
VDD3_3
194
3,083.08
898.2
R34
158
5,853.84
-898.2
VDD2_1
195
2,994.68
898.2
R33
159
5,923.84
-898.2
VDD2_2
196
2,924.68
898.2
R32
160
5,993.84
-898.2
VDD2_3
197
2,854.68
898.2
R48
161
6,021.92
898.2
VDD2_4
198
2,784.68
898.2
R49
162
5,951.92
898.2
VDD2_5
199
2,714.68
898.2
R50
163
5,881.92
898.2
VDD2_6
200
2,644.68
898.2
R51
164
5,811.92
898.2
VDD2_7
201
2,574.68
898.2
R52
165
5,741.92
898.2
TEST_7
202
2,033.84
898.2
R53
166
5,671.92
898.2
TEST_6
203
1,894
898.2
R54
167
5,601.92
898.2
TEST_5
204
1,754.16
898.2
R55
168
5,531.92
898.2
TEST_4
205
1,614.32
898.2
R56
169
5,461.92
898.2
BSY_FLAG
206
1,474.48
898.2
R57
170
5,391.92
898.2
SDIN
207
1,333.2
898.2
R58
171
5,321.92
898.2
SD/C
208
1,193.36
898.2
R59
172
5,251.92
898.2
SCE
209
1,053.52
898.2
R60
173
5,181.92
898.2
SCLK
210
913.68
898.2
R61
174
5,111.92
898.2
D7
211
773.84
898.2
R62
175
5,041.92
898.2
D6
212
634
898.2
R63
176
4,971.92
898.2
D5
213
494.16
898.2
R64
177
4,901.92
898.2
D4
214
354.32
898.2
33/36
STE2001
Table 9. Pad Coordinates (continued)
Table 9. Pad Coordinates (continued)
NAME
PAD
X (µm)
Y(µm)
NAME
PAD
X (µm)
Y(µm)
D3
215
214.48
898.2
TEST_12
252
-4,460.48
898.2
D2
216
74.64
898.2
TEST_13
253
-4,540.48
898.2
D1
217
-65.2
898.2
TEST_10
254
-4,620.48
898.2
D0
218
-205.04
898.2
TEST_11
255
-4,700.48
898.2
PD/C
219
-344.88
898.2
TEST_8
256
-4,780.48
898.2
E
220
-484.72
898.2
R31
257
-4,971.92
898.2
RES
221
-624.56
898.2
R30
258
-5,041.92
898.2
SDA_OUT
222
-764.4
898.2
R29
259
-5,111.92
898.2
SDA_IN
223
-904.24
898.2
R28
260
-5,181.92
898.2
SCL
224
-1,044.08
898.2
R27
261
-5,251.92
898.2
SA0
225
-1,183.92
898.2
R26
262
-5,321.92
898.2
TEST9
226
-1,722.04
898.2
R25
263
-5,391.92
898.2
VSS1_1
227
-1,795.48
898.2
R24
264
-5,461.92
898.2
VSS1_2
228
-1,865.48
898.2
R23
265
-5,531.92
898.2
VSS1_3
229
-1,935.48
898.2
R22
266
-5,601.92
898.2
VSS1_4
230
-2,075.88
898.2
R21
267
-5,671.92
898.2
VSS1_5
231
-2,145.88
898.2
R20
268
-5,741.92
898.2
VSS1_6
232
-2,215.88
898.2
R19
269
-5,811.92
898.2
VSS2_1
233
-2,356.28
898.2
R18
270
-5,881.92
898.2
VSS2_2
234
-2,426.28
898.2
R17
271
-5,951.92
898.2
VSS2_3
235
-2,496.28
898.2
R16
272
-6,021.92
898.2
VSS2_4
236
-2,636.68
898.2
VSS2_5
237
-2,706.68
898.2
VSS2_6
238
-2,776.68
898.2
X
Y
MARKS
VLCDOUT1
239
-3,545.64
898.2
4806.2
901.8
mark1
VLCDOUT2
240
-3,615.64
898.2
-4876.2
901.8
mark2
VLCDOUT3
241
-3,685.64
898.2
-6092.6
-901.8
mark3
VLCDOUT4
242
-3,755.64
898.2
6092.6
-901.8
mark4
VLCDOUT5
243
-3,825.64
898.2
VLCDOUT6
244
-3,895.64
898.2
VLCSENSE
245
-3,968.08
898.2
VLCDIN_1
246
-4,040.48
898.2
VLCDIN_2
247
-4,110.48
898.2
VLCDIN_3
248
-4,180.48
898.2
VLCDIN_4
249
-4,250.48
898.2
VLCDIN_5
250
-4,320.48
898.2
VLCDIN_6
251
-4,390.48
898.2
34/36
Table 10. Alignment marks coordinates
Figure 38. Alignment marks dimensions
A
FLUOROWARE GmbH
+0.08
3.94 -0.13
DETAIL Y
13 x 3.19 = 41.47±0.25
4.60
2.18
+0.08
2.46 -0.10
10.75
50.6±0.25
B
B
SCHNITT A-A
DETAIL Y
MASSTAB 5:1
12.80
10º
+0.13
45.59 -0.25
STATPROT.150
2 x 14.59 = 29.18±0.25
0.3
A
SCHNITT B-B
DETAIL X
10º
DETAIL X
MASSTAB 5:1
D01IN1248
0.90
2.39
2.54 x 45?
1
1
TRAY OR WAFFLE PACK
OF STE2000/STE2001
MATERIAL: STATPRO150
BUILD TOOL TO 0.009 MM/MM SHRINK
KNOCKDUTS NOT TO EXCEED 0.08 PAD
ENGRAVING TO BE 20 CHAIR x 0.3 WIDE
x 0.05 RAISED CENTER ON CENTERLINE
NOTES:
45.90
STE2001
Figure 39.
DIE IDENTIFICATION
STE2001
R16
D01IN1249
Figure 40. Tray Information
35/36
STE2001
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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36/36