STMICROELECTRONICS STE2004S

STE2004S
102 x 65 single-chip LCD controller/driver
Features
Description
■
102 x 65 bits display data RAM
■
Programmable MUX rate
■
Programmable frame rate
■
X,Y programmable carriage return
■
Dual partial display mode
■
Row by row scrolling
The STE2004S is a low power CMOS LCD
controller driver. Designed to drive a 65 rows by
102 columns graphic display, it provides all
necessary functions in a single chip, including
on-chip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption.
■
N-line inversion
■
Automatic data RAM blanking procedure
■
Selectable input interface:
– I2C Bus Fast and Hs-mode (read and write)
– 8000 and 8080 Parallel Interfaces (read
and write)
– 3-lines and 4-lines SPI Interface (read and
write)
– 3-lines 9 bit Serial Interface (read and
write)
STE2004S features six standard interfaces
(3-lines Serial, 3-lines SPI, 4-lines SPI, 68000
Parallel, 8080 parallel and I2C) for interfacing with
the host micro-controller.
OSC_IN
FR_IN
FR_OUT
VSENSE SLAVE
VLCD
CMOS compatible inputs
■
Fully integrated oscillator requires no external
components
■
Designed for chip-on-glass (COG)
applications.
■
Low power consumption, suitable for battery
operated systems
■
Logic supply voltage range from 1.7 to 3.6V
■
High voltage generator supply voltage range
from 1.75 to 4.5V
■
Display supply voltage range from 4.5 to 14.5V
■
Backward compatibility with STE2001/2/4
January 2007
R0 to R64
COLUMN
DRIVERS
ROW
DRIVERS
DATA
LATCHES
SHIFT
REGISTER
CLOCK
HIGH VOLTAGE
GENERATOR
65 x 102
RAM
VLCDSENSE
Fully integrated configurable LCD bias voltage
generator with:
– Selectable multiplication factor (up to 5X)
– Effective sensing for high precision output
– Eight selectable temperature compensation
coefficients
■
MASTER
SLAVE SYNC
BIAS VOLTAGE
GENERATOR
RES
■
TIMING
GENERATOR
OSC
OSC_OUT
CO to C101
RESET
SCROLL
LOGIC
TEST
VSSAUX
VDD1,2
DATA
REGISTER
INSTRUCTION
REGISTER
VSS
DISPLAY
CONTROL
LOGIC
TEST_MODE
TEST_VREF
ICON_MODE
EXT
SEL 3
I2C BUS
9 Bit SERIAL
3 & 4 Line SPI
Parallel 8080
Parallel 68K
SEL 2
SEL 1
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD
to
DB7
Rev 3
D/C
CS
LR0047
1/7979
www.st.com
79
Contents
STE2004S
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
3.1
Supplies voltages and grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Internal supply voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
Master/slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5
Bias levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6
LCD voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.7
Temperature coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8
Display data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.1
4.2
4.3
5
2/79
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.1
4-lines SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2.2
3-lines SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2.3
3-lines 9 bits serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.1
68000-series parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3.2
8080-series parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1
Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2
Power down (PD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.3
Memory blanking procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.4
Checker board procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5
Scrolling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.6
Dual partial display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STE2004S
Contents
6
ID-number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.3
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8
Pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3/79
Block diagram
STE2004S
1
Block diagram
Figure 1.
STE2004S block diagram
OSC_IN
TIMING
GENERATOR
OSC
OSC_OUT
FR_IN
FR_OUT
MASTER
SLAVE SYNC
VLCD
COLUMN
DRIVERS
ROW
DRIVERS
DATA
LATCHES
SHIFT
REGISTER
HIGH VOLTAGE
GENERATOR
65 x 102
RAM
VLCDSENSE
RES
R0 to R64
CLOCK
BIAS VOLTAGE
GENERATOR
VSENSE SLAVE
CO to C101
RESET
SCROLL
LOGIC
TEST
VSSAUX
VDD1,2
DATA
REGISTER
INSTRUCTION
REGISTER
VSS
DISPLAY
CONTROL
LOGIC
TEST_MODE
TEST_VREF
ICON_MODE
EXT
SEL 3
I2C BUS
9 Bit SERIAL
3 & 4 Line SPI
Parallel 8080
Parallel 68K
SEL 2
SEL 1
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD
to
DB7
4/79
D/C
CS
LR0047
STE2004S
2
Pin description
Pin description
Table 1. Pin description
N°
Pad
Type
Function
R0 to R64
1-6
109-141
O
LCD row driver output
C0 to C101
6-107
O
LCD column driver output
VSS
192-203
GND
VDD1
156-163
Supply IC positive power supply
VDD2
164-171
Supply Internal generator supply voltages.
VLCD
205-209
Supply Voltage multiplier output
Ground pads.
Voltage multiplier regulation input. VLCDOUT sensing for output voltage fine
tuning
VLCDSENSE
204
Supply
VSENSE_SLAVE
145
Supply Voltage reference for slave charge pump
VSSAUX
190-177-147
O
Ground reference for pins configuration
VDD1AUX
142
O
VDD1 reference for pins configuration
Interface mode selection - cannot be left floating
SEL3
SEL2
SEL1
Interface
I2C
GND/VSSAUX GND/VSSAUX GND/VSSAUX
SEL1,2,3
152
153
154
GND/VSSAUX GND/VSSAUX
I
VDD1
SPI 4-Lines 8 bit
GND/VSSAUX
VDD1
GND/VSSAUX
SPI 3-Lines 8 bit
GND/VSSAUX
VDD1
VDD1
Serial 3-Lines 9 bit
VDD1
GND/VSSAUX GND/VSSAUX
Parallel 8080-series
VDD1
GND/VSSAUX
Parallel 68000-series
VDD1
Extended instruction set selection - cannot be left floating
EXT_SET
151
Ext pad config
Instruction set selected
GND or VSSAUX
BASIC
VDD1
EXTENDED
I
Extended instruction set selection - cannot be left floating
ICON_MODE
155
SDOUT
180
SDIN - SDAIN
179
I
Icon mode pad config
Icon mode status
GND or VSSAUX
DISBLED
VDD1
ENABLED
O
Serial and SPI data output - if unused must be left floating
I
SDIN - Serial and SPI interface data input - cannot be left floating
I
SDAIN - I2C bus data in - cannot be left floating
5/79
Pin description
STE2004S
Table 1. Pin description (continued)
N°
SCLK - SCL
Pad
Type
Function
I
SCLK - Serial and SPI interface clock - cannot be left floating
I
SCL - I2C bus clock - cannot be left floating
181
SDA_OUT
178
O
I2C Bus data out - if unused must be left floating
SA0
149
I
I2C slave address BIT 0 - cannot be left floating
SA1
148
I
I2C slave address BIT 1- cannot be left floating
182-189
I/O
DB0 to DB7
R/W - RD
Parallel interface 8 bit data bus - cannot be left floating
I
R/W - 68000 Series Parallel interface read and write control input
- cannot be left floating
I
RD - 8080 Series Parallel interface read enable clock input
- cannot be left floating
175
E / WR
176
I
E - 68000 Series Parallel interface read and write clock input
- cannot be left floating
E / WR
176
I
WR - 8080 Series Parallel interface - write enable clock input
- cannot be left floating
RES
172
I
Reset input. Active Low.
D/C
174
I
Interface data/command selector- cannot be left floating
CS
173
I
Serial and Parallel interfaces ENABLE. When Low the incoming data are
clocked In. Cannot be left floating
TEST_MODE
191
I
Test Pad - 50 kohm internal pull-down must be connected to VSS/VSSAUX
TEST_VREF
146
O
Test Pad - must be left floating
Oscillator Input:
OSCIN
144
OSC_IN
Configuration
High
Internal oscillator enabled
Low
Internal oscillator disabled
External Oscillator
Internal oscillator disabled
I
OSCOUT
210
O
Internal/external oscillator out - if unused must be left floating
FR_OUT
211
O
Master slave frame inversion synchronization - f unused must be left floating
FR_IN
143
I
Master slave frame inversion synchronization - cannot be left floating
Master/slave configuration bit:- cannot be left floating
M/S
6/79
100
I
M/S PIN
OSC_OUT
FR_OUT
FR_IN
Charge Pump
High
ENABLED
Enabled
Disabled
AuxVsense disabled
Low
ENABLED
Enabled
Enabled
Charge pump in slave
mode or ext power
STE2004S
Pin description
ROW 6
ROW 27
Chip mechanical drawing
MARK_1
ROW 5
ROW28
ROW31
ROW 0
COL 0
FR_OUT
OSC_OUT
MARK_3
STE2004S
VLCD
VLCDSENSE
VSS
TEST_MODE
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK - SCL
SDOUT
SDIN - SDAIN
SDAOUT
COL 50
VSSAUX
E - WR
(0,0)
R/W - RD
Y
COL 51
D/C
CS
X
RES
MARK_4
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
COL 101
ROW 32
ROW64/ICON
ROW63
ROW 37
ROW60
MARK_2
ROW 59
LR0048
ROW 38
Figure 2.
7/79
Pin description
STE2004S
Figure 3.
Improved ALTH and PLESKO driving method
VLCD
V2
V3
∆V1(t)
∆V2(t)
ROW 0
R0 (t)
V4
V5
VSS
VLCD
V2
V3
ROW 1
R1 (t)
V4
V5
VSS
VLCD
V2
V3
COL 0
C0 (t)
V4
V5
VSS
VLCD
V2
V3
COL 1
C1 (t)
V4
V5
VSS
VLCD - VSS
V3 - VSS
Vstate1(t)
V4 - V5
0V
VSS - V5
VLCD - V2
0V
V3 - VSS
V4 - VLCD
VSS - VLCD
VLCD - VSS
V3 - VSS
Vstate2(t)
VLCD - V2
0V
V3 - VSS
V4 - V5
0V
VSS - V5
V4 - VLCD
VSS - VLCD
..... 64 0 1 2 3 4 5 6 7 8 9 .......
0 1 2 3 4 5 6 7 8 9 .......
FRAME n
∆V1(t) = C1(t) - R0(t)
∆V2(t) = C1(t) - R1(t)
8/79
..... 64
FRAME n + 1
D00IN1154
STE2004S
Circuit description
3
Circuit description
3.1
Supplies voltages and grounds
VDD2 supplies voltages to the internal voltage generator (see below). If the internal voltage
generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the
IC. VDD1 supply voltage could be different form VDD2.
V
3.2
DD2
⋅ VLCD- + 200mV
≥2
-------------------------(n + 4)
Internal supply voltage generator
The IC has a fully integrated (no external capacitors required) charge pump for the liquid
crystal display (LCD) supply voltage generation. The multiplying factor can be programmed
to be: Auto, X5, X4, X3, X2, using the ’set CP multiplication’ command. If auto is set, the
multiplying factor is automatically selected to have the lowest current consumption in every
condition, allowing an input voltage that changes over time and a constant VLCD voltage.
The output voltage (VLCD) is tightly controlled through the VLCDSENSE pad. For this voltage,
eight different temperature coefficients (TC, rate of change with temperature) can be
programmed using the bits TC1, TC0, T2, T1, T0, to ensure there is no contrast degradation
over the LCD operating range.
An external supply could be connected to VLCD to supply the LCD without using the internal
generator. In such event the internal voltage generator must be programmed to zero (PRS =
[0;0], Vop = 0 - reset condition) and the charge pump (CP[0;0]) set to 5x or quto mode.
3.3
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock
for the display system. When used the OSC pad must be connected to VDD1 pad. An
external oscillator could be used and fed into the OSC pin. If an external oscillator is used, it
must be always present when STE2004S is not in power down mode. An oscillator out is
provided on the OSCOUT Pad to cascade two or more drivers.
3.4
Master/slave mode
STE2004S supports the master slave working mode for both control logic and charge pump.
This function allows to drive matrix such as 204x65 or 102x130 using two synchronized
STE2004S and the internal charge pump of both devices.
If M/S is connected to VDD1, the driver is configured to work in master mode. When
STE2004S is in master mode, the Vsense_Slave pin is disabled and the VLCD value can be
controlled using Vop bits. The master time generator outputs the relevant timing references
on FR_OUT and OSC_OUT.
If M/S is connected to GND, the driver is configured to work in slave mode. When
STE2004S is in slave mode, the VLCD configuration set by Vop registers and the thermal
compensation slope set by TC register, are neglected. The VLCD value generated is equal
to the voltage value present on the Vsense_Slave pin so the slave configuration can follow
9/79
Circuit description
STE2004S
the master configuration. The only recognized configuration is Vop=0 that forces the charge
pump to be in off state whatever is the value of Vsense_aux.
To synchronize the master and slave timing circuits, the slave driver FR_IN pad must be
connected to master driver FR_OUT pad, and slave driver OSC_IN pad must be connected
to the master driver OSC_OUT Pad (Figure 4.). This connection ensures a synchronization
at both frame level (R0 on the master is driven together with the Slave R0 driver) and at
oscillator level (same frame frequency on the master and on the slave). If the
synchronization at frame level is not required, FR_IN pin must be connected toVDD1 or to
VDD1_aux (Figure 5.).
During the power up procesure, the master device must be forced to exit from power down
before the slave device. To enter into PowerDown mode, the slave device must be forced
into power down state before master device.
Figure 4.
Master slave logic connection with frame synchronization
STE2004S
VDD1AUX
OSCIN FRIN
OSCOUT
STE2004S
FROUT
FRIN OSCIN
OSCOUT
FROUT
LR0219
Figure 5.
Master slave logic connection without frame synchronization
STE2004S
VDD1AUX
OSCIN FRIN
OSCOUT
STE2004S
OSCIN
FROUT
VDD1AUX
3.5
OSCOUT
FROUT
FRIN
LR0220
Bias levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are
generated. The ratios among these levels and VLCD, should be selected according to the
MUX ratio (m). They are established according to the following (Figure 6.)
V
10/79
n+3
n+2
2
1
, ------------- V
, ------------- V
, ------------- V
, ------------- V
,V
LCD n + 4 LCD n + 4 LCD n + 4 LCD n + 4 LCD SS
STE2004S
Circuit description
Figure 6.
Bias level generator
VLCD
R
n+3
·VLCD
n+4
R
n+2
·VLCD
n+4
nR
2
·VLCD
n+4
R
1
·VLCD
n+4
R
VSS
D00IN1150
providing an 1/(n+4) ratio, with n calculated from:
n=
m–3
For m = 65, n = 5, a 1/9 ratio is set.
For m = 49, n =4, a 1/8 ratio is set.
The STE2004S provides three bits (BS0, BS1, BS2) for programming the bias ratio as shown
below:
Table 2. Bias ratio programmable bits
BS2
BS1
BS0
n
0
0
0
7
0
0
1
6
0
1
0
5
0
1
1
4
1
0
0
3
1
0
1
2
1
1
0
1
1
1
1
0
The following table shows the bias level for m = 65 and m = 49:
11/79
Circuit description
STE2004S
Table 3. Bias level m=65 and m=49
3.6
Symbol
m = 65 (1/9)
m = 49 (1/8)
V1
VLCD
VLCD
V2
8/9*VLCD
7/8*VLCD
V3
7/9*VLCD
6/8*VLCD
V4
2/9*V VLCD
2/8*VLCD
V5
1/9 *VLCD
1/8*VLCD
V6
VSS
VSS
LCD voltage generation
The LCD voltage at reference temperature (To = 27°C) can be set using the VOP register content
according to the following formula:
VLCD(T=To) = VLCDo = (Ai+VOP · B)
(i=0,1,2)
with the following values:
Table 4. LCD voltage generation
Symbol
Value
Unit
Note
Ao
2.95
V
PRS = [0;0]
A1
6.83
V
PRS = [0;1]
A2
10.71
V
PRS = [1;0]
B
0.0303
V
To
27
°C
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register
and PRS bits are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the liquid crystal threshold voltage (Vth) and
of the multiplexing rate. A general expression for this is:
1+ m
V LCD = --------------------------------------- ⋅ V th
1 -⎞
2 ⋅ ⎛ 1 – -------⎝
m⎠
For MUX Rate m = 65 the ideal VLCD is:
VLCD(to) = 6.85 · Vth
than:
12/79
( 6.85 ⋅ Vth – A i )
V op = -------------------------------------------0.03
STE2004S
3.7
Circuit description
Temperature coefficients
As the viscosity, and therefore the contrast, of the LCD are subject to change with
temperature, the LCD voltage must be varied with temperature. STE2004S provides eight
different temperature coefficients to change the VLCD in a linear fashion against
temperature. selectable through T2, T1 and T0 bits. Only four of the temperature coefficients
are available through the basic instruction set.
Table 5. Temperature coefficients with basic instruction set
NAME
TC1
TC0
Value
Unit
TC0
0
0
-0.0· 10-3
1/ °C
-3
1/°C
TC2
0
1
-0.7 · 10
TC3
1
0
-1.05· 10-3
1/°C
1
10-3
1/°C
TC6
1
-2.1 ·
Table 6. Temperature coefficients
NAME
T2
T1
T0
Value
Unit
TC0
0
0
0
-0.0· 10-3
1/ °C
TC1
0
TC2
0
0
1
1
0
-0.35 ·
10-3
1/°C
-0.7 ·
10-3
1/°C
10-3
1/°C
TC3
0
1
1
-1.05·
TC4
1
0
0
-1.4 · 10-3
1/°C
1
-1.75·
10-3
1/°C
-2.1 ·
10-3
1/°C
-2.3·
10-3
1/°C
TC5
1
TC6
1
TC7
Figure 7.
1
0
1
0
1
1
Temperature coefficients
VLCD
B
A2
A0 + B
A1
A1
00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h ….
PRS = [0;0]
7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh
PRS = [0;1]
PRS = [1;0]
VO
Finally, the VLCD voltage at a given (T) temperature can be calculated as:
VLCD(T) = VLCDo · [1 + (T-To) · TC]
13/79
Circuit description
3.8
STE2004S
Display data RAM
The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized
into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons.
RAM access is accomplished in either one of the bus interfaces provided (see below).
Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical).
There are four address mode provided to write to RAM:
●
Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on
the left of the memory map. The X pointer is increased after each byte written. After the
last column address (X=X-Carriage), Y address pointer jumps to the following bank and
X restarts from X=0. (Figure 8.)
●
Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the
left of the memory map. The Y pointer is increased after each byte written. After the last
Y bank address (Y=Y-Carriage), X address pointer jumps to next column and Y restarts
from Y=0 (Figure 9).
●
Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on
the right of the memory map. The X pointer is increased after each byte written. After
the last column address (X=X-Carriage), Y address pointer jumps to the next bank and
X restarts from X=0 (Figure 10.).
●
Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the
last Y bank address (Y=Y-Carriage), the X pointer jumps to next column and Y restarts
from Y=0 (Figure 11.).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jumps to the cell with address (X;Y) = (0;0) (Figure 12. Figure 13. Figure 14. Figure 15.).
Data bytes in the memory could have the MSB either on top (D0 = 0, Figure 16.) or on the
bottom (D0=1, Figure 17.).
The STE2004S also allows the normal output address to be altered. The display is mirrored
along the X axis if a logic one MY bit is set. Only the memory read process is altered, the
content is not affected in memory.
When ICON MODE=1 the icon row is not mirrored with MY and is not scrolled.
When ICON MODE=0 the icon row is like an other graphic line and is mirrored and scrolled.
When the partial display mode is disabled, there are three multiplex ratios available (MUX
33, MUX 49 and MUX 65). Only a subset of writable rows are output on row drivers in MUX
33,49 and 65 modes.
When Y-Carriage<MUX/8, if MUX 49 is selected only the first 49 memory rows are
visualized; if MUX 33 selected, only the first 33 memory rows. The unused output row and
column drivers must be left floating.
When Y-Carriage<=MUX/8 the icon bank is located to BANK 8 in MUX 65 Mode, to BANK6
in MUX 49 Mode, and to BANK 4 in MUX 33 Mode.
In MUX 33 and MUX 49 modes and Y-Carriage>MUX/8, only lines 33 and 49 are
visualized.
The lines of DDRAM connected on the output drivers using the scrolling function (Range: 0Y-Carriage*8) are selectable. When Y-Carriage>MUX/8 lines, the icon row is moved in
DDRAM to the first row of the bank, corresponding to the Y-CARRIAGE Return value, being
always connected on the same output Driver.
14/79
STE2004S
Circuit description
When MY=0, the icon Row is output on R64 in MUX 65 mode, on R56 in MUX 49, and on
R48 in MUX33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever the MUX rate.
Figure 8.
Automatic data RAM writing sequence with V=0 and data RAM normal
format (MX=0)(a)
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
1
2
3
98
99
100
101
0
1
2
3
4
5
6
7
8
LR0049
Figure 9.
Automatic data RAM writing sequence with V=1 and data RAM normal
format (MX=0)(a)
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
1
2
3
98
99
100
101
0
1
2
3
4
5
6
7
8
LR0050
a. X Carriage=101; Y-Carriage = 8
15/79
Circuit description
STE2004S
Figure 10. Automatic data RAM writing sequence with V=0 and data RAM mirrored
format (MX=1)(a)
101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
100
99
98
3
2
1
0
0
1
2
3
4
5
6
7
8
LR0051
Figure 11. Automatic data RAM writing sequence with V=1 and data RAM mirrored
format (MX=1)(a)
101
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
100
99
98
3
2
1
0
0
1
2
3
4
5
6
7
8
LR0052
Figure 12. Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=0)
0
1
2
3
X CARR
98
99
100
101
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
LR0053
16/79
STE2004S
Circuit description
Figure 13. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=0)
X CARR
0
1
2
98
3
99
100
101
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
LR0054
Figure 14. Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=1)
X CARR
101
100
99
98
3
2
1
0
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
LR0055
Figure 15. Automatic data RAM writing sequence with X-Y carriage return (V=1;
MX=1)
X CARR
101
100
99
98
3
2
1
0
BANK 0
BANK 1
BANK 2
Y CARR
BANK 7
BANK 8
LR0056
17/79
Circuit description
STE2004S
Figure 16. Data RAM Byte organization with D0 = 0
MSB
0
LSB
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
1
2
3
98
99
100
101
0
1
2
3
4
5
6
7
8
LR0057
Figure 17. Data RAM byte organization with D0 = 1
LSB
0
MSB
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
1
2
3
98
99
100
101
0
1
2
3
4
5
6
7
8
LR0058
18/79
STE2004S
Circuit description
Figure 18. Memory rows vs. row drivers mapping ICON_MODE=1 and MUX 65
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
Y-CARRIAGE
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
0
1
X address
0
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R63
R1
R62
R2
R61
R3
R60
R4
R59
R5
R58
R6
R57
R7
R56
R8
R55
R9
R54
R10
R53
R11
R52
R12
R51
R13
R50
R14
R49
R15
R48
R16
R47
R17
R46
R18
R45
R19
R44
R20
R43
R21
R42
R22
R41
R23
R40
R24
R39
R25
R38
R26
R37
R27
R36
R28
R35
R29
R34
R30
R33
R31
R32
R32
R31
R33
R30
R34
R29
R35
R28
R36
R27
R37
R26
R38
R25
R39
R24
R40
R23
R41
R22
R42
R21
R43
R20
R44
R19
R45
R18
R46
R17
R47
R16
R48
R15
R49
R14
R50
R13
R51
R12
R52
R11
R53
R10
R54
R9
R55
R8
R56
R7
R57
R6
R58
R5
R59
R4
R60
R3
R61
R2
R62
R1
R63
R0
R64
R64
5FH 60H 61H 62H 63H 64H 65H
lr0268
COL
Output
Normal
Direction
Reverse
Direction
C
C
O
O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
O
L
99
C
O
L
2
C
O
L
100
C
O
L
1
C
O
L
101
C
O
L
0
19/79
Circuit description
STE2004S
Figure 19. Memory rows vs. row drivers mapping ICON_MODE=0 and MUX 65
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
Y-CARRIAGE
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
COL
Output
20/79
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
Normal
Direction
Reverse
Direction
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O
O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R64
R1
R63
R2
R62
R3
R61
R4
R60
R5
R59
R6
R58
R7
R57
R8
R56
R9
R55
R10
R54
R11
R53
R12
R52
R13
R51
R14
R50
R15
R49
R16
R48
R17
R47
R18
R46
R19
R45
R20
R44
R21
R43
R22
R42
R23
R41
R24
R40
R25
R39
R26
R38
R27
R37
R28
R36
R29
R35
R30
R34
R31
R33
R32
R32
R33
R31
R34
R30
R35
R29
R36
R28
R37
R27
R38
R26
R39
R25
R40
R24
R41
R23
R42
R22
R43
R21
R44
R20
R45
R19
R46
R18
R47
R17
R16
R48
R49
R15
R50
R14
R51
R13
R52
R12
R53
R11
R54
R10
R55
R9
R56
R8
R57
R7
R58
R6
R59
R5
R60
R4
R61
R3
R62
R2
R63
R1
R64
R0
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
O
L
99
C
O
L
2
C
O
L
100
C
O
L
1
C
O
L
101
C
O
L
0
lr0269
STE2004S
Circuit description
Figure 20. Memory rows vs. Row drivers mapping ICON_MODE=1, Y-Carriage<=6 and
MUX 49
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O
O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R55
R1
R54
R2
R53
R3
R52
R4
R51
R5
R50
R6
R49
R7
R48
R8
R47
R9
R46
R10
R45
R11
R44
R12
R43
R13
R42
R14
R41
R15
R40
R16
R39
R17
R38
R18
R37
R19
R36
R20
R35
R21
R34
R22
R33
R23
R32
R23
R32
R22
R33
R21
R34
R20
R35
R19
R36
R18
R37
R17
R38
R16
R39
R15
R40
R14
R41
R13
R42
R12
R43
R11
R44
R10
R45
R9
R46
R8
R47
R7
R48
R6
R49
R5
R50
R4
R51
R3
R52
R2
R53
R1
R54
R0
R55
R56
R56
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
O
L
99
C
O
L
2
C
O
L
100
C
O
L
1
C
O
L
101
C
O
L
0
lr0270
21/79
Circuit description
STE2004S
Figure 21. Memory rows vs. row drivers ;apping ICON_MODE=0, Y-Carriage<=6 and
MUX 49
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
22/79
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O
O
L
L
1
0
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R56
R1
R55
R2
R54
R3
R53
R4
R52
R5
R51
R6
R50
R7
R49
R8
R48
R9
R47
R10
R46
R11
R45
R12
R44
R13
R43
R14
R42
R15
R41
R16
R40
R17
R39
R18
R38
R19
R37
R20
R36
R21
R35
R22
R34
R23
R33
R32
R32
R23
R33
R22
R34
R21
R35
R20
R36
R19
R37
R18
R38
R17
R39
R16
R40
R15
R41
R14
R42
R13
R43
R12
R44
R11
R45
R10
R46
R9
R47
R8
R48
R7
R49
R6
R50
R5
R51
R4
R52
R3
R53
R2
R54
R1
R55
R0
R56
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
O
L
99
C
O
L
2
C
O
L
100
C
O
L
1
C
O
L
101
C
O
L
0
lr0271
STE2004S
Circuit description
Figure 22. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=7,
scrolling pointer>07h and MUX 49
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R56
R1
R55
R2
R54
R3
R53
R4
R52
R5
R51
R6
R50
R7
R49
R8
R48
R9
R47
R10
R46
R11
R45
R12
R44
R13
R43
R14
R42
R15
R41
R16
R40
R17
R39
R18
R38
R19
R37
R20
R36
R21
R35
R22
R34
R23
R33
R32
R32
R23
R33
R22
R34
R21
R35
R20
R36
R19
R37
R18
R38
R17
R39
R16
R40
R15
R41
R14
R42
R13
R43
R12
R44
R11
R45
R10
R46
R9
R47
R8
R48
R7
R49
R6
R50
R5
R51
R4
R52
R3
R53
R2
R54
R1
R55
R0
R56
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
C
C
O O O
L
L
L
99 100 101
C
C C
O
O O
L
L L
0
2
1
lr0275
23/79
Circuit description
STE2004S
Figure 23. Memory rows vs. row drivers mapping ICON_MODE=1, Y-Carriage=7,
scrolling pointer>07h and MUX 49
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
24/79
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R55
R1
R54
R2
R53
R3
R52
R4
R51
R5
R50
R6
R49
R7
R48
R8
R47
R9
R46
R10
R45
R11
R44
R12
R43
R13
R42
R14
R41
R15
R40
R16
R39
R17
R38
R18
R37
R19
R36
R20
R35
R21
R34
R22
R33
R23
R32
R23
R32
R22
R33
R21
R34
R20
R35
R19
R36
R18
R37
R17
R38
R16
R39
R15
R40
R14
R41
R13
R42
R12
R43
R11
R44
R10
R45
R9
R46
R8
R47
R7
R48
R6
R49
R5
R50
R4
R51
R3
R52
R2
R53
R1
R54
R0
R55
R56
R56
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
C
C
O O O
L
L
L
99 100 101
C
C C
O
O O
L
L L
0
2
1
lr0276
STE2004S
Circuit description
Figure 24. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage=8,
Scrolling pointer<10h and MUX 49
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R55
R1
R54
R2
R53
R3
R52
R4
R51
R5
R50
R6
R49
R7
R48
R8
R47
R9
R46
R10
R45
R11
R44
R12
R43
R13
R42
R14
R41
R15
R40
R16
R39
R17
R38
R18
R37
R19
R36
R20
R35
R21
R34
R22
R33
R23
R32
R23
R32
R22
R33
R21
R34
R20
R35
R19
R36
R18
R37
R17
R38
R16
R39
R15
R40
R14
R41
R13
R42
R12
R43
R11
R44
R10
R45
R9
R46
R8
R47
R7
R48
R6
R49
R5
R50
R4
R51
R3
R52
R2
R53
R1
R54
R0
R55
R56
R56
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
C
C
O O O
L
L
L
99 100 101
C
C C
O
O O
L
L L
0
2
1
LR0273
25/79
Circuit description
STE2004S
Figure 25. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=8,
Scrolling pointer<10h and MUX 49
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
26/79
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R56
R1
R55
R2
R54
R3
R53
R4
R52
R5
R51
R6
R50
R7
R49
R8
R48
R9
R47
R10
R46
R11
R45
R12
R44
R13
R43
R14
R42
R15
R41
R16
R40
R17
R39
R18
R38
R19
R37
R20
R36
R21
R35
R22
R34
R23
R33
R32
R32
R23
R33
R22
R34
R21
R35
R20
R36
R19
R37
R18
R38
R17
R39
R16
R40
R15
R41
R14
R42
R13
R43
R12
R44
R11
R45
R10
R46
R9
R47
R8
R48
R7
R49
R6
R50
R5
R51
R4
R52
R3
R53
R2
R54
R1
R55
R0
R56
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
C
C
O O O
L
L
L
99 100 101
C
C C
O
O O
L
L L
0
2
1
LR0274
STE2004S
Circuit description
Figure 26. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage<=4 and
MUX33
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R47
R1
R46
R2
R45
R3
R44
R4
R43
R5
R42
R6
R41
R7
R40
R8
R39
R9
R38
R10
R37
R11
R36
R12
R35
R13
R34
R14
R33
R15
R32
R15
R32
R14
R33
R13
R34
R12
R35
R11
R36
R10
R37
R9
R38
R8
R39
R7
R40
R6
R41
R5
R42
R4
R43
R3
R44
R2
R45
R1
R46
R0
R47
R48
R48
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
C
C
O O O
L
L
L
99 100 101
C
C C
O
O O
L
L L
0
2
1
LR0272
27/79
Circuit description
STE2004S
Figure 27. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage<=4 and
MUX 33
Y Address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0
1
X address
0
Y-CARRIAGE
COL
Output
28/79
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Normal
Direction
Reverse
Direction
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
C
C
O O
L
L
0
1
C
C
O
O
L
L
101 100
C
O
L
2
C
O
L
99
C
O
L
3
C
O
L
98
C
O
L
4
C
O
L
97
C
O
L
5
C
O
L
96
C
O
L
6
C
O
L
95
Scrolling Pointer
ROW Output
Normal Reverse
direction direction
R0
R48
R1
R47
R2
R46
R3
R45
R4
R44
R5
R43
R6
R42
R7
R41
R8
R40
R9
R39
R10
R38
R11
R37
R12
R36
R13
R35
R14
R34
R15
R33
R32
R32
R15
R33
R14
R34
R13
R35
R12
R36
R11
R37
R10
R38
R9
R39
R8
R40
R7
R41
R6
R42
R5
R43
R4
R44
R3
R45
R2
R46
R1
R47
R0
R48
5FH 60H 61H 62H 63H 64H 65H
C
O
L
95
C
O
L
6
C
O
L
96
C
O
L
5
C
O
L
97
C
O
L
4
C
O
L
98
C
O
L
3
C
C
C
O O O
L
L
L
99 100 101
C
C C
O
O O
L
L L
0
2
1
LR0272
STE2004S
Circuit description
Figure 28. Row drivers vs. LCD panel interconnection in MUX65 mode
ICON
MUX 65
COLUMN DRIVERS
ROW DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
STE2004S
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
ROW DRIVERS
LR0109
Figure 29. Row drivers vs. LCD panel interconnection in MUX49 mode
ICON
MUX 49
COLUMN DRIVERS
ROW DRIVERS
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
STE2004S
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
ROW DRIVERS
LR0108
29/79
Circuit description
STE2004S
Figure 30. Row drivers vs. LCD panel interconnection in MUX33 mode
ICON
MUX 33
COLUMN DRIVERS
ROW DRIVERS
30/79
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
STE2004S
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
ROW DRIVERS
LR0107
STE2004S
4
Bus interfaces
Bus interfaces
To provide the widest flexibility and ease of use the STE2004S features six different
methods for interfacing the host controller. To select the desired interface the SEL1, SEL2
and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH
(connect to VDD). All the I/O pins of the unused interfaces must be connected to GND.
All interfaces work while the STE2004S is in power down.
Table 7. Bus interfaces
4.1
SEL3
SEL2
SEL1
Interface
Note
0
0
0
I2C
0
0
1
SPI 4 lines 8 bit
Read and write
0
1
0
SPI 3 lines 8 bit
Read and write
0
1
1
Serial 3 lines 9 bit
Read and write
1
0
0
Parallel 8080-series
Read and write
1
0
1
Parallel 68000-series
Read and write
Read and write; fast and
high speed mode
I2C Interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different LCs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
–
Data transfer may be initiated only when the bus is not busy.
–
During data transfer, the data line must remain stable whenever the clock line is
high. Changes in the data line while the clock line is high are interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and the stop conditions is not
31/79
Bus interfaces
STE2004S
limited. The information is transmitted byte-wide and each receiver acknowledges with the
ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the signals is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master receiver must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and
hold time must be taken into account. A master receiver must signal an end-of-data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAOUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the STE2004S will not be able to
create a valid logic 0 level. By splitting the SDA input from the output the device could be
used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2004S is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in
Hs-mode without detecting the master code.
Figure 31. Bit transfer and start,stop conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
32/79
CHANGE OF
DATA ALLOWED
STOP
CONDITION
LR0069
STE2004S
Bus interfaces
Figure 32. Acknowledgment on the I2C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
LR0070
4.1.1
Communication protocol
The STE2004S is an I2C slave. The access to the device is bi-directional as data write and
status read are allowed.
The STE2004S has four device addresses. All have the first 5 bits (01111) in common. The
two least significant bit of the slave address are set by connecting the SA0 and SA1 inputs
to a logic 0 or logic 1.
To start the communication between the bus master and the slave LCD driver, the master
must initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA
bus line (most significant bit first). This consists of the 7-bit device select code, and the 1-bit
read/write designator (R/W).
All slaves with the corresponding address acknowledge in parallel, while the rest ignore the
I2C-bus transfer.
Writing mode
When the R/W bit is set to logic 0, the STE2004S is set to be a receiver. After the slaves
acknowledge, one or more command word follows to define the status of the device.
A command word is composed of three bytes. The first is a control byte which defines the
Co and D/C values, the second and third are data bytes. The Co bit is the command MSB
and defines whether this command is followed by two data bytes and and another command
word, or if a stream of data follows (Co = 1 Command word, Co = 0 Stream of data). The
D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C
= 0 Command).
If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte is stored in the data RAM at the location specified by the
data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside
the STE2004S display RAM starting at the address specified by the data pointer. The data
pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
Every byte must be acknowledged by all addressed units.
33/79
Bus interfaces
STE2004S
Reading mode
If the R/W bit is set to logic 1 the chip outputs data immediately after the slave address. If
the D/C bit during the last write access is set to a logic 0, the byte read is the status byte.
Figure 33. Communication protocol
WRITE MODE
DRIVER ACK
DRIVER ACK
S S
S 0 1 1 1 1 A A 0 A 1 DC Control Byte A
1 0
R/W Co
SLAVE ADDRESS
DRIVER ACK
DATA Byte
A 0 DC Control Byte A
Co
COMMAND WORD
DRIVER ACK
LAST
CONTROL BYTE
DRIVER ACK
DATA Byte
A P
N> 0 BYTE
MSB........LSB
READ MODE
DRIVER ACK
S S
S 0 1 1 1 1 A A 1 A
1 0
R/W
4.2
MASTER ACK
P
S S R
0 1 1 1 1 A A /
1 0 W
DRIVER
SLAVE ADDRESS
H H H
C D
0 0 0
A
E [1] [0]
o C
CONTROL BYTE
LR0008
Serial interfaces
STE2004S can feature three different serial synchronized interfaces with the host controller. It is
possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits serial interface.
4.2.1
4-lines SPI interface
The STE2004S 4-lines serial interface is a bidirectional link between the display driver and the
application supervisor. It consists of four lines: one/two for data signals (SDIN, SOUT), one for
clock signals (SCLK), one for the peripheral enable (CS) and one for mode selection (SD/C).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the serial
peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset.
The STE2004S is always a slave on the bus and receives the communication clock on the SCLK
pin from the master.
Information is exchanged byte-wide. During data transfer, the data line is sampled on the positive
SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or a data (SD/C =1); SD/C
line is read on the eighth SCLK clock pulse during every byte transfer.
If CS stays low after the last bit of a command/data byte, the serial interface expects the MSB of
the next byte at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all
the internal registers are cleared.
If CS is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SDOUT, the driver I2C slave address or the status byte can be read. The command
sequence to read the I2C slave address or the status byte is shown in Figure 34., Figure 35.,
34/79
STE2004S
Bus interfaces
Figure 36.. SDOUT is in high impedance in steady state and during data write. It is possible to
short circuit SDOUT and SDIN and read the I2C address or status byte without any additional
lines.
Figure 34. 4-lines serial bus protocol - one byte transmission
CS
D/C
SCLK
MSB
SDIN
LSB
LR0071
Figure 35. 4-lines serial bus protocol - several byte transmission
CS
D/C
SCLK
DB7
SDIN
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
LR0072
Figure 36. 4-lines serial bus protocol - I2C address or status byte read
CS
SCLK
SDIN
DB7
DB6
DB5
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
High-Z
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
High-Z
DB7
DB6
DB5
DB2
DB1
DB0
High-Z
DB4
DB3
DB2
DB1
DB0
D/C
ID Number
SDOUT
DB4
DB3
STATUS BYTE
Command Write
DATA Read
LR00076
35/79
Bus interfaces
Figure 37.
STE2004S
4-lines SPI reading sequence
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and
1
Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read.
LR0078
4.2.2
3-lines SPI interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and
the application supervisor.
It consists of three lines: one/two for data signals (SDIN,SDOUT), one for clock signals
(SCLK) and one for peripheral enable (CS).
If the R/W bit is set to logic 0 the STE2004S is set to be a receiver. One or more command
words follow to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines Co,
D/C, R/W H[1;0] and HE values, the second is a data byte (Figure 38.). The Co bit is the
command MSB and defines whether the command is followed by one data byte and an
other command word, or if it is followed by a stream of commands, or a steam of DDRAM
data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines whether the data
byte is a command or DDRAM data (D/C = 1 RAM Data, D/C = 0 Command). The H[1;0] bits
define the instruction Set Page if HE bit =1. If HE bit is set to 0, H[1;0] values are neglected
and it is possible to update the instruction set page number using only the related instruction
in the instruction set.
If Co =1 and D/C = 0, the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte is stored in the data RAM at the location specified by the
data pointer.
After the last control byte, if D/C is set to a logic 1, the incoming data bytes are stored inside
the STE2004S display data RAM starting at the address specified by the data pointer. The
data pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
36/79
STE2004S
Bus interfaces
Throughout SDOUT can be read the driver I2C slave address or the status byte. The
command sequence that allows to read I2C slave address or the status byte is shown in
Figure 39. and Figure 40..
If the R bit is set to logic 0 and D/C=0, the I2C slave address is read. If the R bit is set to logic
1 and D/C=0, the the I2C slave address is read. SDOUT is in high impedance in steady state
and during data write.
It is possible to short circuit SDOUT and SDIN and read the I2C address or status byte
without any additional line.
Figure 38. 3-lines serial interface protocol in writing mode
WRITE MODE
1
Control Byte
Co
0
DATA Byte
Control Byte
Co
LAST
CONTROL BYTE
COMMAND WORD
R
H H H
C D
/ 0 0
E [1] [0]
o CW
DATA Byte
CONTROL BYTE
N> 0 BYTE
MSB........LSB
Control Byte
0 0
DATA Byte
LAST
CONTROL BYTE
TRANSFERRED
ONLY COMMANDS
DATA Byte
DATA Byte = Command
N> 0 BYTE
MSB........LSB
if D/C=0
DATA Byte = DDRAM Data if D/C=1
Control Byte
0 1
DATA Byte
LAST
CONTROL BYTE
TRANSFERRED
ONLY DDRAM DATA
DATA Byte
N> 0 BYTE
MSB........LSB
LR0002
Figure 39. 3-lines SPI interface protocol in reading mode
CS
SCLK
SDIN
DB7
Co=1
DB6
DB5
D/C=0
R/W=1
"Command" "Read"
DB4
DB3
DB2
High-Z
DB1
DB0
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
DB2
DB1
DB0
High-Z
ID-Number
SDOUT
High-Z
DB7
DB6
DB5
DB4
DB3
STATUS BYTE
Command Write
DATA Read
LR0077
37/79
Bus interfaces
Figure 40.
STE2004S
3-lines SPI reading sequence
READING SEQUENCE
Set Co bit =1, D/C Bit =0 R/W Bit =1
SDOUT Buffer become active (Low Impedence)
Source 8 pulses on SCLK and
1
Read the ID-Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read.
LR0079
4.2.3
3-lines 9 bits serial interface
The STE2004S 3-lines serial interface is a bidirectional link between the display driver and
the application supervisor.
It consists of three lines: one/two for data signals (SDIN, SDOUT), one for clock signals
(SCLK) and one for peripheral enable (CS).
The serial interface is active only if the CS line is set to a logic 0. When CS line is high the
serial peripheral power consumption is zero. While CS pin is high the serial interface is kept
in reset.
The STE2004S is always a slave on the bus and receives the communication clock on the
SCLK pin from the master.
Information is exchanged word-wide. The word is composed of 9 bits. The first bit is named
SD/C and indicates whether the following byte is a command (SD/C =0) or data byte (SD/C
=1). During data transfer, the data line is sampled on the positive SCLK edge.
If CS stays low after the last bit of a command/data byte, the serial interface expects the
SD/C bit of the next word at the next SCLK positive edge. A reset pulse on RES pin
interrupts the transmission. No data is written into the data RAM and all the internal
registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready
to receive data.
Throughout SDOUT, only the driver I2C slave address or the status byte can be read. The
command sequence that the I2C slave address or status byte to be read is shown in Figure
43. and Figure 44.. SDOUT is in high impedance in steady state and during data write.
38/79
STE2004S
Bus interfaces
It is possible to short circuit SDOUT and SDIN, and read the I2C address or status byte
without any additional line.
Figure 41. 3-lines serial bus protocol - one byte transmission
CS
SCLK
SDIN
SD/C
MSB
LSB
LR0073
Figure 42. 3-lines serial bus protocol - several byte transmission
CS
SCLK
SDIN
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D/C
DB7
DB6
LR0074
Figure 43. 3-lines serial interface protocol in Reading Mode
CS
SCLK
SDIN
SD/C
DB7
DB6
DB5
DB4
DB3
High-Z
DB2
DB1
DB0
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
High-Z
DB2
DB1
DB0
High-Z
ID-Number
SDOUT
High-Z
DB7
DB6
DB5
DB4
DB3
STATUS BYTE
Command Write
DATA Read
LR0075
39/79
Bus interfaces
STE2004S
Figure 44. 3-lines serial reading sequence
READING SEQUENCE
Write a "00000000" Instruction
SDOUT Buffer becomes active (Low Impedence)
Source 9 pulses on SCLK and
1
Read the ID Number or the Status Byte On SDOUT
SDOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SDOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read.
LR0080
4.3
Parallel interface
The STE2004S selectable parallel interfaces are 68000-series and 8080-series. They are
both an 8-bits bi-directional link between the display driver and the application supervisor.
Both parallel interfaces can be read the I2C driver slave address or the status byte.
4.3.1
68000-series parallel interface
If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or
transmit data.
While CS pin is high the 68000 parallel interface is kept in reset.
Write mode
If R/W line is set to 0, data is latched on the E falling edge.
Read mode
When R/W line is set to 1, data is output on the D0-D7 bus on the E rising edge. The data
bus is set in high impedance mode when E is set to logic 0.
The I2C address or status byte is output on D0-D7 bus, according to R bit value.
40/79
STE2004S
Bus interfaces
Figure 45. 68000-series parallel interface protocol - one byte transmission
CS
R/W
D/C
E
D0
to
D7
LR0004
Figure 46. 68000-series parallel interface bus protocol - several bytes transmission
CS
R/W
D/C
E
D0
to
D7
LR0081
Figure 47. 68000-series parallel interface protocol in reading mode
CS
D/C
R/W
E
D0
to
D7
LR0082
41/79
Bus interfaces
STE2004S
Figure 48. 68000-series parallel interface protocol in reading mode (several bytes)
CS
D/C
R/W
E
D0
to
D7
Note 1) Data Bus is configured in high impedence mode after evry RD rising edge
2) Always the same data is output on D0-D7
4.3.2
LR0046
8080-series parallel interface
If CS is low after the positive edge of RES, the 8080 parallel interface is ready to receive or
transmit data. While CS pin is high the 8080 parallel interface is kept in reset.
Write mode
Data are latched on WR rising edge.
Read mode
Data is output on the D0-D7 bus on the RD rising edge. The data bus is set in high impedance
mode when RD is set to logic 1.
The I2C address or status byte is output on D0-D7 bus, accordingly to R bit value.
Figure 49. 8080-series parallel bus protocol - one byte transmission
CS
D/C
RD
WR
D0
to
D7
LR0083
42/79
STE2004S
Bus interfaces
Figure 50. 8080-series parallel bus protocol - several bytes transmission
CS
D/C
RD
WR
D0
to
D7
LR0084
Figure 51. 8080-series parallel interface protocol in reading mode
CS
D/C
RD
WR
D0
to
D7
LR0085
Figure 52. 8080-series parallel interface protocol in reading mode (several bytes)
CS
D/C
RD
WR
D0
to
D7
LR0045
Note 1) Data Bus is configured in high impedence mode after every RD rising edge
2) Always the same data is output on D0-D7
43/79
Instruction set
5
STE2004S
Instruction set
Two different instructions formats are provided:
–
With D/C set to LOW : commands are sent to the control circuitry.
–
With D/C set to HIGH : the data RAM is addressed.
Two different instruction sets are embedded: the STE2001-like instruction set and the
extended instruction set. To select the STE2001-like instruction set, the EXT pad must be
connected to a logic LOW (connect to GND). To select the extended instruction set, the EXT
pad must be connected to a logic HIGH (connect to VDD1).
The instruction syntax is summarized in Table 8. (basic-set) and Table 9. (extended set).
Table 8. STE2001/2-like instruction set
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
0
Read I2C address or
status byte
(with 3-lines serial and
4-lines SPI only)
H=0 or H=1
Read command
0
0
0
0
0
0
0
0
0
Function set
0
0
0
0
1
MX
MY
PD
V
Status byte
0
1
PD
BSY
0
D
E
MX
MY
DO
ID code
0
1
0
0
1
1
1
1
ID1
ID0
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data to RAM
Memory blank
0
0
0
0
0
0
0
0
0
1
Starts memory blank
procedure
Scroll
0
0
0
0
0
0
0
0
1
DIR
Scrolls by one row up
or down
VLCD range setting
0
0
0
0
0
0
0
1
0
Display control
0
0
0
0
0
0
1
D
0
E
Select display
configuration
Set CP factor
0
0
0
0
0
1
0
S2
S1
S0
Charge pump
multiplication factor
Set RAM Y
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set horizontal (Y)
RAM address
Set RAM X
0
0
1
X6
X5
X4
X3
X2
X1
X0
Set vertical (X) RAM
address
Power down
H[0] management; entry
mode;
(I2C interface only)
H=0
44/79
PRS[ VLDC programming
0] range selection
STE2004S
Instruction set
Table 8. STE2001/2-like instruction set
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
Checker board
0
0
0
0
0
0
0
0
0
1
Duty
0
0
0
0
0
0
0
0
1
TC select
0
0
0
0
0
0
0
1
TC1
TC0
Data order
0
0
0
0
0
0
1
DO
0
0
Bias ratios
0
0
0
0
0
1
0
BS2
BS1
Reserved
0
0
0
1
X
X
X
X
X
X
Set VOP
0
0
1
OP6
OP5
OP4
OP3
OP2
OP1
OP0
B6
B5
B4
B3
B2
B1
B0
Description
0
Read I2C address or
status byte
(with 3-lines serial and
4-lines SPI only)
H=1
Starts checker board
procedure
MUX Selects duty factor
Set temperature
coefficient for VLDC
BS0 Set desired bias ratios
Not to be used
VOP register write
instruction
Table 9. Extended instruction set
Instruction
D/C
R/W
B7
H independent instructions
Read command
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MX
MY
PD
H[1]
Page selector, power
H[0] down management;
entry mode
Status byte
0
1
PD
BSY
0
D
E
MX
MY
DO
ID code
0
1
0
0
1
1
1
1
ID1
ID0
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data to RAM
H=[0;0] RAM commands
Memory blank
0
0
0
0
0
0
0
0
0
1
Starts memory blank
procedure
Scroll
0
0
0
0
0
0
0
0
1
DIR
Scrolls by one row up
or down
VLCD range setting
0
0
0
0
0
0
0
1
Display control
0
0
0
0
0
0
1
D
0
E
Select display
configuration
Set CP factor
0
0
0
0
0
1
0
S2
S1
S0
Charge pump
multiplication factor
Set RAM Y
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set horizontal (Y)
RAM address
Set RAM X
0
0
1
X6
X5
X4
X3
X2
X1
X0
Set vertical (X) RAM
address
PRS[ PRS[ VLDC programming
1]
0] range selection
45/79
Instruction set
STE2004S
Table 9. Extended instruction set
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
0
0
0
0
0
0
0
0
0
1
Starts checker board
procedure
0
0
0
0
0
0
0
0
1
V
Vertical addressing
mode
TC select
0
0
0
0
0
0
0
1
TC1
TC0
Set temperature
coefficient for VLDC
Data order
0
0
0
0
0
0
1
DO
0
0
Bias ratios
0
0
0
0
0
1
0
BS2
BS1
Read mode,
0
0
0
1
0
0
R
0
0
0
Set VOP
0
0
1
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Driver control
0
0
0
0
0
0
0
0
0
1
Software reset
Display control
0
0
0
0
0
0
0
0
1
PE
Partial enable
0
0
0
0
0
0
0
1
FR1
FR0 Frame rate control
0
0
0
0
0
0
1
0
M[1]
M[0] MUX ratio
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
Scrolling pointer reset
0
0
0
0
0
0
0
0
1
X
Not used
0
0
0
0
0
0
0
1
X
X
Not used
0
0
0
0
0
0
1
T2
T1
T0
Set temperature
coefficient for VLDC
0
0
0
0
0
1
NW3 NW2 NW1 NW0 N-Line inversion
0
0
0
1
0
0
YC-3 YC-2 YC-1 YC-0 Y carriage return
0
0
1
H=[0;1]
Checker board
MSB position
BS0 Set desired bias ratios
VOP register write
instruction
H=[1;0]
Partial mode
PDC2 PDC1 PDC0 Partial display config
PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
1st Sector start
address
PDY6 PDY5 PDY4 PDY3 PDY2 PDY1 PDY0
2nd Sector start
address
H=[1;1]
46/79
XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0 X carriage return
STE2004S
Instruction set
Table 10. Explanations of Table 8 and Table 9 symbols
Bit
0
1
Reset state
DIR
Scroll by one down
Scroll by one up
H[0]
Select page 0
Select page 1
0
PD
Device fully working
Device in power down
1
V
Horizontal addressing
Vertical addressing
0
MX
Normal X axis addressing
X axis address is mirrored.
0
MY
Image is displayed not vertically
mirrored
Image is displayed vertically
mirrored
0
DO
MSB on TOP
MSB on BOTTOM
0
PE
Partial Display disabled
Partial Display enabled
0
MUX
MUX 65 mode
MUX 33 mode
0
R
Read ID-Number / I2C address
Read status byte
0
Table 11. Page selection
H[1]
H[0]
Description
0
0
Page 0
0
1
Page 1
1
0
Page 2
1
1
Page 3
Reset state
Page 0
Table 12. Display mode
D
E
Description
Reset state
0
0
Display blank
0
1
Qll display segments on
E=0
1
0
Normal mode
D=0
1
1
Inverse video mode
Table 13. Frame rate control
FR[1]
FR[0]
Description
0
0
65Hz
0
1
70Hz
1
0
75Hz
1
1
80Hz
Reset state
75Hz
47/79
Instruction set
STE2004S
Table 14. Vlcd range selection
PRS[1]
PRS[0]
Description
0
0
0
1
6.78
1
0
10.62
1
1
10.62
Reset state
2.94
Table 15. Multiplexing ratio
M[1]
M[0]
Description
0
0
49
0
1
65
1
0
33
1
1
Not Allowed
Reset state
01
Table 16. Temperature coefficient (T0, T1, T2)
T2
T1
T0
Description
0
0
0
VLCD temperature coefficient 0
0
0
1
VLCD temperature coefficient 1
0
1
0
VLCD temperature coefficient 2
0
1
1
VLCD temperature coefficient 3
1
0
0
VLCD temperature coefficient 4
1
0
1
VLCD temperature coefficient 5
1
1
0
VLCD temperature coefficient 6
1
1
1
VLCD temperature coefficient 7
Reset state
000
Table 17. Temperature coefficient (TC0, TC1)
48/79
TC1
TC0
Description
0
0
VLCD temperature coefficient 0
0
1
VLCD temperature coefficient 2
0
1
VLCD temperature coefficient 3
1
1
VLCD temperature coefficient 6
Reset state
00
STE2004S
Instruction set
Table 18. Charge pump multiplication factor
CP2
CP1
CP0
Description
0
0
0
Multiplication factor X2
0
0
1
Multiplication factor X3
0
1
0
Multiplication factor X4
0
1
1
Multiplication factor X5
1
0
0
Not used
1
0
1
Not used
1
1
0
Not used
1
1
1
Automatic
Reset state
000
Table 19. Bias ratio
BS2
BS1
BS0
Description
0
0
0
Bias ratio equal to 7
0
0
1
Bias ratio equal to 6
0
1
0
Bias ratio equal to 5
0
1
1
Bias ratio equal to 4
1
0
0
Bias ratio equal to 3
1
0
1
Bias ratio equal to 2
1
1
0
Bias ratio equal to 1
1
1
1
Bias ratio equal to 0
Reset state
000
Table 20. Y Carriage return register
Y-C[3]
Y-C[2]
Y-C[1]
Y-C[0]
Description
0
0
0
0
Y-CARRIAGE =0
0
0
0
1
Y-CARRIAGE =1
0
0
1
0
Y-CARRIAGE =2
0
0
1
1
Y-CARRIAGE =3
0
1
0
0
Y-CARRIAGE =4
.
.
.
.
0
1
1
0
Y-CARRIAGE =6
0
1
1
1
Y-CARRIAGE =7
1
0
0
0
Y-CARRIAGE =8
Reset state
1000
49/79
Instruction set
STE2004S
Table 21. Partial display configuration
PD2
PD1
PD0
Section 1
Section 2
0
0
0
0
8 + Icon row
0
0
1
8
0 + Icon row
0
1
0
8
8 + Icon row
0
1
1
0
16 + Icon row
1
0
0
16
0 + Icon row
1
0
1
8
16 + Icon row
1
1
0
16
8 + Icon row
1
1
1
16
16 + Icon row
Reset state
000
Table 22. N-Line inversion
5.1
NW3
NW2
NW1
NW0
Description
0
0
0
0
0-Line inversion
(Frame inversion)
0
0
0
1
2-Line inversion
0
0
1
0
3-Line inversion
0
0
1
1
4-Line inversion
:
:
:
:
:
1
1
1
0
15-Line inversion
1
1
1
1
16-Line inversion
Reset state
0000
Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is
not defined. A reset pulse on the RES pad (active low) re-initializes the internal registers
content see Table 10. All on-going communication with the host controller is interrupted if a
reset pulse is applied. After the power-on, the software reset instruction can be used to reload the reset configuration into the internal registers.
The default configuration is:
– Horizontal addressing (V = 0)
– Multiplexing ratio (M[1:0]=0 - MUX 65)
– Normal instruction set (H[1:0] = 0)
– Frame rate (FR[1:0]=”75Hz”)
– Normal display (MX = MY = 0)
– Power down (PD = 1)
– Display blank (E = D = 0)
– Dual partial display disabled (PE=0)
– Address counter X[6: 0] = 0 and Y[4: 0] = 0
– VOP=0
– Temperature coefficient (TC[1: 0] = 0)
– Y-CARRIAGE=8
– Bias system (BS[2: 0] = 0)
– X-CARRIAGE=101
A memory blank instruction can be used to clear the DDRAM content.
50/79
STE2004S
5.2
Instruction set
Power down (PD = 1)
At power down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD
generator are off (VLCDOUT output is discharged to VSS, and then VLCDOUT can be
disconnected). The internal oscillator is in off state. An external clock can be provided. The
RAM contents is not cleared.
5.3
Memory blanking procedure
This instruction fills the memory with "blank" patterns, in order to delete patterns randomly
generated in memory when starting up the device. It substitutes (102X8) single "write"
instructions. The procedure can only be programmed if:
PD bit = 0
No instruction can be programmed for a period equivalent to 102X8 internal write cycles
(102X8X1/fclock). The start of the memory blanking procedure is between one and two
fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK
rising edge for the serial and SPI interfaces, last SCL rising edge for the I2C interface).
5.4
Checker board procedure
This instruction fills the memory with "checker-board" pattern, allowing developers to create
a complex module test configuration using one instruction. It can only be programmed if:
PD bit = 0
No instruction can be programmed for a period equivalent to 102X8 internal write cycles
(102X8X1/fclock). The start of checker-board procedure is between one and two fclock
cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising
edge for the serial and SPI interfaces, last SCL rising edge for the I2C interface).
5.5
Scrolling function
The STE2004S can scroll the graphics display in units of raster-rows. The scrolling function
changes the correspondence between the rows of the logical memory map and the output
row drivers. The scroll function does not affect the data ram contentm it is only related to the
visualization process. The information output on the drivers is related to the row reading
sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means
reading the matrix starting from a row that is sequentially increased or decreased. After
every scrolling command the offset between the memory address and the memory scanning
pointer is increased or decreased by one. The offset range changes in accordance with
MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th
scrolling commands in MUX 49 mode, or after 32nd/33rd scrolling command in MUX 33
mode, the offset between the memory address and the memory scanning pointer is again
zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force the offset between the
memory address and the memory scanning pointer to zero.
If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a
general purpose row and it is scrolled as other lines.
51/79
Instruction set
STE2004S
If the DIR bit is set to a logic 0, the offset register is increased by one and the raster is
scrolled from top down. If the DIR bit is set to a logic 1, the offset register is decreased by
one and the raster is scrolled from bottom-up.
Table 23. Scrolling function
5.6
MUX Rate
Icon mode
Description
Icon row driver with MY=0
MUX 33
1
Icon row not scrooled
R48
MUX 33
0
33 line graphic matrix
R48
MUX 49
1
Icon row not scrooled
R56
MUX 49
0
49 line graphic matrix
R56
MUX 65
1
Icon row not scrooled
R64
MUX 65
0
65 line graphic matrix
R64
Dual partial display
If the PE bit is set to a logic one the dual partial display mode is enabled. There are eight
partial display modes available. The offset of the two partial display zones is row by row
programmable. The icon row is accessed last in each partial display frame.
Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0],
BS[2:0], CP[2:0]), allowing normal mode and partial display mode to be switched using one
instruction. The HV generator is automatically reconfigured using the parameters related to
the enabled mode. The parameters of the two sets of registers with the same function are
located in the same position of the instruction set. The registers related to the normal mode
are accessible when normal mode (PE=0) is selected, the others are accessible when the
partial display mode is enabled (PE=1). To setup the PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
values, follow the instruction flow proposed in Figure 54. To setup partial display sectors
start qddress and partial display mode no particular instruction flow has to be followed.
Figure 53. Dual partial display enabling instruction flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address
SET 2nd Sector Start Address
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
52/79
OPTIONAL1
STE2004S
Instruction set
Figure 54. Dual partial display mode configuration or duty change
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
for Partial Display Operation
SET Partial Display Configuration (PDC[2:0])
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Table 24. Partial display configurations
PDC2
PDC1
PDC0
Section 1
Section2
0
0
0
0
8 + Icon Row
0
0
1
8
0 + Icon Row
0
1
0
8
8 + Icon Row
0
1
1
0
16 + Icon Row
1
0
0
16
0 + Icon Row
1
0
1
8
16 + Icon Row
1
1
0
16
8 + Icon Row
1
1
1
16
16 + Icon Row
Reset state
000
53/79
ID-number
6
STE2004S
ID-number
The STE2004S lets you program a driver identification number (ID-Number), so more than
one LCD module with different configuration parameters can be managed on one platform.
There are four programmable device ID-numbers: 00111100, 00111101, 0011110 and
0011111. All have the first 6 bits (001111) in common. The two least significant bits can be
used to connect the SA0 and SA1 inputs to a VSS or VDD1.
The driver ID-number can be read through all communication interfaces. The way to read
the ID-number changes according the interface selected. The readout protocol for each
interface is described in Chapter 4.
Figure 55. I2C interface interconnection in master/ slave mode
STE2004S
RES
SCL
STE2004S
SDAOUT SDAIN
RES
SCL
SDAOUT
SDAIN
LR0214
NOTE:
MASTER and SLAVE I2C AADDRESS
MUST BE DIFFERENT
RES
SCL
SDA
Figure 56. I3-lines SPI and 3-lines serial interfaces interconnection in master slave
mode
STE2004S
RES
CS
SCLK
SDIN
SDOUT
STE2004S
RES
CS
SCLK
SDIN SDOUT
LR0215
RES MASTER SCLK
CS
54/79
SD
SLAVE
CS
STE2004S
ID-number
Figure 57. 4-lines SPI interface interconnection in master slave mode
STE2004S
RES
CS
D/C
SCLK
SDIN
STE2004S
RES
SDOUT
D/C
CS
SCLK
SDIN SDOUT
LR0216
RES
MASTER D/C
CS
SCLK
SD
SLAVE
CS
Figure 58. 8080-series and 68000-series interface interconnection in master slave
mode
STE2004S
STE2004S
RES
CS
D/C RW-RD
E-WR
D7-D0
RES
D/C
CS
RW-RD
E-WR
D7-D0
LR0217
8 LINES
RES
MASTER D/C
CS
RW-RD E-WR
D7-D0
8 LINES
SLAVE
CS
55/79
ID-number
STE2004S
Figure 59. Host processor interconnection with I2C interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
STE2004S
SCLK -SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0110
Figure 60. Host processor interconnection with 4-line SPI interface
VSS
TEST_MODE
STE2004S
µP
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VDD1
VSSAUX
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0111
56/79
STE2004S
ID-number
Figure 61. Host processor interconnection with 3-line SPI interface
VSS
TEST_MODE
µP
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
STE2004S
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
VDD1
VSSAUX
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0112
Figure 62. Host processor interconnection with 3-line serial interface
VSS
TEST_MODE
STE2004S
µP
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VDD1
VDD1
VSSAUX
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0113
57/79
ID-number
STE2004S
Figure 63. Host processor interconnection with 8080-series parallel interface
VSS
TEST_MODE
STE2004S
µP
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VSSAUX
VSSAUX
VDD1
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0114
Figure 64. Host processor interconnection with 6800
VSS
TEST_MODE
STE2004S
µP
VSSAUX
D0
D1
D2
D3
D4
D5
D6
D7
SCLK-SCL
SDOUT
SDIN-SDAIN
SDAOUT
VSSAUX
E - WR
R/W - RD
D/C
CS
RES
VDD2
VDD1
ICON
SEL1
SEL2
SEL3
EXT_SET
M/S
SA0
SA1
VSSAUX
TEST VREF
ANALOG VDD
DIGITAL VDD
VDD1 / VSSAUX
VDD1
VSSAUX
VDD1
VDD1 / VSSAUX
VDD1
VDD1 / VSSAUX
VDD1 / VSSAUX
VSENSE_SLAVE
OSC_IN
FR_IN
VDD1_AUX
LR0115
58/79
STE2004S
ID-number
Figure 65. Application schematic using the internal LCD voltage generator and two
separate supplies
I/O
VDD2
VDD2
VDD1
1µF
VSS
VDD1
32
1µF
VSS
102
VLCDSENSE
33
65 x 102
DISPLAY
1µF
VLCD
Figure 66. Application schematic using the internal LCD voltage generator and a
single supply
I/O
VDD
VDD2
32
VDD1
1µF
VSS
VSS
102
VLCDSENSE
33
65 x 102
DISPLAY
1µF
VLCD
59/79
ID-number
STE2004S
Figure 67. Power-ON timing diagram
Tvdd
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
CS
SCLK
SDIN
D/C
E
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
SCL- SDAIN
SDOUT SDA OUT
Hi-Z
OSCIN, FR_IN
(HOST)
OSC OUT, FR_OUT
(DRIVER)
RESET POWER ON
BOOSTER
Acceptance INTERNAL
OFF
RESET
Time
LR0208
60/79
STE2004S
ID-number
Figure 68. Power-OFF timing diagram
TVDD
VDD2
VDD1
RES
CLK-SCL
SDIN-SDAIN
D/C
E
CS
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
SDOUT
SDA-OUT
Hi-Z
OSCIN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
FR_IN
RESET
TABLE
LOADED
LR0207
61/79
ID-number
STE2004S
Figure 69. Initialization with built-in booster
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET Operative Voltage for Normal Display Operation
( Vop[6:0] - PRS[1;0])
SET Bias Raio for Normal Display Operation
(BS[2:0])
SET Temperature Compensation for
Normal Display Operation (T[2:0] or TC[1:0])
SET Multiplexing Rate
M[1:0)
SET Charge Pump for
Normal Display Operation (CP[1:0])
Switch "ON" Booster and Display Control Logic
(PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
LR0218
62/79
STE2004S
ID-number
Figure 70. Data RAM to display mapping
DISPLAY DATA RAM
GLASS
TOP VIEW
bank
0
bank
1
DISPLAY DATA RAM = "1"
DISPLAY DATA RAM = "0"
bank
2
LCD
bank
3
bank
7
bank
8
ICOR ROW
D00IN1155
Table 25. Test pin configuration
Test Pin
Pin Configuration
TEST_VREF
OPEN
TEST_MODE
GND
63/79
Electrical characteristics
STE2004S
7
Electrical characteristics
7.1
Absolute maximum ratings
Table 26. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDD1
Supply voltage range
- 0.5 to + 5
V
VDD2
Supply voltage range
- 0.5 to + 7
V
VLCD
LCD supply voltage range
- 0.5 to + 15
V
ISS
Supply current
- 50 to +50
mA
Vi
Input voltage (all input pads)
-0.5 to VDD1 + 0.5
V
Iin
DC input current
- 10 to + 10
mA
Iout
DC output current
- 10 to + 10
mA
Ptot
Total power dissipation (Tj = 85°C)
300
mW
Po
Power dissipation per output
30
mW
Tj
Operating junction temperature(1)
-25 to + 85
°C
Storage temperature
- 65 to 150
°C
Tstg
1. Device behavior and characterization are measured over this temperature range during internal qualification of the product.
During production testing, however, device performance is measured at a fixed ambient temperature - typically 25°C.
7.2
DC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25°C;
unless otherwise specified.
Table 27. DC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
3.6
V
VDD2
V
Supply voltages
1.7
VDD1
Supply voltage(1)
VDD2
Supply voltage
LCD voltage internally
generated
1.75
4.5
V
LCD supply voltage
LCD voltage supplied
externally
4.5
14.5
V
LCD supply voltage
Internally generated(2)
4.5
14.5
V
Supply current
VDD1 = 2.8V;
VLCD = 10V; fsclk = 0;
Parallel Port (3) (5)
15
20
40
µA
Supply current write
mode
VDD2 = 2.8V;
VLCD = 10V; fsclk = 1Mhz;
OSC_IN=GND(3)
100
200
µA
VLCD
I(VDD1)
64/79
STE2004S
Electrical characteristics
Table 27. DC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
with VOP = 0 and
PRS = [0:0] with external
VLCD(4)
I(VDD2)
I(VDD1,2)
I(VLDCIN)
Max.
Unit
5
µA
Voltage generator supply
VDD2 = 2.8V;
current
VLCD = 10V; fsclk=0;
no display load;
5x charge pump(5)(3) (6)
60
150
µA
VDD2 = 2.8V; VLCD =
10V; 5x charge pump;
fsclk = 0;
no display load(5) (3) (6)
80
190
µA
Power down mode with
internal or external
VLCD(7)
3
15
µA
25
µA
Total supply current
External LCD supply
voltage current
VDD =2.8V;
VLCD =10V;
no display load;
fsclk = 0;(3)
Logic outputs
V0H
High logic level output
voltage
IOH=-500µA
0.8VDD1
VDD1
V
VOL
Low logic level output
voltage
IOL=+500µA
VSS
0.2VDD1
V
Logic inputs
VIL
Logic low voltage level
VSS
0.3 VDD1
V
VIH
Logic high voltage level
0.7 VDD1
VDD2
V
Iin
Input current
-1
1
µA
Vin = VSS1 or VDD1
Logic inputs/outputs
VIL
Logic low voltage level
VSS
0.3 VDD1
V
VIH
Logic high voltage level
0.7 VDD1
VDD1 + 0.5
V
65/79
Electrical characteristics
STE2004S
Table 27. DC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Column and row driver
Rrow
ROW output resistance
3K
5K
kohm
Rcol
Column output
resistance
5K
10K
kohm
Vcol
Column bias voltage
accuracy
-50
+50
mV
Vrow
Row bias voltage
accuracy
-50
+50
mV
-2
+2
%
No load
LCD supply voltage
VLCD
LCD supply voltage
accuracy; internally
generated
VDD = 2.8V; VLCD = 10V;
fsclk=0;
no display load(5)(3) (6) (8)
VOP=69h, PRS=2Hex(9)
-0.0· 10-3
TC0
1/°C
10-3
1/°C
-0.7 ·
10-3
1/°C
-1.05·
10-3
1/°C
TC4
-1.4 · 10-3
1/°C
TC5
-1.75·
10-3
1/°C
-2.1 ·
10-3
1/°C
-2.3·
10-3
1/°C
TC1
-0.35 ·
TC2
TC3
Temperature coefficient
TC6
TC7
1. VDD1<=VDD2
2. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load.
3. When fsclk = 0 there is no interface clock.
4. If external VLCD, the display load current is not transmitted to IDD
5. Internal clock
6. Tolerance depends on the temperature; (typically zero at Tamb = 25°C), maximum tolerance values are measured at the
temperature range limit.
7. Power-down mode. During power-down all static currents are switched-off.
8. For TC0 to TC7
9. Data byte writing mode
66/79
STE2004S
7.3
Electrical characteristics
AC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =25°C;
unless otherwise specified.
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
61
72
83
kHz
100
kHz
Internal oscillator (Figure 71)
FOSC
Internal oscillator
frequency
FEXT
External oscillator
frequency
FFRAME
Frame frequency
VDD = 2.8V
20
fosc or fext = 72 kHz(1)
RES LOW pulse width
Tw(RES)
TLOGIC
75
Hz
µs
5
Reset pulse rejection
1
µs
Internal logic reset time
5
µs
(RES)
TVDD
I2C
VDD1 vs. VDD2 Delay
bus interface (Figure
FSCL
µs
0
72)(2) (3)
SCL clock frequency
Fast mode
DC
400
kHz
High speed mode;
Cb=100pF (max);(4)
VDD1=2
DC
3.4
MHz
High speed mode;
Cb=400pF (max)(4);
VDD1=2
DC
1.7
MHz
400
KHz
Fast Mode (4);VDD1=1.7V
TSU;STA
Set-up time (repeated)
START condition
Cb = 100pF(5) (6)
160
ns
THD;STA
Hold time (repeated)
START condition
Cb = 100pF(5) (6)
160
ns
TLOW
Low period of SCLH
clock
Cb = 100pF(5) (6)
160
ns
THIGH
High period of SCLH
clock
Cb = 100pF(5) (6)
160
ns
Data set-up time
Cb = 100pF(5) (6)
60
ns
Cb =
100pF(5) (6)
10
ns
Tr;CL
Rise time of SCLH signal Cb =
100pF(5) (6)
10
ns
Tr;CL1
Rise time of SCLH signal
after a repeated START
Cb = 100pF(5) (6)
condition and aftyer an
acknowledge bit
10
ns
Tf;CL
Fall time of SCLH signal
Cb = 100pF(5) (6)
10
ns
TSU;DAT
THD;DAT
Data hold time
67/79
Electrical characteristics
STE2004S
Table 28. AC operation
Symbol
Parameter
Test condition
10
Cb = 100pF(5) (6)
10
(5) (6)
20
(5) (6)
Tr;DA
Rise time of SCLH signal Cb = 100pF
Tf;DA
Fall time of SDAH signal
Tr;DA
Tf;DA
TSU;STO
Min.
(5) (6)
Rise time of SDAH signal Cb = 400pF
Fall time of SDAH signal
Cb = 400pF
20
Setup time for STOP
condition
Cb = 100pF(5) (6)
160
Cb
Capacitive load for SDAH
and SCLH
Cb
Capacitive load for SDAH
+SDA line and SCLH
+SCL line
100
Typ.
Max.
Unit
ns
80
ns
ns
160
ns
ns
400
pF
400
pF
Parallel interface (Figure 73, Figure 74)
TCYC
System cycle time
TCLW
VDD1 = 1.7V;
read and write
125
ns
Control low pulse width
(WR)
20
ns
TCHW
Control high pulse width
(WR)
75
ns
TCLR
Control low pulse width
(RD)
40
ns
TCHR
Control high pulse width
(RD)
55
ns
TEWHW
Enable high pulse width
(Write)
60
ns
TEWLW
Enable low pulse width
(Write)
60
ns
TEWHR
Enable high pulse width
(Read)
60
ns
TEWLR
Enable low pulse width
(Read)
60
ns
TSU(A)
Address set-up time
10
ns
TH(A)
Address hold time
10
ns
TSU1
Data set-up time
30
ns
TH1
Data hold time
30
ns
TSU2
Read access time
TH2
Output disable time
68/79
0
40
ns
30
ns
STE2004S
Electrical characteristics
Table 28. AC operation
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Serial interface (Figure 75)
FSCLK
Clock frequency
TCYC
VDD1 = 1.7V;
8
MHz
Clock cycle SCLK
125
ns
TPWH1
SCLK pulse width HIGH
60
ns
TPWL1
SCLK pulse width LOW
60
ns
TS2
CS setup time
VDD1 = 1.7V
40
ns
TH2
CS hold time
VDD1 = 1.7V
50
ns
TPWH2
CS minimum high time
VDD1 = 1.7V
50
ns
TS3
SD/C setup time
30
ns
TH3
SD/C hold time
30
ns
TS4
SDIN setup time
30
ns
TH4
SDIN hold time
40
ns
TS5
SDOUT access time
TH5
SDOUT disable time vs.
SCLK
TH6
SDOUT disable time vs.
CS
30
ns
0
20
ns
0
20
ns
f osc
1. F
frame = ---------960
2. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
3. Trise and Tfall (30%-70%) -10ns
4.
CVLCD is the filtering capacitor on VLCD
5. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and
VIH with an input voltage swing of VSS to VDD
6. Cb is the capacitive load for each bus line.
69/79
Electrical characteristics
STE2004S
Figure 71. Reset timing diagram
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
INPUTS
I/O
(HOST)
I/O
(DRIVER)
Hi-Z
INTERFACE
OUTPUT
Hi-Z
OSCIN
FR_IN
(HOST)
OSC OUT
FR_OUT
(DRIVER)
RESET
TABLE
LOADED
LR0209
Figure 72. I2C-bus timings
Sr
Sr P
tfDA
trDA
SDAH
tHD;DAT
tSU;STA
tSU;DAT
tHD;STA
SCLH
tfCL
trCL
trCL1
tHIGH tLOW
= MCS current source pull-up
= Rp resistor pull-up
70/79
(1)
tLOW tHIGH
trCL1
(1)
LR0093
STE2004S
Electrical characteristics
Figure 73. 68000-series parallel interface timing
D/C
R/W
tSU(A)
tH(A)
CS
tCYC
tEWHR, tEWHW
E
tEWLR, tEWLW
tSU1
tH1
D0 to D7
(Write)
tSU2
tH2
D0 to D7
(Read)
Figure 74. 8080-series parallel interface timing
D/C
tSU(A)
tH (A)
CS
tCYC
tCLR , tCLW
WR, RD
tCHR , tCHW
tSU1
tH1
D0 to D7
(Write)
tSU2
tH2
D0 to D7
(Read)
71/79
Pad coordinates
STE2004S
Figure 75. Serial interface timing
tS2
tH2
tPWH2
CS
tH3
tS3
D/C
tCYC
tPWL1
tWH1
tS2
SCLK
tS4
tH4
SDIN
tS5
tH5
tH6
SOUT
LR0096
8
Pad coordinates
See Table 29: Pad coordinates and Table 30: Alignment marks coordinates.
72/79
STE2004S
Pad coordinates
Table 29. Pad coordinates
No
Pad placements
Name
X
Y
No
Pad placements
Name
X
Y
1
R5
-2632.5
-532.8
34
C27
-1147.5
-532.8
2
R4
-2587.5
-532.8
35
C28
-1102.5
-532.8
3
R3
-2542.5
-532.8
36
C29
-1057.5
-532.8
4
R2
-2497.5
-532.8
37
C30
-1012.5
-532.8
5
R1
-2452.5
-532.8
38
C31
-967.5
-532.8
6
R0
-2407.5
-532.8
39
C32
-922.5
-532.8
7
C0
-2362.5
-532.8
40
C33
-877.5
-532.8
8
C1
-2317.5
-532.8
41
C34
-832.5
-532.8
9
C2
-2272.5
-532.8
42
C35
-787.5
-532.8
10
C3
-2227.5
-532.8
43
C36
-742.5
-532.8
11
C4
-2182.5
-532.8
44
C37
-697.5
-532.8
12
C5
-2137.5
-532.8
45
C38
-652.5
-532.8
13
C6
-2092.5
-532.8
46
C39
-607.5
-532.8
14
C7
-2047.5
-532.8
47
C40
-562.5
-532.8
15
C8
-2002.5
-532.8
48
C41
-517.5
-532.8
16
C9
-1957.5
-532.8
49
C42
-472.5
-532.8
17
C10
-1912.5
-532.8
50
C43
-427.5
-532.8
18
C11
-1867.5
-532.8
51
C44
-382.5
-532.8
19
C12
-1822.5
-532.8
52
C45
-337.5
-532.8
20
C13
-1777.5
-532.8
53
C46
-292.5
-532.8
21
C14
-1732.5
-532.8
54
C47
-247.5
-532.8
22
C15
-1687.5
-532.8
55
C48
-202.5
-532.8
23
C16
-1642.5
-532.8
56
C49
-157.5
-532.8
24
C17
-1597.5
-532.8
57
C50
-112.5
-532.8
25
C18
-1552.5
-532.8
58
C51
112.5
-532.8
26
C19
-1507.5
-532.8
59
C52
157.5
-532.8
27
C20
-1462.5
-532.8
60
C53
202.5
-532.8
28
C21
-1417.5
-532.8
61
C54
247.5
-532.8
29
C22
-1372.5
-532.8
62
C55
292.5
-532.8
30
C23
-1327.5
-532.8
63
C56
337.5
-532.8
31
C24
-1282.5
-532.8
64
C57
382.5
-532.8
32
C25
-1237.5
-532.8
65
C58
427.5
-532.8
33
C26
-1192.5
-532.8
66
C59
472.5
-532.8
73/79
Pad coordinates
STE2004S
Table 29. Pad coordinates
No
Pad placements
Name
X
Y
No
Pad placements
Name
X
Y
67
C60
517.5
-532.8
100
C93
2002.5
-532.8
68
C61
562.5
-532.8
101
C94
2047.5
-532.8
69
C62
607.5
-532.8
102
C95
2092.5
-532.8
70
C63
652.5
-532.8
103
C96
2137.5
-532.8
71
C64
697.5
-532.8
104
C97
2182.5
-532.8
72
C65
742.5
-532.8
105
C98
2227.5
-532.8
73
C66
787.5
-532.8
106
C99
2272.5
-532.8
74
C67
832.5
-532.8
107
C100
2317.5
-532.8
75
C68
877.5
-532.8
108
C101
2362.5
-532.8
76
C69
922.5
-532.8
109
R32
2407.5
-532.8
77
C70
967.5
-532.8
110
R33
2452.5
-532.8
78
C71
1012.5
-532.8
111
R34
2497.5
-532.8
79
C72
1057.5
-532.8
112
R35
2542.5
-532.8
80
C73
1102.5
-532.8
113
R36
2587.5
-532.8
81
C74
1147.5
-532.8
114
R37
2632.5
-532.8
82
C75
1192.5
-532.8
115
R38
2773.8
-472.5
83
C76
1237.5
-532.8
116
R39
2773.8
-427.5
84
C77
1282.5
-532.8
117
R40
2773.8
-382.5
85
C78
1327.5
-532.8
118
R41
2773.8
-337.5
86
C79
1372.5
-532.8
119
R42
2773.8
-292.5
87
C80
1417.5
-532.8
120
R43
2773.8
-247.5
88
C81
1462.5
-532.8
121
R44
2773.8
-202.5
89
C82
1507.5
-532.8
122
R45
2773.8
-157.5
90
C83
1552.5
-532.8
123
R46
2773.8
-112.5
91
C84
1597.5
-532.8
124
R47
2773.8
-67.5
92
C85
1642.5
-532.8
125
R48
2773.8
-22.5
93
C86
1687.5
-532.8
126
R49
2773.8
22.5
94
C87
1732.5
-532.8
127
R50
2773.8
67.5
95
C88
1777.5
-532.8
128
R51
2773.8
112.5
96
C89
1822.5
-532.8
129
R52
2773.8
157.5
97
C90
1867.5
-532.8
130
R53
2773.8
202.5
98
C91
1912.5
-532.8
131
R54
2773.8
247.5
99
C92
1957.5
-532.8
132
R55
2773.8
292.5
74/79
STE2004S
Pad coordinates
Table 29. Pad coordinates
No
Pad placements
Name
X
Y
No
Pad placements
Name
X
Y
133
R56
2773.8
337.5
166
VDD2
877.5
532.8
134
R57
2773.8
382.5
167
VDD2
832.5
532.8
135
R58
2773.8
427.5
168
VDD2
787.5
532.8
136
R59
2773.8
472.5
169
VDD2
742.5
532.8
137
R60
2632.5
532.8
170
VDD2
697.5
532.8
138
R61
2587.5
532.8
171
VDD2
652.5
532.8
139
R62
2542.5
532.8
172
_RES
337.5
532.8
140
R63
2497.5
532.8
173
-CS
247.5
532.8
141
R64/ICON
2452.5
532.8
174
D/C
157.5
532.8
142
VDD1 AUX
2227.5
532.8
175
RW-RD
67.5
532.8
143
FR IN
2182.5
532.8
176
E-WR
-22.5
532.8
144
OSC IN
2137.5
532.8
177
VSSAUX
-67.5
532.8
145
Vsns_Slave
2092.5
532.8
178
SDA_OUT
-157.5
532.8
146
TEST_VREF
1777.5
532.8
179
SDIN_SDAIN
-202.5
532.8
147
VSSAUX
1732.5
532.8
180
SDOUT
-247.5
532.8
148
SA1
1687.5
532.8
181
SCLK_SCL
-337.5
532.8
149
SA0
1642.5
532.8
182
D7
-382.5
532.8
150
M/S
1597.5
532.8
183
D6
-427.5
532.8
151
EXT_SET
1552.5
532.8
184
D5
-472.5
532.8
152
SEL3
1507.5
532.8
185
D4
-517.5
532.8
153
SEL2
1462.5
532.8
186
D3
-562.5
532.8
154
SEL1
1417.5
532.8
187
D2
-607.5
532.8
155
ICON
1372.5
532.8
188
D1
-652.5
532.8
156
VDD1
1327.5
532.8
189
D0
-697.5
532.8
157
VDD1
1282.5
532.8
190
VSSAUX
-742.5
532.8
158
VDD1
1237.5
532.8
191
TEST_MODE
-1102.5
532.8
159
VDD1
1192.5
532.8
192
VSS
-1147.5
532.8
160
VDD1
1147.5
532.8
193
VSS
-1192.5
532.8
161
VDD1
1102.5
532.8
194
VSS
-1237.5
532.8
162
VDD1
1057.5
532.8
195
VSS
-1282.5
532.8
163
VDD1
1012.5
532.8
196
VSS
-1327.5
532.8
164
VDD2
967.5
532.8
197
VSS
-1372.5
532.8
165
VDD2
922.5
532.8
198
VSS
-1417.5
532.8
75/79
Pad coordinates
STE2004S
Table 29. Pad coordinates
No
Pad placements
No
Name
X
Y
Pad placements
Name
X
Y
199
VSS
-1462.5
532.8
220
R23
-2773.8
292.5
200
VSS
-1507.5
532.8
221
R22
-2773.8
247.5
201
VSS
-1552.5
532.8
222
R21
-2773.8
202.5
202
VSS
-1597.5
532.8
223
R20
-2773.8
157.5
203
VSS
-1642.5
532.8
224
R19
-2773.8
112.5
204
VLCD_SNS
-1867.5
532.8
225
R18
-2773.8
67.5
205
VLCD
-1912.5
532.8
226
R17
-2773.8
22.5
206
VLCD
-1957.5
532.8
227
R16
-2773.8
-22.5
207
VLCD
-2002.5
532.8
228
R15
-2773.8
-67.5
208
VLCD
-2047.5
532.8
229
R14
-2773.8
-112.5
209
VLCD
-2092.5
532.8
230
R13
-2773.8
-157.5
210
OSC_OUT
-2227.5
532.8
231
R12
-2773.8
-202.5
211
FR_OUT
-2272.5
532.8
232
R11
-2773.8
-247.5
212
R31
-2497.5
532.8
233
R10
-2773.8
-292.5
213
R30
-2542.5
532.8
234
R9
-2773.8
-337.5
214
R29
-2587.5
532.8
235
R8
-2773.8
-382.5
215
R28
-2632.5
532.8
236
R7
-2773.8
-427.5
216
R27
-2773.8
472.5
237
R6
-2773.8
-472.5
217
R26
-2773.8
427.5
218
R25
-2773.8
382.5
219
R24
-2773.8
337.5
1. I2C bus AC characteristics are tested by correlation
Table 30. Alignment marks coordinates
76/79
Marks
X
Y
mark1
-2780.55
-539.55
mark2
2780.55
-539.55
mark3
-2160.0
539.55
mark4
484.89
539.55
STE2004S
Pad coordinates
Figure 76. Alignment marks dimensions
35 µm
85 µm
Table 31. Bumps
Dimensions
Bumps size
28µmX97µmX17.5µm
Pad size
35µm X 104µm
Pad pitch
45µm
Spacing between bumps
17µm
Table 32. Die mechanical dimensions
Die Size (X x Y)
5.815mm x 1.333mm
Wafers thickness
500µm
77/79
Ordering information
9
STE2004S
Ordering information
Table 33. Ordering information
Part numbers
STE2004S DIE2
10
Type
Bumped dice on waffle pack
Revision history
Table 34. Document revision history
78/79
Date
Revision
Changes
24-Jan-2006
1
Initial release.
12-Dec-2006
2
– Junction temperature range in Table 26: Absolute maximum
ratings set to: -25 to + 85 and added a footnote.
– Globally set Tamb = 25°C
– Moved Table 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 from
Chapter 6: ID-number to Chapter 5: Instruction set where Table 8
and Table 9 are referenced.
– Ordering information moved from cover page to Chapter 9.
31-Jan-2007
3
Added Chapter 1: Block diagram and corrected the document title.
STE2004S
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79/79