STMICROELECTRONICS STE2002

STE2002
81 x 128 single-chip LCD controller/driver
Features
– Eight selectable temperature compensation
coefficients
■
104 x 128 bits Display Data RAM
■
Programmable MUX rate
■
Programmable frame rate
■
■
Designed for chip-on-glass (COG) applications
■
Low power consumption, suitable for battery
operated systems
X,Y Programmable carriage return
■
Logic supply voltage range from 1.7 to 3.6V
■
Dual partial display mode
■
■
Row by Row Scrolling
High voltage generator supply voltage range
from 1.75 to 4.2V
■
Automatic data RAM Blanking procedure
■
■
Selectable Input interface:
– I2C Bus Fast and Hs-mode (read and write)
– Parallel Interface (read and write)
– Serial Interface (read and write)
Display supply voltage range from 4.5 Vto
14.5V
■
Backward compatibility with STE2001
■
Fully Integrated oscillator requires no external
components
■
CMOS compatible inputs
■
Fully integrated configurable LCD bias voltage
generator with:
– Selectable multiplication factor (up to 6X)
– Effective sensing for High Precision Output
Description
The STE2002 is a low power CMOS LCD
controller driver. Designed to drive a 81 rows by
128 columns graphic display, provides all
necessary functions in a single chip, including onchip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption. The
STE2002 features three standard interfaces
(Serial, Parallel & I2C) for ease of interfacing with
the host microcontroller.
Block diagram
CO to C127
OSC_IN
TIMING
GENERATOR
OSC
OSC_OUT
R0 to R80
ICON
COLUMN
DRIVERS
ROW
DRIVERS
DATA
LATCHES
SHIFT
REGISTER
CLOCK
BIAS VOLTAGE
GENERATOR
VLCDIN
VLCDSENSE
HIGH VOLTAGE
GENERATOR
VLCDOUT
104 x 128
RAM
RESET
RES
VSSAUX
SCROLL
LOGIC
TEST_1_14
TEST
VDD1,2
DATA
REGISTER
VSS
INSTRUCTION
REGISTER
ICON_MODE
EXT
BSY_FLG
DISPLAY
CONTROL
LOGIC
SEL1,2
SA1
I2CBUS
SAO
December 2006
SCL
SDA_IN
SOUT
PARALLEL
SDA_OUT DB0 to DB7 E
R/W PD/C SCE
Rev 3
SERIAL
SDIN
SCLK
SD/C
1/61
www.st.com
61
Contents
STE2002
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Supplies voltages and grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Internal supply voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Bias levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
LCD voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6
Temperature coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Display data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
4.1
Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Power down (PD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
Memory blanking procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Checker board procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5
Scrolling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6
Dual partial display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1
6
7
2/61
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STE2002
Contents
8
Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3/61
Pin description
STE2002
1
Pin description
Table 1.
Pin description
N°
Pad
Type
Function
R0 to R80
129-169
282-322
O
LCD Row Driver Output
ICON
323
O
ICON Row Driver
C0 to C127
1-128
O
LCD Column Driver Output
VSS
236-255
GND
VDD1
188-199
Supply IC Positive Power Supply
VDD2
200-211
Supply Internal Generator Supply Voltages.
VLCDIN
261-270
Supply LCD Supply Voltages for the Column and Row Output Drivers.
VLCDOUT
273-282
Supply Voltage Multiplier Output
VLCDSENSE
271-272
Supply
VSSAUX
180, 231,
218
O
Ground Reference for Selection Pins Configuration
SEL1,2
184,185
I
Interface Mode Selection
Ground pads.
Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine
Tuning
Extended Instruction Set Selection
EXT
183
I
Ext pad config
Instruction set selected
VSS or VSSAUX
BASIC
VDD1
EXTENDED
ICON ROW Management
ICON_MOD
E
186
Icon mode pad config
Icon mode status
VSS or VSSAUX
DISABLED
VDD1
ENABLED
I
SDA_IN
234
I
I2C Bus Data In
SDA_OUT
232
O
I2C Bus Data Out
SCL
235
I
I2C bus Clock
SA0
182
I
I2C Slave Address BIT 0
SA1
181
I
I2C Slave Address BIT 1
OSCIN
187
I
External Oscillator Input
OSCOUT
260
O
Internal/External Oscillator Out
RES
230
I
Reset Input. Active Low.
DB0 to DB7
220-227
I/O
4/61
Parallel Interface 8 Bit Data Bus
STE2002
Table 1.
Pin description
Pin description (continued)
N°
Pad
Type
Function
R/W
219
I
Parallel Interface Read & Write Control Line
E
229
I
Parallel Interface Data Latch Signal.
PD/C
228
I
Parallel Interface Data/Command Selector
SDIN
214
I
Serial Interface Data Input
SCLK
217
I
Serial Interface Clock
SCE
216
I
Serial Interface ENABLE. When Low the Incoming Data are Clocked In.
SD/C
215
I
Serial Interface Data/Command Selector
SOUT
213
O
Serial Out
BSYFLG
212
O
Active Procedure Flag. Notice if There is an ongoing Internal Operation or an
active reset. Active Low.
Test Pads. - A 50kohm pull-down resistor is added on input pis.
T1 to T14
170-179,
256-259
I/O
Test Num.
Pin Configuration
TEST_1
TEST_2
TEST_3
TEST_4
OPEN
TEST_5
TEST_6
TEST_7
TEST_8
TEST_9
TEST_10
VSS / VSSAUX
TEST_11
TEST_12
TEST_13
TEST_14
VSS / VSSAUX
5/61
Pin description
ROW 34
Chip mechanical drawing
ICON
ROW 0
Figure 1.
STE2002
MARK_1
COL
0
ROW 35
ROW 39.
STE2002
VLCDOUT
VLCDOUT
VLCDSENSE
VLCDSENSE
VLCDIN
VLCDIN
MARK_3
OSCOUT
TEST_14
TEST_13
TEST_12
TEST_11
VSS
SCL
SDAIN
SDAOUT
COL 63
VSSAUX
RES
(0,0)
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
Y
COL 64
X
SCLK
SCE
SD/C
SDIN
SDOUT
MARK_4
BSY_FLG
VDD2
VDD2
VDD1
VDD1
OSCIN
ICON_MODE
SEL1
SEL2
EXT_SET
SA0
SA1
VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
ROW 80/ICON
ROW 79
COL 127
ROW 76
6/61
ROW 75
ROW 40
MARK_2
STE2002
Pin description
Figure 2.
Improved ALTH & PLESKO driving method
VLCD
V2
V3
∆V1(t)
∆V2(t)
ROW 0
R0 (t)
V4
V5
VSS
VLCD
V2
V3
ROW 1
R1 (t)
V4
V5
VSS
VLCD
V2
V3
COL 0
C0 (t)
V4
V5
VSS
VLCD
V2
V3
COL 1
C1 (t)
V4
V5
VSS
VLCD - VSS
V3 - VSS
Vstate1(t)
VLCD - V2
0V
V3 - VSS
V4 - V5
0V
VSS - V5
V4 - VLCD
VSS - VLCD
VLCD - VSS
V3 - VSS
Vstate2(t)
VLCD - V2
0V
V3 - VSS
V4 - V5
0V
VSS - V5
V4 - VLCD
VSS - VLCD
..... 64 0 1 2 3 4 5 6 7 8 9 .......
0 1 2 3 4 5 6 7 8 9 .......
FRAME n
∆V1(t) = C1(t) - R0(t)
∆V2(t) = C1(t) - R1(t)
..... 64
FRAME n + 1
D00IN1154
7/61
Circuit description
STE2002
2
Circuit description
2.1
Supplies voltages and grounds
VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage
generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the
IC. VDD1 supply voltage could be different form VDD2.
2.2
Internal supply voltage generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid
Crystal Display supply voltage generation. The multiplying factor can be programmed to be:
Auto, X6, X5, X4, X3, X2, using the ’set CP Multiplication’ Command. If Auto is set, the
multiplying factor is automatically selected to have the lowest current consumption in every
condition. This make possible to have an input voltage that changes over time and a
constant VLCD voltage. The output voltage (VLCDOUT) is tightly controlled through the
VLCDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change
with temperature) can be programmed using the bits TC1 and TC0 and T2,T1 & T0. This will
ensure no contrast degradation over the LCD operating range. Using the internal charge
pump, the VLCDIN and VLCDOUT pads must be connected together. An external supply could
be connected to VLCDIN to supply the LCD without using the internal generator. In such
event the VLDCOUT and VLCDSENSE must be connected to GND and the internal voltage
generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition).
2.3
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock
for the Display System. When used the OSC pad must be connected to VDD1 pad. An
external oscillator could be used and fed into the OSC pin. An oscillator out is provided on
the OSCOUT Pad to cascade two or more drivers
2.4
Bias levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are
generated. The ratios among these levels and VLCD, should be selected according to the
MUX ratio (m). They are established to be (Fig. 4):
n+3
n+2
2
1
V LCD, ------------- V LCD , ------------- V LCD , ------------- V LCD , ------------- V LCD ,V SS
n+4
n+4
n+4
n+4
8/61
STE2002
Circuit description
Figure 3.
Bias level generator
VLCD
R
n+3
·VLCD
n+4
R
n+2
·VLCD
n+4
nR
2
·VLCD
n+4
R
1
·VLCD
n+4
R
VSS
D00IN1150
thus providing an 1/(n+4) ratio, with n calculated from:
=
m–
For m = 81, n = 6 and an 1/10 ratio is set.
For m = 65, n =5 and an 1/9 ratio is set.
The STE2002 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio
as shown below:
Table 2.
Bias ratio programming
BS2
BS1
BS0
n
0
0
0
7
0
0
1
6
0
1
0
5
0
1
1
4
1
0
0
3
1
0
1
2
1
1
0
1
1
1
1
0
The following table Bias Level for m = 65 and m = 81 are provided:
Table 3.
Bias level
Symbol
m = 65 (1/9)
m = 81 (1/10)
V1
VLCD
VLCD
V2
8/9*VLCD
9/10*VLCD
V3
7/9*VLCD
8/10*VLCD
V4
2/9*V VLCD
2/10*VLCD
V5
1/9 *VLCD
1/10*VLCD
V6
VSS
VSS
9/61
Circuit description
2.5
STE2002
LCD voltage generation
The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register
content according to the following formula:
VLCD(T=To) = VLCDo = (Ai+VOP · B)
(i=0,1,2)
with the following values:
Table 4.
LCD voltage values
Symbol
Value
Unit
Note
Ao
2.95
V
PRS = [0;0]
A1
6.83
V
PRS = [0;1]
A2
10.71
V
PRS = [1;0]
B
0.0303
V
To
27
°C
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register
and PRS bits are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth)
and of the Multiplexing Rate. A general expression for this is:
1+ m
V LCD = --------------------------------------- ⋅ V th
1
2 ⋅ ⎛ 1 – ---------⎞
⎝
m⎠
For MUX Rate m = 65 the ideal VLCD is:
VLCD(to) = 6.85 · Vth
then:
( 6.85 ⋅ V th – A i )
V op = -------------------------------------------0.03
10/61
STE2002
2.6
Circuit description
Temperature coefficient
As the viscosity, and therefore the contrast, of the LCD are subject to change with
temperature, there's the need to vary the LCD Voltage with temperature. The STE2002
provides the possibility to change the VLCD in a linear fashion against temperature with
eight different Temperature Coefficient selectable through the T2, T1 and T0 bits. Only four
of them are available with basic instruction set (TC1 & TC0 Bits).
Table 5.
Temperature coefficients
Name
TC1
TC0
Value
Unit
TC0
0
0
-0.0· 10-3
1/ °C
-3
1/°C
TC2
0
1
-0.7 · 10
TC3
1
0
-1.05· 10-3
1/°C
1
10-3
1/°C
TC6
Table 6.
1
-2.1 ·
Temperature coefficients
Name
TC2
TC1
TC0
Value
Unit
TC0
0
0
0
-0.0· 10-3
1/ °C
TC1
0
TC2
0
0
1
1
0
-0.35 ·
10-3
1/°C
-0.7 ·
10-3
1/°C
10-3
1/°C
TC3
0
1
1
-1.05·
TC4
1
0
0
-1.4 · 10-3
1/°C
1
-1.75·
10-3
1/°C
-2.1 ·
10-3
1/°C
-2.3·
10-3
1/°C
TC5
1
TC6
1
TC7
Figure 4.
1
0
1
0
1
1
LCD voltage
VLCD
B
A2
A0 + B
A1
A0
00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h ….
PRS = [0;0]
7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh
PRS = [0;1]
PRS = [1;0]
VO
Finally, the VLCD voltage at a given (T) temperature can be calculated as:
VLCD(T) = VLCDo · [1 + (T-To) · TC]
11/61
Display data RAM
3
STE2002
Display data RAM
The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized
into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be
used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided
(see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y12 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the
left of the memory map. The X pointer is increased after each byte written. After the last
column address (X=X-Carriage), Y address pointer is set to jump to the following bank and
X restarts from X=0. (Fig. 6)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left
of the memory map. The Y pointer is increased after each byte written. After the last Y bank
address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from
Y=0 (Fig. 7).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the
right of the memory map. The X pointer is increased after each byte written. After the last
column address (X=X-Carriage), Y address pointer is set to jump to the next bank and X
restarts from X=0 (fig. 8).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the last Y
bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts
from Y=0 (fig. 9).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jump to the cell with address (X;Y) = (0;0) (Fi. 10, 11, 12 & 13).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.14) or on the
bottom (D0=1, Fig. 15).
The STE2002 provides also means to alter the normal output addressing. A mirroring of the
Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect
the content of the memory RAM. It is only related to the visualization process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON
Mode=0 the Icon Row is like the other graphic lines and is mirrored and scrolled.
Four are the multiplex ratio available when the partial display mode is disabled (MUX 33,
MUX 49, MUX 65 and MUX 81).
Only a subset of writable rows are output on Row drivers.
When Y-Carriage<MUX/8, if Mux 65 is selected only the first 65 memory rows are
visualized, if Mux 49 is selected only the first 49 memory rows are visualized, if Mux 33 is
selected only the first 33 memory rows are visualized. All unused Row and Column drivers
must be left floating.
When Y-Carriage<MUX/8, the icon Bank is located to BANK 10 in MUX 81 Mode, to
BANK8 in MUX 65 Mode, to BANK 6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode.
When Y-Carriage>MUX/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to
select which lines of DDRAM are connected on the output drivers. The DDRAM rows to
visualized can be selected in the 0-Y-Carriage*8 range using the scrolling function.
12/61
STE2002
Display data RAM
When Y-Carriage>MUX lines, the icon row is moved in DDRAM to the first row of the YCARRIAGE Return BANK even if it is always connected on the same output Driver.
When MY=0, the icon Row is output on R80 in mux 81 mode, on R72 in MUX 65, on R64 in
MUX49 and on R56 in MUX 33.
When MY=1, and ICON MODE=1, the icon Row is output on R80 in mux 81 mode, on R72
in MUX 65, on R64 in MUX49 and on R56 in MUX 33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.
When ICON MODE =1, the Memory ICON Row content is output on ICON Pad.
If Not Used ICON Pad must be left floating.
Figure 5.
Automatic data RAM writing sequence with V=0 and Data RAM Normal
Format (MX=0)(a)
0
1
2
3
124
125
126
127
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
Figure 6.
Automatic data RAM writing sequence with V=1 and Data RAM Normal
Format (MX=0)(a)
0
1
2
3
124
125
126
127
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
Figure 7.
Automatic data RAM writing sequence with V=0 and Data RAM Mirrored
Format (MX=1(a)
127
126
125
124
3
2
1
0
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
a. X Carriage=127; Y-Carriage = 12
13/61
Display data RAM
Figure 8.
STE2002
Automatic data RAM writing sequence with V=1 and Data RAM mirrored
format (MX=1)(a)
127
126
125
124
3
2
1
0
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
Figure 9.
Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=0)
0
1
2
X CARR
3
124
125
126 127
BANK 0
BANK 1
BANK 2
Y CARR
BANK 11
BANK 12
Figure 10. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=0)
X CARR
0
1
2
3
124
125
126 127
BANK 0
BANK 1
BANK 2
Y CARR
BANK 11
BANK 12
Figure 11. Automatic data RAM writing sequence with X-Y carriage return (V=0;
MX=1)
X CARR
127
BANK 0
BANK 1
BANK 2
Y CARR
BANK 11
BANK 12
14/61
126
125
124
3
2
1
0
STE2002
Display data RAM
Figure 12. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=1)
X CARR
127
126
125
124
3
2
1
0
BANK 0
BANK 1
BANK 2
Y CARR
BANK 11
BANK 12
Figure 13. Data RAM Byte organization with D0 = 0
MSB
0
LSB
1
2
3
124
125
126
127
124
125
126
127
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
Figure 14. Data RAM Byte organization with D0 = 1
LSB
0
MSB
1
2
3
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
Figure 15. Memory rows vs. row drivers mapping with MY=0, MUX81, icon mode=0,1
ROW DRIVER
ICON MODE=1
ROW DRIVER
ICON MODE=0
R0
R1
R2
R3
R0
R1
R2
R3
PHYSICAL MEMORY ROW
0
1
2
3
124
125
126
127
ROW 0
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R 79
R 80
R 79
R 80
ROW 79
ROW 80
ICON ROW
ICON
15/61
Display data RAM
STE2002
Figure 16. Memory rows vs. row drivers mapping with MY=0, MUX 81, scroll pointer = +3, icon
mode=1
ROW DRIVER
ICON MODE=1
PHYSICAL MEMORY ROW
0
R0
R1
R2
R3
1
2
3
124
125
126
127
ROW 0
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R 76
R 77
R 78
R 79
R 80
ROW 79
ROW 80
ICON ROW
ICON
Figure 17. Memory rows vs. row drivers mapping with MY=0, MUX 81, scroll
pointer=+3, icon mode=0
ROW DRIVER
ICON MODE=0
PHYSICAL MEMORY ROW
1
0
2
3
124
125
126
127
ROW 0
R0
R1
R2
R3
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R 76
R 77
R 78
R 79
R 80
ROW 79
ROW161
80
ROW
ICON ROW
ICON
Figure 18. Memory rows vs. row drivers mapping with MUX 65 Y-CARRIAGE<=8
scroll pointer=0, icon mode=1
ROW DRIVER
PHYSICAL MEMORY ROW
0
R0
1
2
3
124
125
126
127
ROW 0
ROW 1
R 30
R 31
ROW 31
N.C.
N.C.
R 40
ROW 32
R 71
R 72
ROW 63
ROW 64
R 79
R 80
ROW 96
ICON
16/61
Y-CARRIAGE
ICON ROW
STE2002
Display data RAM
Figure 19. Memory rows vs. row drivers mapping with MUX65, Y-CARRIAGE>8,
scroll pointer=0, icon mode=1
ROW DRIVER
PHYSICAL MEMORY ROW
0
R0
ROW 0
R 31
R 32
ROW 32
R 40
ROW 63
1
2
3
124
125
126
127
ROW 31
N.C.
R 71
R 72
N.C.
ICON ROW
ROW 75
ROW 76
R 79
R 80
Y-CARRIAGE
ROW 96
ICON
Figure 20. Memory rows vs. row drivers mapping with MUX65, Y-CARRIAGE>8,
scroll pointer=3, icon mode=1,
ROW DRIVER
PHYSICAL MEMORY ROW
0
R0
R 30
R 31
2
3
124
125
126
127
ROW 1
ROW 2
ROW 33
N.C.
R 40
R 71
R 72
N.C.
1
ROW 0
ROW 34
ROW 66
ICON ROW
ROW 75
ROW 76
R 79
R 80
Y-CARRIAGE
ROW 96
ICON
Figure 21. Memory Rows vs. Row drivers mapping with MY=1, MUX81, icon mode
0,1 scroll pointer=0
ROW DRIVER
ICON MODE=1
ROW DRIVER
ICON MODE=0
R 79
R 78
R 80
R 79
PHYSICAL MEMORY ROW
0
1
2
3
124
125
126
127
ROW 0
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R2
R1
R0
R 80
R3
R2
R1
R0
ICON
ICON
ROW 79
ROW 80
ICON ROW
17/61
Display data RAM
STE2002
Figure 22. Memory rows vs. row drivers mapping with MY=1, MUX81,
scroll offset = +3, icon mode =0
ROW DRIVER
ICON MODE=0
PHYSICAL MEMORY ROW
0
R 80
R 78
R 79
R 77
R 76
1
2
3
124
125
126
127
ROW 0
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R1
R0
ROW 79
ROW 80
ICON ROW
ICON
Figure 23. Memory rows vs. row drivers mapping with MY=1, MUX81,
scroll offset= +3, icon mode =1
ROW DRIVER
ICON MODE=1
SCROLL OFFSET +3
PHYSICAL MEMORY ROW
0
R 79
R 78
R 77
ROW 0
R 76
ROW 3
1
2
3
124
125
126
127
ROW 1
ROW 2
Y-CARRIAGE
R1
R0
R 80
ROW 79
ROW 80
ICON ROW
ICON
Figure 24. Row drivers vs. LCD panel interconnection in MUX81 mode
ICON
81x128
MUX 81 Mode
COLUMN DRIVERS
ROW DRIVERS
STE2002
R35
R36
R37
R38
R39
R80/ICON
R79
R78
R77
R76
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
ROW DRIVERS
LR0012
18/61
STE2002
Display data RAM
Figure 25. Row drivers vs. LCD panel interconnection in MUX65 mode
ICON
65x128
MUX 65 Mode
COLUMN DRIVERS
ROW DRIVERS
STE2002
R35
R36
R37
R38
R39
R80/ICON
R79
R78
R77
R76
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
ROW DRIVERS
LR0014
Figure 26. Row drivers vs. LCD panel interconnection in MUX49 mode
ICON
49x128
MUX 49 Mode
COLUMN DRIVERS
ROW DRIVERS
STE2002
R35
R36
R37
R38
R39
R80/ICON
R79
R78
R77
R76
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
ROW DRIVERS
LR0013
19/61
Display data RAM
STE2002
Figure 27. Row drivers vs. LCD panel interconnection in MUX33 mode
ICON
33x128
MUX 33Mode
COLUMN DRIVERS
ROW DRIVERS
STE2002
R35
R36
R37
R38
R39
R80/ICON
R79
R78
R77
R76
20/61
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
R 8
R 9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
ROW DRIVERS
LR0106
STE2002
4
Instruction set
Instruction set
Two different instructions formats are provided:
- With D/C set to LOW
commands are sent to the Control circuitry.
- With D/C set to HIGH
the Data RAM is addressed.
Two different instruction set are embedded: the STE2001-like instruction set and the
extended instruction set. To select the STE2001-like instruction set the EXT pad has to be
connected to a logic LOW (connect to VSS). To select the extended instruction the EXT pad
has to be connected to a logic HIGH (connect to VDD1).
The instructions have the syntax summarized in Table 10, (basic-set) and Table 11
(extended set).
4.1
Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is
not defined. A Reset pulse on RES pad (active low) re-initialize the internal registers content
(see Table 10, Table 11, Table 12). Applying a reset pulse, every on-going communication
with the host controller is interrupted. After the power-on, the Software Reset instruction can
be used to re-load the reset configuration into the internal registers
The default configurations is: .
- Horizontal addressing (V = 0)
- Multiplexing Ratio (M[1:0]=0)
- Normal instruction set (H[1:0] = 0)
- Frame Rate (FR[1:0]=”75Hz”)
- Normal display (MX = MY = 0)
- Power Down (PD = 1)
- Display blank (E = D = 0)
- Dual Partial Display Disabled (PE=0)
- Address counter X[6: 0] = 0 and Y[4: 0] = 0
- VOP=0
- Temperature coefficient (TC[1: 0] = 0)
- Bias system (BS[2: 0] = 0)
A MEMORY BLANK instruction can be executed to clear the RAM content.
4.2
Power down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and
VLCD generator are OFF (VLCDOUT output is discharged to VSS, and then is possible to
disconnect VLCDOUT). The internal Oscillator is in off state. An external clock can be
provided. The RAM contents is not cleared.
21/61
Instruction set
4.3
STE2002
Memory blanking procedure
This instruction allows to fill the memory with "blank" patterns, in order to delete patterns
randomly generated in memory when starting up the device. This instruction substitutes
(128X13) single "write" instructions. It is possible to program "Memory Blanking Procedure"
only under the following conditions:
- PD bit
=0
The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the
procedure is running). Any instruction programmed with BSY_FLG LOW will be ignored that
is, no instruction can be programmed for a period equivalent to 128X13 internal write cycles
(128X13X1/fclock). The start of Memory blanking procedure will be between one and two
fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK
rising edge for the Serial interface, last SCL rising edge for the I2C interface).
4.4
Checker board procedure
This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended
to developers, who can now simply obtain complex module test configuration by means of a
single instruction. It is possible to program "Checker Board Procedure" only under the
following conditions:
–
PD bit = 0
The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the
procedure is running. Any instruction programmed with BSY_FLG LOW will be ignored, that
is, no instruction can be programmed for a period equivalent to 128X13 internal write cycles
(128X13X1/fclock). The start of Memory blanking procedure will be between one and two
fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK
rising edge for the Serial interface, last SCL rising edge for the I2C interface).
4.5
Scrolling function
The STE2002 can scroll the graphics display in units of raster-rows. The scrolling function is
achieved changing the correspondence between the rows of the logical memory map and
the output row drivers. The scroll function doesn't affect the data ram content. It is only
related to the visualization process. The information output on the drivers is related to the
row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling
means reading the matrix starting from a row that is sequentially increased or decreased.
After every scrolling command the offset between the memory address and the memory
scanning pointer is increased or decreased by one. The offset range changes in accordance
with MUX Rate. After 80th/81th scrolling commands in MUX 81 mode, or after the 64th/65th
scrolling commands in mux 65 mode, or after 48nd/49rd scrolling command in MUX 49
mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the
memory address and the memory scanning pointer is again zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the
memory address and the memory scanning pointer
The Icon Row is not scrolled if ICON MODE =1. If ICON MODE=0 the last row is like a
general purpose row and it is scrolled as other rows.
If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is
scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by
one and the raster is scrolled from bottom-up.
22/61
STE2002
Instruction set
Table 7.
4.6
Scrolling function
Mux rate
Icon mode
Offset
range
MUX 33
1
0-31
ICON ROW NOT SCROOLED
R56
MUX 33
0
0-32
33 LINE GRAPHIC MATRIX
R56
MUX 49
1
0-47
ICON ROW NOT SCROOLED
R64
MUX 49
0
0-48
49 LINE GRAPHIC MATRIX
R64
MUX 65
1
0-63
ICON ROW NOT SCROOLED
R72
MUX 65
0
0-64
65 LINE GRAPHIC MATRIX
R72
MUX 81
1
0-79
ICON ROW NOT SCROOLED
R80
MUX 81
0
0-80
81 LINE GRAPHIC MATRIX
R80
Description
Icon row driver with
MY=0
Dual partial display
If the PE Bit is set to a logic one the dual partial display mode is enabled.
Eight partial display modes are available. The offset of the two partial display zones is row
by row programmable. The Icon row is accessed last in each partial display frame.
Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0],
BS[2:0], CP[2:0].). This allows switching from normal mode to partial display mode applying
one instruction. The HV generator is automatically re configured using the parameters
related to the enabled mode. The parameters of the two sets of registers with the same
function are located in the same position of the instruction set. The registers related to the
normal mode are accessible when normal mode (PE=0) is selected, the others are
accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0],
BS[2:0], CP[2:0] values the instruction flow proposed in Fig.46 must be followed. To setup
Partial Display Sectors Start Address and Partial Display Mode no particular instruction flow
has to be followed.
Table 8.
Dual partial display
PD2 PD1 PD0
Section 1
Section2
0
0
0
0
8 + Icon Row
0
0
1
8
0 + Icon Row
0
1
0
8
8 + Icon Row
0
1
1
0
16 + Icon Row
1
0
0
16
0 + Icon Row
1
0
1
8
16 + Icon Row
1
1
0
16
8 + Icon Row
1
1
1
16
16 + Icon Row
Reset state
000
23/61
Bus interfaces
5
STE2002
Bus interfaces
To provide the widest flexibility and ease of use the STE2002 features three different
methods for interfacing the host Controller. To select the desired interface the SEL1 and
SEL2 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect
to VDD). All the I/O pins of the unused interfaces must be connected to GND.
All interfaces are working while the STE2002 is in Power Down
.
Table 9.
5.1
Bus interface
SEL2
SEL1
Interface
Note
0
0
I2C
Read and Write; Fast
and High Speed Mode
0
1
Serial
Read and Write
1
0
Parallel
Read and Write
1
1
Not Used
I2C interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different Ics. It consists of two lines: one bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and the stop conditions is not
limited. The information is transmitted byte-wide and each receiver acknowledges with the
ninth bit.
24/61
STE2002
Bus interfaces
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the signals is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master receiver must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and
hold time must be taken into account. A master receiver must signal an end-of-data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAOUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the STE2002 will not be able to
create a valid logic 0 level. By splitting the SDA input from the output the device could be
used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2002 is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in
Hs-mode without detecting the master code.
Figure 28. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
CHANGE OF
DATA ALLOWED
START
CONDITION
STOP
CONDITION
D00IN1151
Figure 29. Acknowledgment on the I2C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
D00IN1152
25/61
Bus interfaces
5.1.1
STE2002
Communication protocol
The STE2002 is an I2C slave. The access to the device is bi-directional since data write and
status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits
(01111). The two least significant bit of the slave address are set by connecting the SA0 and
SA1 inputs to a logic 0 or to a logic 1.
To start the communication between the bus master and the slave LCD driver, the master
must initiate a START condition. Following this, the master sends an 8-bit byte, shown in Fig.
30, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device select
Code, and the 1-bit Read/Write Designator (R/W).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore
the I2C-bus transfer.
Writing mode
If the R/W bit is set to logic 0 the STE2002 is set to be a receiver. After the slaves
acknowledge one or more command word follows to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines the Co
and D/C values, the second is a data byte (fig 31). The Co bit is the command MSB and
defines if after this command will follow one data byte and an other command word or if will
follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines
whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte will be stored in the data RAM at the location specified by the
data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside
the STE2002 Display RAM starting at the address specified by the data pointer. The data
pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
Every byte must be acknowledged by all addressed units.
Reading mode
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If
the D/C bit sent during the last write access, is set to a logic 0, the byte read is the status
byte.
26/61
STE2002
Bus interfaces
Figure 30. Communication protocol
WRITE MODE
STE2002 ACK
STE2002 ACK
S S
S 0 1 1 1 1 A A 0 A 1 DC Control Byte A
1 0
R/W Co
SLAVE ADDRESS
STE2002 ACK
DATA Byte
A 0 DC Control Byte A
Co
COMMAND WORD
STE2002 ACK
LAST
CONTROL BYTE
STE2002 ACK
DATA Byte
A P
N> 0 BYTE
MSB........LSB
READ MODE
STE2002 ACK
S S
S 0 1 1 1 1 A A 1 A
1 0
R/W
5.2
MASTER ACK
P
S S R
0 1 1 1 1 A A /
1 0 W
STE2002
SLAVE ADDRESS
C D
0 0 0 0 0 0 A
o C
CONTROL BYTE
Serial interface
The STE2002 serial Interface is a bidirectional link between the display driver and the
application supervisor.
It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one
for the peripheral enable (SCE) and one for mode selection (SD/C).
The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the
serial peripheral power consumption is zero. While SCE pin is high the serial interface is
kept in reset.
The STE2002 is always a slave on the bus and receive the communication clock on the
SCLK pin from the master.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the
positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C
=1);it is read on the eighth SCLK clock pulse during every byte transfer.
If SCE stays low after the last bit of a command/data byte, the serial interface expects the
MSB of the next byte at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM
and all the internal registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SOUT can be read only the driver I2C slave address. The Command sequence
that allows to read I2C slave address is reported in Fig. 34 & 35. SOUT is in High impedance
in steady state and during data write.
It is possible to short circuit DOUT and SDIN and read I2C address without any additional
lines.
27/61
Bus interfaces
STE2002
Figure 31. Serial bus protocol - one byte transmission
SCE
D/C
SCLK
SDIN
MSB
LSB
D00IN1159
Figure 32. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
Figure 33. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
DB7
DB6
DB5
D00IN1160
SOUT
High-Z
Command Write
28/61
DB7
DB6
DB5
DB4
DB3
I2C Address Read
DB2
DB1
DB0
High-Z
STE2002
Bus interfaces
Figure 34. Reading sequence
READING SEQUENCE
Write a "00000000" Instruction
SOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and
Read the I2C Address or Status Byte On SOUT
1
SOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read.
LR0078
5.3
Parallel interface
The STE2002 parallel Interface is a bidirectional link between the display driver and the
application supervisor. It consists of eleven lines: eight data lines (from DB7 to DB0) and
three control lines. The control lines are: enable (E) for data latch, PD/C for mode selection
and R/W for reading or writing.
The data lines and the control line values are internally latched on E rising edge (fig. 50).
When the parallel interface is selected, if R/W line is set to “one”, D0-D7 lines are configured
as output drivers (low impedence) and it is possible to read the driver I2C address (Fig. 51)
Table 10.
STE2001-like instruction set
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
H=0 or H=1
0
0
0
0
0
0
0
0
0
0
Read I2C Address
(with Serial Interface
only)
Function Set
0
0
0
0
1
MX
MY
PD
V
H[0]
Power Down
Management; Entry
Mode;
Read Status Byte
0
1
PD
A1
A2
D
E
MX
MY
DO
(I2C interface only)
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data to RAM
29/61
Bus interfaces
Table 10.
STE2002
STE2001-like instruction set (continued)
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
Memory Blank
0
0
0
0
0
0
0
0
0
1
Starts Memory Blank
Procedure
Scroll
0
0
0
0
0
0
0
0
1
DIR
Scrolls by one Row
UP or DOWN
VLCD Range
Setting
0
0
0
0
0
0
0
1
0
PRS[0]
VLDC programming
range selection
Display Control
0
0
0
0
0
0
1
D
0
E
Select Display
Configuration
Set CP Factor
0
0
0
0
0
1
0
S2
S1
S0
Charge Pump
Multiplication factor
Set RAM Y
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set Horizontal (Y)
RAM Address
Set RAM X
0
0
1
X6
X5
X4
X3
X2
X1
X0
Set Vertical (X) RAM
Address
Checker Board
0
0
0
0
0
0
0
0
0
1
Starts Checker Board
Procedure
Multiplex Select
0
0
0
0
0
0
0
0
1
MUX
Selects MUX factor
TC Select
0
0
0
0
0
0
0
1
TC1
TC0
Set Temperature
Coefficient for VLDC
Output Address
0
0
0
0
0
0
1
DO
A1
A2
Bias Ratios
0
0
0
0
0
1
0
BS2
BS1
BS0
Reserved
0
0
0
1
X
X
X
X
X
X
Set VOP
0
0
1
OP
6
OP
5
OP
4
OP
3
OP
2
OP1
OP0
H=0
H=1
30/61
No function
Set desired Bias
Ratios
Not to be used
VOP register Write
instruction
STE2002
Table 11.
Bus interfaces
Extended instruction set
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
H independent instructions
NOP
0
0
0
0
0
0
0
0
0
0
Read I2C Address
(with Serial
Interface only)
Function Set
0
0
0
0
1
MX
MY
PD
H[1]
H[0]
Power Down
Management; Entry
Mode; Extended
Instruction Set
Read Status
Byte
0
1
PD
0
0
D
E
MX
MY
DO
(I2C interface only)
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data to RAM
H=[0;0] RAM commands
Memory
Blank
0
0
0
0
0
0
0
0
0
1
Scroll
0
0
0
0
0
0
0
0
1
DIR
Scrolls by one Row
UP or DOWN
VLCD Range
Setting
0
0
0
0
0
0
0
1
PRS[1]
PRS[0]
VLDC programming
range selection
Display
Control
0
0
0
0
0
0
1
D
0
E
Select Display
Configuration
Set CP Factor
0
0
0
0
0
1
0
S2
S1
S0
Charge Pump
Multiplication factor
Set RAM Y
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set Horizontal (Y)
RAM Address
Set RAM X
0
0
1
X6
X5
X4
X3
X2
X1
X0
Set Vertical (X)
RAM Address
0
0
0
0
0
0
0
0
0
1
Starts Checker
Board Procedure
0
0
0
0
0
0
0
0
1
V
Vertical Addressing
Mode
TC Select
0
0
0
0
0
0
0
1
TC1
TC0
Set Temperature
Coefficient for VLDC
Data Format
0
0
0
0
0
0
1
DO
0
0
Bias Ratios
0
0
0
0
0
1
0
BS2
BS1
BS0
0
0
0
1
X
X
X
X
X
X
0
0
1
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Starts Memory
Blank Procedure
H=[0;1]
Checker
Board
Set VOP
MSB Position
Set desired Bias
Ratios
Reserved
VOP register Write
instruction
31/61
Bus interfaces
Table 11.
STE2002
Extended instruction set
Instruction
D/C
R/W
B7
B6
B5
B4
B3
B2
B1
B0
Description
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
PE
Partial Enable
0
0
0
0
0
0
0
1
FR1
FR0
Frame rate Control
0
0
0
0
0
0
1
0
M[1]
M[0]
Mux Ratio
0
0
0
0
0
1
0
PD2
PD1
PD0
Partial Display
Config
0
0
0
1
PDY5 PDY4
PDY3
PDY2
PDY1
PDY0
1st Sector Start
Address
0
0
1
PDY6 PDY5 PDY4
PDY3
PDY2
PDY1
PDY0
2nd Sector Start
Address
0
0
0
0
0
0
0
0
0
1
Scrolling Pointer
Reset
0
0
0
0
0
0
0
0
1
X
Not Used
0
0
0
0
0
0
0
1
X
X
Not Used
0
0
0
0
0
0
1
T2
T1
T0
Set Temperature
Coefficient for VLDC
0
0
0
0
0
1
X
X
X
X
Not Used
0
0
0
1
0
0
YC-3
YC-2
YC-1
YC-0
Y-CARRIAGE
RETURN
0
0
1
XC-6
XC-5
XC-4
XC-3
XC-2
XC-1
XC-0
X CARRIAGE
RETURN
H=[1;0]
Partial mode
Software RESET
H=[1;1]
Table 12.
Explanations of symbols
Bit
0
Reset
state
DIR
Scroll by one down
Scroll by one up
PD
Device fully working
Device in power down
1
Horizontal addressing
Vertical addressing
0
MX
Normal X axis addressing
X axis address is mirrored.
0
MY
Image is displayed not vertically mirrored Image is displayed vertically mirrored
0
DO
MSB on TOP
MSB on BOTTOM
0
PE
Partial Display disabled
Partial Display enabled
0
H[0]
Select page 0
Select page 1
0
MUX 33
0
V
MUX MUX 65
32/61
1
STE2002
Bus interfaces
Table 13.
Page number
H[1]
H[0]
0
0
Page 0
0
1
Page 1
1
0
Page 2
1
1
Page 3
Table 14.
Description
Reset state
Page 0
Display mode
D
E
0
0
display blank
0
1
all display segments on
D=0
1
0
normal mode
E=0
1
1
inverse video mode
Table 15.
Description
Frame rate control
FR[1]
FR[0]
0
0
65Hz
0
1
70Hz
1
0
75Hz
1
1
80Hz
Table 16.
Description
Reset state
75Hz
VLCD range selection
PRS[1]
PRS[0]
0
0
0
1
6.78
1
0
10.62
1
1
Table 17.
Reset state
Description
Reset State
2.94
Not Used
Multiplexing ratio
M[1]
M[0]
Description
0
0
49
0
1
65
1
0
81
1
1
Not Used
Reset state
01
33/61
Bus interfaces
STE2002
Table 18.
Temperature coefficient
T2
T1
T0
0
0
0
VLCD temperature Coefficient 0
0
0
1
VLCD temperature Coefficient 1
0
1
0
VLCD temperature Coefficient 2
0
1
1
VLCD temperature Coefficient 3
1
0
0
VLCD temperature Coefficient 4
1
0
1
VLCD temperature Coefficient 5
1
1
0
VLCD temperature Coefficient 6
1
1
1
VLCD temperature Coefficient 7
Table 19.
Reset state
000
TC1 & TC0 temperature coefficients
TC1
TC0
0
0
VLCD temperature Coefficient 0
0
1
VLCD temperature Coefficient 2
1
0
VLCD temperature Coefficient 3
1
1
VLCD temperature Coefficient 6
Table 20.
34/61
Description
Description
Reset state
00
Charge pump multiplication factor
CP2
CP1
CP0
Description
0
0
0
Multiplication Factor X2
0
0
1
Multiplication Factor X3
0
1
0
Multiplication Factor X4
0
1
1
Multiplication Factor X5
1
0
0
Multiplication Factor X6
1
0
1
NOT USED
1
1
0
NOT USED
1
1
1
AUTOMATIC
Reset state
000
STE2002
Bus interfaces
O
Table 21.
Bias ratio
BS2
BS1
BS0
0
0
0
Bias Ratio equal to 7
0
0
1
Bias Ratio equal to 6
0
1
0
Bias Ratio equal to 5
0
1
1
Bias Ratio equal to 4
1
0
0
Bias Ratio equal to 3
1
0
1
Bias Ratio equal to 2
1
1
0
Bias Ratio equal to 1
1
1
1
Bias Ratio equal to 0
Table 22.
Description
Reset state
000
Y carriage return register
Y-C[3] Y-C[2] Y-C[1] Y-C[0]
Description
0
0
0
0
0
0
0
1
Y-CARRIAGE =1
0
0
1
0
Y-CARRIAGE =2
0
0
1
1
Y-CARRIAGE =3
0
1
0
0
Y-CARRIAGE =4
0
1
0
1
Y-CARRIAGE =5
.
.
.
.
1
0
1
0
Y-CARRIAGE =10
1
0
1
1
Y-CARRIAGE =11
1
1
0
0
Y-CARRIAGE =12
Table 23.
Reset state
1000
Partial display configuration
PD2
PD1
PD0
Section 1
Section2
0
0
0
0
8 + Icon Row
0
0
1
8
0 + Icon Row
0
1
0
8
8 + Icon Row
0
1
1
0
16 + Icon Row
1
0
0
16
0 + Icon Row
1
0
1
8
16 + Icon Row
1
1
0
16
8 + Icon Row
1
1
1
16
16 + Icon Row
Reset state
000
35/61
Bus interfaces
STE2002
Figure 35. Host processor interconnection with I2C interface
SCL
SDAIN
STE2002
µP
SDAOUT
VSSAUX
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD1
OSCIN
ICON_MODE
VDD1 / GND / VSSAUX
SEL1
SEL2
EXT_SET
SA0
SA1
VSSAUX
TEST_10
GND / VSSAUX
VDD1
VDD1 / GND / VSSAUX
VDD1 / GND / VSSAUX
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
Figure 36. Host processor interconnection with serial interface
SCL
SDAIN
STE2002
µP
SDAOUT
VSSAUX
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD1
OSCIN
ICON_MODE
SEL1
SEL2
EXT_SET
VDD1
GND / VSSAUX
VDD1
SA0
VDD1 / GND / VSSAUX
SA1
VSSAUX
VDD1 / GND / VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
36/61
VDD1 / GND / VSSAUX
STE2002
Bus interfaces
Figure 37. Host processor interconnection with parallel interface
SCL
SDAIN
µP
SDAOUT
STE2002
VSSAUX
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD1
OSCIN
ICON_MODE
VDD1 / GND / VSSAUX
SEL1
GND / VSSAUX
VDD1
VDD1
VDD1 / GND / VSSAUX
SEL2
EXT_SET
SA0
SA1
VSSAUX
TEST_10
VDD1 / GND / VSSAUX
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
Figure 38. application schematic using an external lcd Voltage Generator
I/O
VDD2
VDD
40
VDD1
100nF
VSS
VSS2
128
81x 128
DISPLAY
VSS1
1µF
VLCDSENSE
41
VLCDOUT
VLCD
VLCDIN
Figure 39. Application schematic using the internal LCD voltage generator and two
separate supplies
I/O
VDD2
VDD2
VDD1
100nF
VSS
VDD1
40
100nF
VSS2
128
81x 128
DISPLAY
VSS1
1µF
VLCDSENSE
41
VLCDOUT
VLCDIN
37/61
Bus interfaces
STE2002
Figure 40. Application schematic using the internal LCD voltage generator and a
single supply
I/O
VDD
VDD2
40
VDD1
100nF
VSS
VSS2
128
VSS1
1µF
VLCDSENSE
VLCDOUT
VLCDIN
38/61
41
81 x 128
DISPLAY
STE2002
Bus interfaces
Figure 41. Power-up sequence
Tvdd
Tw(res) TLogic (res)
BOOSTER
OFF
RESET POWER ON
TABLE
INTERNAL
LOADED
RESET
VDD2
VDD1
RES
SCE
SCLK
SDIN
SD/C
PD/C
E
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
SCL
SDAIN
SOUT
SDA OUT
Hi-Z
OSCIN
(HOST)
OSC OUT
(DRIVER)
BSY FLG
LR0116
39/61
Bus interfaces
STE2002
Figure 42. Power-OFF sequence
Tw(res)
VDD2
VDD1
RES
SCLK
SDIN
SD/C
PD/C
E
SCE
SCl
SDAIN
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
SOUT
SDA OUT
Hi-Z
OSCIN
(HOST)
OSC OUT
(DRIVER)
BSY FLG
RESET
TABLE
LOADED
LR0117
40/61
STE2002
Bus interfaces
Figure 43. Initialization with built-in booster
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0], FR[1:0],
TC, M[1:0] for Normal Display Operation
Switch "ON" Booster and Display Control Logic
(PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
Figure 44. Dual partial display enabling instruction flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL1
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
41/61
Bus interfaces
STE2002
Figure 45. Dual partial display mode configuration or duty change
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
for Partial Display Operation
SET Partial Display Configuration (PD[2:0])
SET 1st Sector Start Address
SET 2nd Sector Start Address
OPTIONAL
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Figure 46. Data RAM to display mapping
DISPLAY DATA RAM
GLASS
TOP VIEW
bank
0
bank
1
DISPLAY DATA RAM = "1"
DISPLAY DATA RAM = "0"
bank
2
LCD
bank
3
bank
7
bank
8
ICOR ROW
D00IN1155
42/61
STE2002
Bus interfaces
Table 24.
Pin configuration
Test numbers
Pin configuration
TEST_1
TEST_2
TEST_3
TEST_4
OPEN
TEST_5
TEST_6
TEST_7
TEST_8
TEST_9
TEST_10
GND
TEST_11
TEST_12
TEST_13
TEST_14
GND
43/61
Electrical characteristics
STE2002
6
Electrical characteristics
6.1
Absolute maximum ratings
Table 25.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
VDD1
Supply voltage range
- 0.5 to + 5
V
VDD2
Supply voltage range
- 0.5 to + 7
V
VLCD
LCD Supply Voltage Range
- 0.5 to + 15
V
ISS
Supply current
- 50 to +50
mA
Vi
Input Voltage (all input pads)
-0.5 to VDD2 + 0.5
V
Iin
DC Input Current
- 10 to + 10
mA
Iout
DC Output Current
- 10 to + 10
mA
Ptot
Total Power Dissipation (Tj = 85°C)
300
mW
Po
Power Dissipation per Output
30
mW
Tj
Operating Junction Temperature(1)
-20 to + 120
°C
Storage Temperature
- 65 to 150
°C
Tstg
1. Device behavior and characterization are measured over this temperature range during internal
qualification of the product. During production testing, however, device performance is measured at a fixed
ambient temperature, typically 25°C.
44/61
STE2002
6.2
Electrical characteristics
DC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5 V;
Tamb = 25°C; unless otherwise specified.
Table 26.
Electrical characteristics DC operation
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
1.7
3.6
V
Supply voltages
VDD1
Supply voltage(1)
VDD2
Supply voltage
LCD voltage internally
generated
1.75
4.2
V
VLCDIN
LCD supply voltage
LCD voltage supplied
externally
4.5
14.5
V
VLCDOUT
LCD supply voltage
Internally generated(2);
4.5
14.5
V
VDD1 = 2.8V;
VLCD = 10V;
fsclk = 0(3)
15
20
40
µA
120
200
µA
1
µA
10
40
µA
25
80
µA
3
10
µA
10
15
µA
I(VDD1)
Supply current
VDD1 = 2.8V;
VLCD = 10V; fsclk = 1Mhz;
(1) (3); OSC_IN=GND;
parallel port
with VOP = 0 and
PRS = [0:0] with external
VLCD(4)
I(VDD2)
I(VDD1,2)
Voltage generator supply
VDD2= 2.8V;VLCD=10V;
current
fsclk= 0;
no display load;
5x charge pump (5) (3) (6)
Total supply current
VDD1,VDD2= 2.8V;
VLCD = 10V; 5x charge
pump; fsclk = 0;
no display load (5) (3) (6)
Power down Mode with
internal or External
VLCD(7)
I(VLDCIN)
External LCD supply
voltage current
VDD =2.8V;
VLCD =10V;no display
load; fsclk = 0 (3)
5
Logic outputs
V0H
High logic level output
voltage
IOH=-500µA
0.8VDD1
VDD1
V
VOL
Low logic level output
voltage
IOL=500µA
VSS
0.2VDD1
V
45/61
Electrical characteristics
Table 26.
STE2002
Electrical characteristics DC operation
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Logic inputs
VIL
Logic LOW voltage level
VSS
0.3VDD1
V
VIH
Logic HIGH voltage level
0.7VDD1
VDD2
V
Iin
Input current
-1
1
µA
VSS
0.3VDD1
V
0.7VDD1
VDD1
+0.5V
V
Vin = VSS1 or VDD1
logic inputs/outputs
VIL
Logic LOW voltage level
VIH
Logic HIGH Voltage
Level
Column and row driver
Rrow
ROW output resistance
VLCD = 10V;
3K
5K
kohm
Rcol
Column output
resistance
VLCD = 10V;
5K
10K
kohm
Vcol
Column Bias voltage
accuracy
No load
-50
+50
mV
Vrow
Row Bias voltage
accuracy
-50
+50
mV
-2.2
2.2
%
LCD supply voltage
VLCD
LCD supply voltage
accuracy; internally
generated
VDD = 2.8V; VLCD = 10V;
fsclk=0;
no display load(5)(3)(6)(8)
(8) VOP = 61h,
PRS = 2hex
TC0
-0.0·10-3
1/°C
TC1
-0.35·10-3
1/°C
TC2
-0.7·10-3
1/°C
TC3
-1.05·10-3
1/°C
TC4
-1.4
·10-3
1/°C
TC5
-1.75·10-3
1/°C
TC6
-2.1·10-3
1/°C
TC7
-3
1/°C
Temperature coefficient
-2.3·10
1. Data Byte Writing Mode VDD1 ≤VDD2
2. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load.
3. When fsclk = 0 there is no interface clock.
4. External VLCD, the display load current is not transmitted to IDD
5. Internal clock
6. Tolerance depends on the temperature; (typically zero at Tamb = 27°C), maximum tolerance values are measured at the
temperature range limit.
7. Power-down mode. During power-down all static currents are switched-off.
8. For TC0 to TC7
46/61
STE2002
6.3
Electrical characteristics
AC operation
VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5V; Tamb = 25°C;
unless otherwise specified.
Table 27.
Symbol
AC operation
Parameter
Test condition
Min.
Typ.
Max.
Unit
61
72
83
kHz
100
kHz
Internal oscillator (Figure 47)
FOSC
Internal oscillator
frequency
FEXT
External oscillator
frequency
FFRAME
Frame frequency
VDD = 2.8V;
20
fosc or fext = 72 kHz(1)
RES LOW pulse width
Tw(RES)
TLOGIC
75
Hz
µs
5
Reset pulse rejection
1
µs
Internal logic reset time
5
µs
(RES)
TVDD
I2C
Bus
FSCL
VDD1 vs. VDD2 delay
interface(4)
µs
0
(Figure 48)
SCL clock frequency
Fast Mode
DC
400
kHz
High Speed Mode;
Cb=100pF
(max);VDD1=2
DC
3.4
MHz
High Speed Mode;
Cb=400pF (max);
VDD1=2
DC
1.7
MHz
400
KHz
Fast Mode; VDD1=1.7V
TSU;STA
Set-up time (repeated)
START condition
Cb=100pF(2) (3)
160
ns
THD;STA
Hold time (repeated)
START condition
Cb=100pF(2) (3)
160
ns
TLOW
LOW period of the SCLH
Cb=100pF (2) (3)
clock
160
ns
THIGH
HIGH period of the
SCLH clock
Cb=100pF(2) (3)
60
ns
TSU;DAT
Data set-up time
Cb=100pF (2) (3)
10
ns
Cb=100pF
(2) (3)
40
ns
Tr;CL
Rise time of SCLH signal Cb=100pF
(2) (3)
10
ns
TrCL1
Rise time of SCLH signal
after a repeated START
Cb=100pF (2) (3)
condition and after an
acknowledge bit
10
ns
TfCL
Fall time of SCLH signal
Cb=100pF (2) (3)
10
ns
THD;DAT
Data hold time
47/61
Electrical characteristics
Table 27.
Symbol
STE2002
AC operation (continued)
Parameter
Test condition
TrDA
Rise time of SDAH signal Cb=100pF
TfDA
Fall time of SDAH signal
(2) (3) (4)
Cb=100pF (2) (3) (4)
Min.
Max.
10
10
Rise time of SDAH signal Cb=400pF
(2) (3) (4)
20
TfDA
Fall time of SDAH signal
Cb=400pF
(2) (3) (4)
20
TSU;STO
Set-up time for STOP
condition
Cb=100pF(2) (3)
Cb
Capacitive load for SDAH
and SCLH
Cb
Capacitive load for SDAH
+ SDA line and SCLH +
SCL line
TrDA
Typ.
ns
80
ns
ns
160
160
100
Unit
ns
ns
400
pF
400
pF
Parallel interface (Figure 49, Figure 50)
TCY(EN)
Enable Cycle Time
150
ns
TW(EN)
Enable Pulse width
60
ns
TSU(A)
Address Set-up Time
30
ns
TH(A)
Address Hold Time
40
ns
TSU(D)
Data Set-Up Time
30
ns
TH(D)
Data Hold Time
30
ns
TSU(D)
Data Set-Up Time in
read Mode
THU(D)
Data Hold Time In Read
mode
48/61
VDD1 = 1.7V; Write-(2) (5)
100
100
ns
ns
STE2002
Electrical characteristics
Table 27.
AC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Serial interface (Figure 51)
TCYC
Clock Cycle SCLK
150
ns
TPWH1
SCLK pulse width HIGH
60
ns
TPWL1
SCLK Pulse width LOW
60
ns
TS2
SCE setup time
30
ns
TH2
SCE hold time
50
ns
TPWH2
SCE minimum high time
50
ns
TS3
SD/C setup time
30
ns
TH3
SD/C hold time
40
ns
TS4
SDIN setup time
30
ns
TH4
SDIN hold time
40
ns
TS5
SOUT Access Time
100
ns
TH5
SOUT Disable Time vs.
SCLK
100
ns
TH6
SOUT Disable Time vs.
SCE
100
ns
VDD1 = 1.7V; Write(2) (5)
f
os
1. F frame = -------960
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and
VIH with an input voltage swing of VSS to VDD
3. Cb is the capacitive load for each bus line.
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. CVLCD is the filtering Capacitor on VLCDOUTTrise and Tfall (30%-70%) = 10 ns
49/61
Electrical characteristics
STE2002
Figure 47. RESET timing diagram
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
INPUTS
I/O
(HOST)
I/O
(DRIVER)
Hi-Z
INTERFACE
OUTPUT
Hi-Z
OSCIN
(HOST)
OSC OUT
(DRIVER)
BSY FLG
RESET
TABLE
LOADED
LR0118
Figure 48. I2C-bus timings
Sr
Sr P
tfDA
trDA
SDAH
tHD;DAT
tSU;STA
tSU;DAT
tHD;STA
SCLH
tfCL
trCL
trCL1
tHIGH tLOW
= MCS current source pull-up
= Rp resistor pull-up
50/61
(1)
tLOW tHIGH
trCL1
(1)
D00IN1153
STE2002
Pad coordinates
Figure 49. Parallel interface write timing
PD/C
tSU(A)
tW(en)
th(A)
E
tSU(D)
tHO(D)
tCY(en)
DB0-DB7
R/W
WRITE
Figure 50. Parallel interface read timing
Don't Care
PD/C
tSU(A)
tW(en)
th(A)
E
tHOR(D)
tSUR(D)
tCY(en)
DB0-DB7
R/W
READ
Figure 51. Serial interface timing
tS2
tH2
tPWH2
CS
tH3
tS3
D/C
tCYC
tPWL1
tWH1
tS2
SCLK
tS4
tH4
SDIN
tS5
tH5
tH6
SOUT
LR0001
7
Pad coordinates
See Table 28: Pad coordinates and Table 29: Alignment marks coordinates.
51/61
Pad coordinates
Table 28.
STE2002
Pad coordinates
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
C0
1
-3275.0
-946.5
C34
35
-1575.0
-946.5
C1
2
-3225.0
-946.5
C35
36
-1525.0
-946.5
C2
3
-3175.0
-946.5
C36
37
-1475.0
-946.5
C3
4
-3125.0
-946.5
C37
38
-1425.0
-946.5
C4
5
-3075.0
-946.5
C38
39
-1375.0
-946.5
C5
6
-3025.0
-946.5
C39
40
-1325.0
-946.5
C6
7
-2975.0
-946.5
C40
41
-1275.0
-946.5
C7
8
-2925.0
-946.5
C41
42
-1225.0
-946.5
C8
9
-2875.0
-946.5
C42
43
-1175.0
-946.5
C9
10
-2825.0
-946.5
C43
44
-1125.0
-946.5
C10
11
-2775.0
-946.5
C44
45
-1075.0
-946.5
C11
12
-2725.0
-946.5
C45
46
-1025.0
-946.5
C12
13
-2675.0
-946.5
C46
47
-975.0
-946.5
C13
14
-2625.0
-946.5
C47
48
-925.0
-946.5
C14
15
-2575.0
-946.5
C48
49
-875.0
-946.5
C15
16
-2525.0
-946.5
C49
50
-825.0
-946.5
C16
17
-2475.0
-946.5
C50
51
-775.0
-946.5
C17
18
-2425.0
-946.5
C51
52
-725.0
-946.5
C18
19
-2375.0
-946.5
C52
53
-675.0
-946.5
C19
20
-2325.0
-946.5
C53
54
-625.0
-946.5
C20
21
-2275.0
-946.5
C54
55
-575.0
-946.5
C21
22
-2225.0
-946.5
C55
56
-525.0
-946.5
C22
23
-2175.0
-946.5
C56
57
-475.0
-946.5
C23
24
-2125.0
-946.5
C57
58
-425.0
-946.5
C24
25
-2075.0
-946.5
C58
59
-375.0
-946.5
C25
26
-2025.0
-946.5
C59
60
-325.0
-946.5
C26
27
-1975.0
-946.5
C60
61
-275.0
-946.5
C27
28
-1925.0
-946.5
C61
62
-225.0
-946.5
C28
29
-1875.0
-946.5
C62
63
-175.0
-946.5
C29
30
-1825.0
-946.5
C63
64
-125.0
-946.5
C30
31
-1775.0
-946.5
C64
65
+125.0
-946.5
C31
32
-1725.0
-946.5
C65
66
+175.0
-946.5
C32
33
-1675.0
-946.5
C66
67
+225.0
-946.5
C33
34
-1625.0
-946.5
C67
68
+275.0
-946.5
52/61
STE2002
Table 28.
Pad coordinates
Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
C68
69
+325.0
-946.5
C103
104
+2075.0
-946.5
C69
70
+375.0
-946.5
C104
105
+2125.0
-946.5
C70
71
+425.0
-946.5
C105
106
+2175.0
-946.5
C71
72
+475.0
-946.5
C106
107
+2225.0
-946.5
C72
73
+525.0
-946.5
C107
108
+2275.0
-946.5
C73
74
+575.0
-946.5
C108
109
+2325.0
-946.5
C74
75
+625.0
-946.5
C109
110
+2375.0
-946.5
C75
76
+675.0
-946.5
C110
111
+2425.0
-946.5
C76
77
+725.0
-946.5
C111
112
+2475.0
-946.5
C77
78
+775.0
-946.5
C112
113
+2525.0
-946.5
C78
79
+825.0
-946.5
C113
114
+2575.0
-946.5
C79
80
+875.0
-946.5
C114
115
+2625.0
-946.5
C80
81
+925.0
-946.5
C115
116
+2675.0
-946.5
C81
82
+975.0
-946.5
C116
117
+2725.0
-946.5
C82
83
+1025.0
-946.5
C117
118
+2775.0
-946.5
C83
84
+1075.0
-946.5
C118
119
+2825.0
-946.5
C84
85
+1125.0
-946.5
C119
120
+2875.0
-946.5
C85
86
+1175.0
-946.5
C120
121
+2925.0
-946.5
C86
87
+1225.0
-946.5
C121
122
+2975.0
-946.5
C87
88
+1275.0
-946.5
C122
123
+3025.0
-946.5
C88
89
+1325.0
-946.5
C123
124
+3075.0
-946.5
C89
90
+1375.0
-946.5
C124
125
+3125.0
-946.5
C90
91
+1425.0
-946.5
C125
126
+3175.0
-946.5
C91
92
+1475.0
-946.5
C126
127
+3225.0
-946.5
C92
93
+1525.0
-946.5
C127
128
+3275.0
-946.5
C93
94
+1575.0
-946.5
R40
129
+3571.5
-875.0
C94
95
+1625.0
-946.5
R41
130
+3571.5
-825.0
C95
96
+1675.0
-946.5
R42
131
+3571.5
-775.0
C96
97
+1725.0
-946.5
R43
132
+3571.5
-725.0
C97
98
+1775.0
-946.5
R44
133
+3571.5
-675.0
C98
99
+1825.0
-946.5
R45
134
+3571.5
-625.0
C99
100
+1875.0
-946.5
R46
135
+3571.5
-575.0
C100
101
+1925.0
-946.5
R47
136
+3571.5
-525.0
C101
102
+1975.0
-946.5
R48
137
+3571.5
-475.0
C102
103
+2025.0
-946.5
R49
138
+3571.5
-425.0
53/61
Pad coordinates
Table 28.
STE2002
Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
R50
139
+3571.5
-375.0
TEST_4
173
+2675.0
+946.5
R51
140
+3571.5
-325.0
TEST_5
174
+2625.0
+946.5
R52
141
+3571.5
-275.0
TEST_6
175
+2575.0
+946.5
R53
142
+3571.5
-225.0
TEST_7
176
+2525.0
+946.5
R54
143
+3571.5
-175.0
TEST_8
177
+2475.0
+946.5
R55
144
+3571.5
-125.0
TEST_9
178
+2425.0
+946.5
R56
145
+3571.5
-75.0
TEST_10
179
+2375.0
+946.5
R57
146
+3571.5
-25.0
VSSAUX
180
+2225.0
+946.5
R58
147
+3571.5
+25.0
SA1
181
+2175.0
+946.5
R59
148
+3571.5
+75.0
SA0
182
+2125.0
+946.5
R60
149
+3571.5
+125.0
EXT
183
+2075.0
+946.5
R61
150
+3571.5
+175.0
SEL2
184
+2025.0
+946.5
R62
151
+3571.5
+225.0
SEL1
185
+1975.0
+946.5
R63
152
+3571.5
+275.0
ICON_MODE
186
+1925.0
+946.5
R64
153
+3571.5
+325.0
OSC_IN
187
+1875.0
+946.5
R65
154
+3571.5
+375.0
VDD1_1
188
+1825.0
+946.5
R66
155
+3571.5
+425.0
VDD1_2
189
+1825.0
+839.5
R67
156
+3571.5
+475.0
VDD1_3
190
+1775.0
+946.5
R68
157
+3571.5
+525.0
VDD1_4
191
+1775.0
+839.5
R69
158
+3571.5
+575.0
VDD1_5
192
+1725.0
+946.5
R70
159
+3571.5
+625.0
VDD1_6
193
+1725.0
+839.5
R71
160
+3571.5
+675.0
VDD1_7
194
+1675.0
+946.5
R72
161
+3571.5
+725.0
VDD1_8
195
+1675.0
+839.5
R73
162
+3571.5
+775.0
VDD1_9
196
+1625.0
+946.5
R74
163
+3571.5
+825.0
VDD1_10
197
+1625.0
+839.5
R75
164
+3571.5
+875.0
VDD1_11
198
+1575.0
+946.5
R76
165
+3275.0
+946.5
VDD1_12
199
+1575.0
+839.5
R77
166
+3225.0
+946.5
VDD2_1
200
+1525.0
+946.5
R78
167
+3175.0
+946.5
VDD2_2
201
+1525.0
+839.5
R79
168
+3125.0
+946.5
VDD2_3
202
+1475.0
+946.5
R80/ICON
169
+3075.0
+946.5
VDD2_4
203
+1475.0
+839.5
TEST_1
170
+2825.0
+946.5
VDD2_5
204
+1425.0
+946.5
TEST_2
171
+2775.0
+946.5
VDD2_6
205
+1425.0
+839.5
TEST_3
172
+2725.0
+946.5
VDD2_7
206
+1375.0
+946.5
54/61
STE2002
Table 28.
Pad coordinates
Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
VDD2_8
207
+1375.0
+839.5
VSS_6
241
-1075.0
+839.5
VDD2_9
208
+1325.0
+946.5
VSS_7
242
-1125.0
+946.5
VDD2_10
209
+1325.0
+839.5
VSS_8
243
-1125.0
+839.5
VDD2_11
210
+1275.0
+946.5
VSS_9
244
-1175.0
+946.5
VDD2_12
211
+1275.0
+839.5
VSS_10
245
-1175.0
+839.5
BUSY_FLAG
212
+1125.0
+946.5
VSS_11
246
-1225.0
+946.5
SDOUT
213
+975.0
+946.5
VSS_12
247
-1225.0
+839.5
SDIN
214
+925.0
+946.5
VSS_13
248
-1275.0
+946.5
SD/C
215
+875.0
+946.5
VSS_14
249
-1275.0
+839.5
SCE
216
+825.0
+946.5
VSS_15
250
-1325.0
+946.5
SCLK
217
+775.0
+946.5
VSS_16
251
-1325.0
+839.5
VSSAUX
218
+625.0
+946.5
VSS_17
252
-1375.0
+946.5
R/W
219
+575.0
+946.5
VSS_18
253
-1375.0
+839.5
D7
220
+525.0
+946.5
VSS_19
254
-1425.0
+946.5
D6
221
+475.0
+946.5
VSS_20
255
-1425.0
+839.5
D5
222
+425.0
+946.5
TEST_11
256
-1475.0
+946.5
D4
223
+375.0
+946.5
TEST_12
257
-1525.0
+946.5
D3
224
+325.0
+946.5
TEST_13
258
-1575.0
+946.5
D2
225
+275.0
+946.5
TEST_14
259
-1625.0
+946.5
D1
226
+225.0
+946.5
OSC_OUT
260
-2175.0
+946.5
D0
227
+175.0
+946.5
VLCDIN_1
261
-2325.0
+946.5
PD/C
228
+125.0
+946.5
VLCDIN_2
262
-2325.0
+839.5
E
229
+75.0
+946.5
VLCDIN_3
263
-2375.0
+946.5
RES
230
-75.0
+946.5
VLCDIN_4
264
-2375.0
+839.5
VSSAUX
231
-225.0
+946.5
VLCDIN_5
265
-2425.0
+946.5
SDA_OUT
232
-275.0
+946.5
VLCDIN_6
266
-2425.0
+839.5
SDA_OUT
233
-325.0
+946.5
VLCDIN_7
267
-2475.0
+946.5
SDA_IN
234
-375.0
+946.5
VLCDIN_8
268
-2475.0
+839.5
SCL
235
-425.0
+946.5
VLCDIN_9
269
-2525.0
+946.5
VSS_1
236
-975.0
+946.5
VLCDIN_10
270
-2525.0
+839.5
VSS_2
237
-975.0
+839.5
VLCDSENSE_1
271
-2575.0
+946.5
VSS_3
238
-1025.0
+946.5
VLCDSENSE_2
272
-2575.0
+839.5
VSS_4
239
-1025.0
+839.5
VLCDOUT_1
273
-2625.0
+946.5
VSS_5
240
-1075.0
+946.5
VLCDOUT_2
274
-2625.0
+839.5
55/61
Pad coordinates
Table 28.
STE2002
Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
VLCDOUT_3
275
-2675.0
+946.5
R13
309
-3571.5
-175.0
VLCDOUT_4
276
-2675.0
+839.5
R12
310
-3571.5
-225.0
VLCDOUT_5
277
-2725.0
+946.5
R11
311
-3571.5
-275.0
VLCDOUT_6
278
-2725.0
+839.5
R10
312
-3571.5
-325.0
VLCDOUT_7
279
-2775.0
+946.5
R9
313
-3571.5
-375.0
VLCDOUT_8
280
-2775.0
+839.5
R8
314
-3571.5
-425.0
VLCDOUT_9
281
-2825.0
+946.5
R7
315
-3571.5
-475.0
VLCDOUT_10
282
-2825.0
+839.5
R6
316
-3571.5
-525.0
R39
283
-3075.0
+946.5
R5
317
-3571.5
-575.0
R38
284
-3125.0
+946.5
R4
318
-3571.5
-625.0
R37
285
-3175.0
+946.5
R3
319
-3571.5
-675.0
R36
286
-3225.0
+946.5
R2
320
-3571.5
-725.0
R35
287
-3275.0
+946.5
R1
321
-3571.5
-775.0
R34
288
-3571.5
+875.0
R0
322
-3571.5
-825.0
R33
289
-3571.5
+825.0
ICON
323
-3571.5
-875.0
R32
290
-3571.5
+775.0
R31
291
-3571.5
+725.0
R30
292
-3571.5
+675.0
R29
293
-3571.5
+625.0
R28
294
-3571.5
+575.0
R27
295
-3571.5
+525.0
R26
296
-3571.5
+475.0
R25
297
-3571.5
+425.0
R24
298
-3571.5
+375.0
R23
299
-3571.5
+325.0
R22
300
-3571.5
+275.0
R21
301
-3571.5
+225.0
R20
302
-3571.5
+175.0
R19
303
-3571.5
+125.0
R18
304
-3571.5
+75.0
R17
305
-3571.5
+25.0
R16
306
-3571.5
-25.0
R15
307
-3571.5
-75.0
56/61
STE2002
Pad coordinates
Table 29.
Alignment marks coordinates
X
Y
Marks
-3574.5
-949.5
mark1
+3574.5
-949.5
mark2
-2250
+949.5
mark3
+1200
+949.5
mark4
Figure 52. Alignment marks dimensions
39 µm
94 µm
57/61
Mechanical data
8
STE2002
Mechanical data
Table 30.
Bumps
Bump number
Dimensions
Bumps on single row size
1-187
212-235
256-260
283-323
30µm x 98 µm x 17.5
Bumps on two rows size
188-211
236-255
261-282
30µm x 87 µm x 17.5
Pad size
1-323
43µm x 107µm
Pad pitch
1-323
50µm
Spacing between bumps
1-323
20µm
Table 31.
Die mechanical dimensions
Die size
2.07mm x 7.32mm
Wafers thickness
500µm
Figure 53. Die orientation in tray
DIE IDENTIFICATION
Mark 3
Mark 1
58/61
STE2002
Mark 4
Mark 2
STE2002
Mechanical data
Figure 54. Tray information
A
A
Array Size = 13 x5 (65) Units
59/61
Ordering information
9
STE2002
Ordering information
Table 32.
Order codes
Part numbers
10
STE2002DIE1
Bumped wafers
STE2002DIE2
Bumped dice on waffle pack
Revision history
Table 33.
Document revision history
Date
60/61
Type
Revision
Changes
15-Sep-2002
1
Initial release.
15-Sep- 2005
2
Updated suppy current values, LCD supply voltage accuracy, Internal
Oscillator frequency range
12-Dec-2006
3
Reviewed the Junction operating temperature range in Table 25:
Absolute maximum ratings and added a footnote.
STE2002
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