STSJ18NF3LL N-CHANNEL 30V - 0.016 Ω - 18A PowerSO-8™ LOW GATE CHARGE STripFET™ II POWER MOSFET Table 1: General Features TYPE STSJ18NF3LL ■ ■ ■ ■ ■ Figure 1:Package VDSS RDS(on) ID 30 V <0.019 Ω 18 A TYPICAL RDS(on) = 0.016 Ω @ 10V TYPICAL Qg = 12.5 nC @ 4.5 V CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED IMPROVED JUNCTION-CASE THERMAL RESISTANCE DESCRIPTION This Power MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. This silicon, housed in thermally improved SO-8™ package, exhibits optimal on-resistance versus gate charge tradeoff plus lower Rthj-c. PowerSO-8™ Figure 2: Internal Schematic Diagram APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCS DRAIN CONTACT ALSO ON THE BACKSIDE Table 2: Order Codes SALES TYPE STSJ18NF3LL MARKING PACKAGE 18F3LL) PowerSO-8 PACKAGING TAPE & REEL Table 3: ABSOLUTE MAXIMUM RATING Symbol VDS VDGR VGS Parameter 30 V Drain-gate Voltage (RGS = 20 kΩ) 30 V Gate- source Voltage ± 16 V 18 A Drain Current (continuous) at TC = 100°C(*) 18 A Drain Current (pulsed) 72 A Total Dissipation at TC = 25°C Total Dissipation at TC = 25°C (#) 70 3 W W Drain Current (continuous) at TC = 25°C (*) ID Ptot (•) Pulse width limited by safe operating area. March 2005 Unit Drain-source Voltage (VGS = 0) ID IDM(•) Value (*) Value limited by wires bonding Rev. 1.0 1/9 STSJ18NF3LL Table 4: THERMAL DATA Rthj-c Rthj-amb Tj Tstg Thermal Resistance Junction-case (*)Thermal Resistance Junction-ambient Maximum Operating Junction Temperature Storage Temperature Max Max °C/W °C/W °C °C 1.8 41.7 150 -55 to 150 (*) When Mounted on FR-4 board with 1 inch2 pad, 2 oz of Cu and t > 10 sec. ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) Table 5: OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 16 V V(BR)DSS Min. Typ. Max. 30 Unit V 1 10 µA µA ±100 nA Max. Unit Table 6: ON (*) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS ID = 250 µA RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 4.5 V ID = 9 A ID = 9 A Min. Typ. 1 V 0.016 0.019 0.019 0.022 Ω Ω Typ. Max. Unit Table 7: DYNAMIC Symbol 2/9 Parameter Test Conditions gfs (*) Forward Transconductance VDS=15 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 ID = 9 A Min. 17 S 800 250 60 pF pF pF STSJ18NF3LL ELECTRICAL CHARACTERISTICS (continued) Table 8: SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 15 V ID = 9 A VGS = 4.5 V RG = 4.7 Ω (Resistive Load, Figure 15) 18 32 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=15V ID=18A VGS=4.5V 12.5 3.2 4.5 17 nC nC nC Typ. Max. Unit (see test circuit, Figure 16) ns ns Table 9: SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. VDD = 15 V ID = 9 A VGS = 4.5 V RG = 4.7Ω, (Resistive Load, Figure 17) 21 11 ns ns Table 10: SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 18 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 18 A di/dt = 100A/µs Tj = 150°C VDD = 15 V (see test circuit, Figure 17) trr Qrr IRRM (• )Pulse Test Conditions Min. Typ. VGS = 0 23 17 1.5 Max. Unit 18 72 A A 1.2 V ns nC A width limited by safe operating area. (*)Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Figure 3: Safe Operating Area Figure 4: Thermal Impedance 3/9 STSJ18NF3LL Figure 5: Output Characteristics Figure 6: Transfer Characteristics Figure 7: Transconductance Figure 8: Static Drain-source On Resistance Figure 9: Gate Charge vs Gate-source Voltage Figure 10: Capacitance Variations 4/9 STSJ18NF3LL Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 12: Normalized on Resistance vs Temperature Figure 13: Source-drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature. . . 5/9 STSJ18NF3LL Fig. 15 Switching Times Test Circuits For Resistive Load Fig. 17: Test Circuit For Diode Recovery Behaviour 6/9 Fig.16: Gate Charge test Circuit STSJ18NF3LL 7/9 STSJ18NF3LL Table 11:Revision History 8/9 Date Revision March 2005 1.0 Description of Changes FIRST ISSUE STSJ18NF3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America. www.st.com 9/9