TI TPS2394PW

TPS2394
www.ti.com
SLVSAA9 – AUGUST 2010
–48-V Hot Swap Power Manager
Check for Samples: TPS2394
FEATURES
1
•
•
•
•
•
•
•
•
•
DESCRIPTION
Operating Supply Range of –12 V to –80 V
Withstands Transients to –100 V
Programmable Current Limit
Programmable Linear Inrush Slew Rate
Programmable UV/OV Thresholds
Programmable UV and OV Hysteresis
Fault Timer to Eliminate Nuisance Trips
Power Good and Fault Outputs
14-Pin TSSOP Package
The TPS2394 is a hot swap power manager which
can provide inrush limit, over current protection, short
circuit protection. The TPS2394 operates with supply
voltages from −12 V to −80 V, and withstands input
transient to −100 V.
The TPS2394 uses a power FET to provide load
current slew rate control and peak current limiting that
is programmed by one resistor and one capacitor.
The device also provides a power good output to
enable down-stream power converters and a fault
output to indicate load problems.
APPLICATIONS
•
•
•
•
–48-V Distributed Power Systems
Central Office Switching
ATCA Systems
Base Stations
TYPICAL APPLICATION DIAGRAM
RLOAD
RTN
D1
R1
RTN
UV
GAT 11
12 PG
Fault
CLOAD
1
3
Power Good
(1)
2
TPS2394
FLT
R2
4
R3
RSENSE
SENSE 10
SOURCE
7
NC
9
NC
8
OV
FLTTIM
RAMP
NC
NC
6
14
13
5
CFLT
Q1
CRAMP
-Vin
(1)
D1 optional per application requirements.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS2394
SLVSAA9 – AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted) (2)
PARAMETERS
VALUE
RTN
Input voltage range
FLTTIM, RAMP, SENSE, OV, UV
Output voltage range
FLT, PG
Continuous output current
FLT, PG
–0.3 to 15
(3)
10
mA
–55 to 125
°C
ESD - Human body model (HBM)
2
ESD - Charged device model (CDM)
(3)
V
–0.3 to 100
Operating junction temperature range, TJ
(1)
(2)
UNIT
–0.3 to 100
kV
1.5
All voltages are with respect to SOURCE (unless otherwise noted).
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With 10 kΩ minimum series resistance. Range limited to –0.3V to 80V from low impedance source.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Input supply, SOURCE to RTN
–80
–48
–12
UNIT
V
Operating junction temperature range
–40
85
°C
TSSOP-14 PACKAGE
(TOP VIEW)
RTN
FLT
UV
OV
FLTTIM
RAMP
SOURCE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
NC
NC
PG
GAT
SENSE
NC
NC
PRODUCT INFORMATIONS (1)
(1)
TA
PACKAGE
PART NUMBER
−40°C to 85°C
TSSOP-14
TPS2394PW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at wwww.ti.com.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS2394
PW (14 (PINS)
qJA
Junction-to-ambient thermal resistance
120.8
qJB
Junction-to-board thermal resistance
62.8
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
(1)
1
UNITS
°C/W
56.5
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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ELECTRICAL CHARACTERISTICS
SOURCE = -48 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, TA = −40°C to 85°C (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1000
1500
UNIT
INPUT SUPPLY
ICC1
Supply current
SOURCE = -48 V
ICC2
Supply current
SOURCE = -80 V
VUVLO_I
Internal UVLO threshold voltage
To GAT pull up
VHYST
Internal UVLO hysteresis voltage
2000
µA
–11.8
–10
–8
V
50
240
500
mV
To GAT pull up, 25°C
1.391
1.400
1.409
To GAT pull up, 0 to 70°C
1.387
1.400
1.413
To GAT pull up, –40 to 85°C
1.384
1.400
1.419
–11
–10
–9
OVERVOLTAGE AND UNDERVOLTAGE INPUTS (OV AND UV)
VTHUV
UV threshold voltage, UV rising, to SOURCE
IHYSUV
UV hysteresis
UV = −45.5 V
IILUV
UV low−level input current
UV = −47 V
VTHOV
OV threshold voltage, OV rising, to SOURCE
To GAT pull up
1.376
1.400
1.426
IHYSOV
OV hysteresis
OV = −45.5 V
–11.1
–10
–8.6
IILOV
OV low−level input current
OV = −47 V
–1
High level output, GAT−SOURCE
SENSE = SOURCE
11
14
ISINK_f
GAT sink current in fault
SENSE – SOURCE = 80 mV,
GAT = –43 V, FLTTIME = 5 V
30
75
ISINK_l
GAT sink current in linear mode
SENSE – SOURCE = 80 mV,
GAT = –43 V, FLTTIME = 2 V
IIN
SENSE input current
0 V < SENSE – SOURCE < 0.2 V
–1
VREF_K
Reference clamp voltage, SENSE – SOURCE
RAMP – SOURCE = 6 V
34
VIO
Input offset voltage, SENSE – SOURCE
RAMP – SOURCE = 0 V
–7
–1
1
1
V
µA
V
µA
LINEAR CURENT AMPLIFIER (LCA)
VOH
(1)
(2)
17
V
mA
5
10
42
50
1
9
µA
mV
All voltages are with respect to RTN unless otherwise stated.
Currents are positive into and negative out of the specified terminal.
3
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ELECTRICAL CHARACTERISTICS (continued)
SOURCE = -48 V, UV = 2.5 V, OV = 0.5 V, SENSE = 0 V, RAMP = 0 V, TA = −40°C to 85°C (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RAMP GENERATOR
ISRC1
RAMP source current, slow turn-on rate
RAMP – SOURCE = 0.25 V
–800
–550
–300
nA
ISRC2
RAMP source current, normal rate
RAMP – SOURCE = 1 V and 3 V
–11.3
–10
–8.5
µA
VOL
Low-level output voltage
UV = SOURCE
AV
Voltage gain, relative to SENSE
0 V < RAMP – SOURCE < 5 V
9.5
10
10.7
mV/V
100
120
140
mV
2
4
7
µs
5
mV
–54
–50
–41
µA
3.75
4.00
4.25
5
mV
OVERLOAD COMPARATOR
VTH_OL
SENSE current overload threshold
tRSP
Response time
SENSE – SOURCE = 200 mV
FAULT TIMER
VOL
FLTTIM low−level output voltage, to SOURCE
UV = –48 V
ICHG
FLTTIM charging current, current limit mode
FLTTIM – SOURCE = 2 V
VFLT
FLTTIM fault threshold voltage to SOURCE
VRST
Fault reset threshold to SOURCE
IDSG
FLTTIM Discharge current, retry mode
FLTTIM – SOURCE = 2 V
D
Output duty cycle during retry cycles
SENSE − SOURCE = 80 mV,
FLTTIM – SOURCE = 2 V
IRST
FLTTIM discharge current, timer reset mode
FLTTIM – SOURCE = 2 V, SENSE = V
0.5
0.38
0.75
1%
1.5%
1
V
µA
mA
LOGIC OUTPUTS (FLT, PG)
IOHFLT
FLT high-level output leakage current
UV = –48 V, FLT – SOURCE = 80 V
–10
10
IOHPG
PG high-level output leakage current
UV = –45 V, PG – SOURCE = 80 V
–10
10
FLT ON resistance
SENSE–SOURCE = 80 mV,
FLTTIM–SOURCE = 5 V, I(FLT) = 1 mA
50
80
Ω
PG ON resistance
UV = –48 V, IO(PG) = 1 mA
50
80
Ω
RDS(on)
4
µA
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2394
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SLVSAA9 – AUGUST 2010
DEVICE INFORMATION
PIN FUNCTIONS
PIN
NAME
I/O
DESCRIPTION
NO.
FLT
2
O
Open-drain, active-low indication that the part is in fault.
FLTTIM
5
I/O
Connection for user programming of the fault timeout period.
GAT
11
O
Gate drive for external N-channel MOSFET that ramps load current and disconnects in the event of a
fault.
NC
9
Not connected, leave floating
NC
8
Not connected, leave floating
NC
14
Not connected, leave floating
NC
13
OV
4
I
Over voltage sense input.
PG
12
O
Open-drain, active-high indication that the power MOSFET is fully enhanced.
RAMP
6
I/O
Programming input for setting the inrush current slew rate.
RTN
1
I
Supply return (for positive grounded system).
SENSE
10
I
Positive current sense input.
SOURCE
7
I/O
Negative current sense input.
UV
3
I
Not connected, leave floating
Under voltage sense input.
PIN DESCRIPTIONS
FLT: Open-drain, active-low indication that TPS2394 has shut down due to a faulted load. This happens if the
load current stays limited by the linear current amplifier (LCA) for more than the fault time (time to charge the
FLTTIM capacitor). FLT is cleared when input supply drops below the UV-comparator threshold or exceeds the
OV-comparator threshold. The FLT output is pulled to SOURCE. The FLT output is able to sink 10 mA when in
fault, withstand 80 V without leakage when not faulted, and withstand transients as high as 100 V when limited
by a series resistor of at least 10 kΩ.
FLTTIM: Connection for user programming of the fault timeout period. An external capacitor connected from
FLTTIM to SOURCE establishes the timeout period to declare a fault condition. This timeout protects against
indefinite current sourcing into a faulted load, and also provides a filter against nuisance trips from momentary
current spikes or surges. TPS2394 defines a fault condition as voltage at the SENSE pin at or greater than the
42-mV fault threshold. When a fault condition exists, the timer is active. The devices manage fault timing by
charging the external capacitor to the 4-V fault threshold, then subsequently discharging it at approximately 1%
the charge rate to establish the duty cycle for retrying the load. Whenever the fault latch is set (timer expired),
GAT and FLT are pulled low.
GAT: Gate drive for an external N-channel protection power MOSFET. When input supply is above the UV
threshold and below the OV threshold, gate drive is enabled and the device begins charging the external
capacitor connected to RAMP. RAMP develops the reference voltage at the non-inverting input of the internal
LCA. The inverting input is connected to the current sense node, SENSE. The LCA acts to slew the pass
MOSFET gate to force the SENSE voltage to track the reference. The reference is internally clamped to 42 mV,
so the maximum current that can be sourced to the load is determined by the sense resistor value as IMAX ≤42
mV/RSENSE. Once the load voltage has ramped up to the input dc potential and current demand drops off, the
LCA drives GAT 14 V above SOURCE to fully enhance the pass MOSFET, completing the low-impedance
supply return path for the load.
PG: Open-drain, active-high indication that load current is below the current limit and the power MOSFET is fully
enhanced. When commanded load current is more than the actual load current, the linear current amplifier (LCA)
will raise the power MOSFET gate voltage to fully enhance the power MOSFET. At this time, the PG output will
go high. This output can be used to enable a down-stream dc-to-dc converter. The PG output is pulled to
SOURCE and is able to sink 10 mA when in fault, withstand 80 V without leakage when power is not good, and
withstand transients as high as 100 V when limited by a series resistor of at least 10 kΩ.
5
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OV: Over voltage comparator input. This input is typically connected to a voltage divider between RTN and
SOURCE to sense the magnitude of the input supply. If OV is less than 1.4 V above SOURCE, and UV is more
than 1.4 V above SOURCE, and there is no fault, the linear current amp will be enabled. In the event of a fault,
pulling OV high or UV low will reset the fault latch and allow the IC to restart. OV can also be used as an
active-low logic enable input. The over-voltage comparator hysteresis is programmed by the equivalent
resistance seen looking into the divider at the OV input.
RAMP: Programming input for setting inrush current and current slew rate. An external capacitor connected
between RAMP and SOURCE establishes turn-on current slew rate. During turn-on, TPS2394 charges this
capacitor to establish the reference input to the LCA at 1% of the voltage from RAMP to SOURCE. The
closed-loop control of the LCA and the pass MOSFET maintains the V(SENSE - SOURCE) at the reference
potential, so the load current slew rate is directly set by the voltage ramp rate at the RAMP pin. When fully
charged, RAMP can exceed SOURCE by 6 V, but the reference is internally clamped to 42 mV, limiting load
current to 42 mV/RSENSE. When the output is disabled via OV, UV, or due to a load fault, the RAMP capacitor is
discharged and held low to initialize for the next turn on.
The TPS2394 initiates ramp capacitor charging, and consequently load current slewing, at a reduced rate. This
reduced rate applies until the voltage on the RAMP pin is about 0.5 V. The maximum di/dt rate, as set by
Equation 2, is effective once the device switches to a 10-mA charging source.
RTN: Positive supply input. For negative voltage systems, this pin connects directly to the return node of the
input power bus.
SENSE: Current sense input. An external low-value resistor connected between SENSE and SOURCE is used
to monitor current magnitude. There are two internal device thresholds associated with the voltage at the SENSE
pin. During ramp-up of the load capacitance or during other periods of excessive demand, the linear current amp
(LCA) will regulate this voltage to 42 mV. Whenever the LCA is in current regulation mode, the FLTTIM capacitor
charges. If the LCA output is at its maximum, GAT is pulled 14 V above SOURCE. At this time, a fast fault such
as a short circuit can cause the SENSE voltage to rapidly exceed 120 mV (the overload threshold). In this case,
the GAT pin is pulled low rapidly, bypassing the fault timer.
SOURCE: Connection to the input supply negative rail.
UV: Under Voltage Comparator input. This input is typically connected to a voltage divider between RTN and
SOURCE to sense the magnitude of the input supply. If UV is more than 1.4 V above SOURCE, OV is less than
1.4 V above SOURCE, and there is no fault, the LCA will be enabled. In the event of a fault, pulling UV low or
OV high will reset the fault latch and allow restarting. UV can also be used as an active high logic enable input.
The under-voltage comparator hysteresis is programmed by the equivalent resistance seen looking into the
divider at the UV input.
6
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
AMBIENT TEMPERATURE
1500
UNDERVOLTAGE PULL-UP CURRENT
vs
AMBIENT TEMPERATURE
-9.0
V(RTN) = 0 V
V(RTN) = 0 V
900
600
-48 V ≤ V(SOURCE) ≤ -20 V
VIN(UV) - V(SOURCE) = 25 V
-9.4
V(SOURCE) = -80 V
V(SOURCE) = -48 V
V(SOURCE) = -20 V
V(SOURCE) = -12 V
300
IHYS_UV - Source Current - mA
ICC - Supply Current - mA
1200
-9.8
-10.2
-10.6
0
-40
-15
10
35
60
TA - Ambient Temperature - °C
-11.0
-40
85
-15
10
35
60
TA - Ambient Temperature - °C
85
Figure 1.
Figure 2.
GAT HIGH-LEVEL OUTPUT VOLTAGE
vs
AMBIENT TEMPERATURE
RAMP OUTPUT CURRENT
vs
AMBIENT TEMPERATURE, REDUCED RATE MODE
-460
16
V(RTN) = 0 V
VOUT(RAMP) - V(SOURCE) = 0.25 V
VOH - Output Voltage - V
12
V(SOURCE) = -48 V
ISRC1 - RAMP Output Current - nA
-480
V(SOURCE) = -20 V
8
V(SOURCE) = -12 V
4
V(RTN) = 0 V
VIN(SENSE) = V(SOURCE) = 0 V
IOUT(GAT) = -10 mA
-15
V(SOURCE) = -12 V
-520
-540
V(SOURCE) = -48 V
V(SOURCE) = -36 V
-560
0
-40
-500
10
35
60
TA - Ambient Temperature - °C
85
-580
-40
Figure 3.
-15
10
35
60
TA - Ambient Temperature - °C
85
Figure 4.
7
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TYPICAL CHARACTERISTICS (continued)
RAMP OUTPUT CURRENT
vs
AMBIENT TEMPERATURE, NORMAL RATE MODE
TIMER CHARGING CURRENT
vs
AMIBENT TEMPERATURE
-8.5
-46
V(RTN) = 0 V
V(FLTTIM) - V(SOURCE) = 2 V
-80 V ≤ V(SOURCE) ≤ -12 V
-80 V ≤ V(SOURCE) ≤ -20 V
-9.1
ICHG - Charging Current - mA
ISCR2 - RAMP Output Current - mA
Average for VOUT(RAMP) - V(SOURCE) = 1V, 3V
V(RTN) = 0 V
-9.7
-10.3
-48
-52
-54
-10.9
-11.5
-40
-15
10
35
60
TA - Ambient Temperature - °C
-58
85
-40
Figure 6.
TIMER DISCHARGE CURRENT
vs
AMIBENT TEMPERATURE
FAULT LATCH THRESHOLD VOLTAGE
vs
AMIBENT TEMPERATURE
V(RTN) = 0 V
V(SOURCE) = -48 V
Relative to SOURCE
-80 V ≤ V(SOURCE) ≤ -20 V
VFLT - Fault Latch Threshold - V
IDSG - Discharge Current - mA
85
4.25
V(RTN) = 0 V
V(FLTTIM) - V(SOURCE) = 2 V
0.40
0.35
0.30
0.25
0.20
-40
10
35
60
TA - Ambient Temperature - °C
Figure 5.
0.50
0.45
-15
-15
10
35
60
TA - Ambient Temperature - °C
85
4.15
4.05
3.95
3.85
3.75
-40
Figure 7.
-15
10
35
60
TA - Ambient Temperature - °C
85
Figure 8.
8
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FUNCTIONAL BLOCK DIAGRAM
RTN
1
UV
Input UV
Comparator
+
3
1.4 V
Input OV
Comparator
OV
Disable
4
1.4 V
+
2
FLT
Fault Latch
120 mV
4 ms
Filter
+
Fault
Timer
Retry
Timer
S
Q
R
Q
Overload
Comparator
FLTTIM
5
SENSE
10
+
Linear Current
Amp
99R
RAMP
11 GAT
6
Disable
42 mV
R
Power Good
Detection
12
PG
+
14
13
NC
NC
7
SOURCE
9
NC
8
NC
9
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APPLICATION INFORMATION
RTN
CLOAD
R1
RLOAD
1
RTN
POWER GOOD
12
PG
FAULT
2
FLT
GAT 11
SENSE 10
TPS2394
3
SOURCE
OV
FLTTIM
R3
RSENSE
UV
R2
4
Q1
5
CFLT
7
NC
9
NC
8
RAMP
NC
NC
6
14
13
CRAMP
-Vin
Figure 9. Typical Application
10
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APPLICATION INFORMATION
Setting the Sense Resistor Value
Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation
is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage
V(SENSE-SOURCE) to its internal reference. Once the voltage at the RAMP pin exceeds approximately 4 V, this
limit is the clamp voltage, VREF_K. Therefore; a maximum sense resistor value can be determined from
Equation 1.
34 mV
RSENSE £
IIMAX
(1)
Where:
RSENSE is the sensing resistor value
IIMAX is the minimum desired current limit
When setting the sense resistor value, it is important to consider two factors, the minimum current limit that may
be imposed by the TPS2394, and the maximum load under normal operation of the module. For the first factor,
the specification minimum clamp value is used, as seen in Equation 1. Second factor is to ensure the peak
operating load current is less than IIMAX. One example of this is a switching converter which draws higher input
current, for a given power output, when the output is at the low end of its voltage range. To avoid current limit
operation under normal loading, some margin should be designed in between this maximum anticipated load and
the minimum current limit level, or IIMAX > ILOAD(max), for Equation 1.
For example, using a 10-mΩ sense resistor for a nominal 2-A load application provides a minimum of 1.4 A of
overhead for load variance/margin. Typical bulk capacitor charging current during turn-on is 4.2 A
(42 mV/10 mΩ).
Setting the Inrush Slew Rate
The TPS2394 device enables user-programming of the maximum current slew rate during load start-up events. A
capacitor tied to the RAMP pin (CRAMP in the typical application diagram) controls the di/dt rate. Once the sense
resistor value has been established, a value for CRAMP, in microfarads, can be determined from Equation 2.
11.3
CRAMP =
æ di ö
100 ´ RSENSE ´ ç ÷
è dt ø (max)
(2)
Where:
RSENSE is the sense resistor value in Ω
(di/dt)(max) is the desired maximum slew rate in A/s
For example, if the desired slew rate for the typical application shown is 1500 mA/ms, the calculated value for
CRAMP is about 7500 pF. Selecting the next larger standard value of 8200 pF provides some margin for capacitor
and sense resistor tolerances.
Setting the Fault Timing Capacitor
The fault timeout period is established by the value of the capacitor connected to the FLTTIM pin, CFLT. The
timeout period permits riding out spurious current glitches and surges that may occur during operation of the
system, and prevents indefinite sourcing into faulted loads. However, to ensure smooth voltage ramping under all
conditions of load capacitance and input supply potential, the minimum timeout should be set to accommodate
these system variables. To do this, a rough estimate of the maximum voltage ramp time for a completely
discharged plug-in card provides a good basis for setting the minimum timer delay. This section presents a quick
procedure for calculating the timing capacitance requirement. However, for proper operation of the TPS2394,
there is an absolute minimum value of 0.01-µF for CFLT. This minimum requirement overrides any smaller results
of Equation 7 and Equation 8.
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Due to the three-phase nature of the load current at turn-on, the load voltage ramp has potentially three distinct
phases. This profile depends on the relative values of load capacitance, input DC potential, maximum current
limit and other factors. The first two phases are characterized by the two different slopes of the current ramp; the
third phase, if required to complete load charging, is the constant-current charging at IMAX. Considering the two
current ramp phases to be one period at an average di/dt simplifies calculation of the required timing capacitor.
For the TPS2394, the typical duration of the soft-start period, tSS, is given by Equation 3.
tSS = 1260 ´ CRAMP
(3)
Where:
tSS is the soft-start period in ms
CRAMP is given in µF
During this current ramp period, the load voltage magnitude which is attained is estimated by Equation 4.
i AVG
2
VLSS =
´ (tSS )
2 × CLOAD × CRAMP × 100 × RSENSE
(4)
Where:
VLSS is the load voltage reached during soft-start
iAVG is 3.18 µA for the TPS2394
CLOAD is the load capacitance in Farads
tSS is the soft-start period in s
The quantity iAVG in Equation 4 is a weighted average of the two charge currents applied to CRAMP during turn-on,
considering the typical output values.
If the result of Equation 4 is larger than the maximum input supply value, then the load can be expected to
charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than
the maximum supply input, VIN(MAX), the HSPM transitions to the constant-current charging of the load. The
remaining amount of time required at IMAX is determined from Equation 5.
tCC =
CLOAD ´
(VIN(MAX)
- VLSS
)
VREF_K(MIN)
RSENSE
(5)
Where:
tCC is the constant-current voltage ramp time, in seconds
VREF_K(MIN) is the minimum clamp voltage, 34 mV
With this information, the minimum recommended value timing capacitor CFLT can be determined. The delay time
needed will be either a time tSS2 or the sum of tSS2 and tCC, according to the estimated time to charge the load.
The quantity tSS2 is the duration of the normal rate current ramp period, and is given by Equation 6.
t SS2 = 0.35 ´ CRAMP
(6)
Where:
CRAMP is given in µF
Since fault timing is generated by the constant-current charging of CFLT, the capacitor value is determined from
either Equation 7 or Equation 8, as appropriate.
54 ´ t SS2
CFLT(MIN) =
3.75
(7)
54 ´ (t SS2 + t CC )
CFLT(MIN) =
3.75
(8)
Where:
CFLT(MIN) is the recommended capacitor value, in µ-Farads
tSS2 is the result of Equation 6, in seconds
tCC is the result of Equation 5, in seconds
12
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2394
TPS2394
www.ti.com
SLVSAA9 – AUGUST 2010
Continuing this calculation example, using a 220-µF input capacitor (CLOAD), Equation 3 and Equation 4 estimate
the load voltage ramping to approximately –45 V during the soft-start period. If the module should operate down
to –72-V input supply, approximately another 1.4 ms of constant-current charging may be required. Therefore,
Equation 6 and Equation 8 are used to determine CFLT(MIN), and the result is approximately 0.039-µF.
Setting the Undervoltage and Overvoltage Thresholds
The UV and OV pins can be used to set the undervoltage (VUV) and overvoltage (VOV) thresholds of the hot swap
circuit. When the input supply is below VUV or above VOV, the GAT pin is held low, disconnecting power from the
load, and the PG output is deasserted. When input voltage is within the UV/OV window, the GAT pin drive is
enabled, assuming all other input conditions are valid for turn-on.
Threshold hysteresis is provided via two internal sources which are switched to either pin whenever the
corresponding input level exceeds the internal 1.4-V reference. The additional bias shifts the pin voltage in
proportion to the external resistance connected to it. This small voltage shift at the device pin is gained up by the
external divider to input supply levels.
(a)
(b)
GND
GND
R1
200 kΩ
1%
1
R1
1
R8
RTN
RTN
3 UV
R2
4.99 kΩ
1%
3 UV
TPS2394
(1)
TPS2394
4 OV
R3
3.92 kΩ
1%
(1)
4 OV
R2
SOURCE
SOURCE
R9
7
-48V
7
-48V
V UV_L = R1 + R2 + R3 x V THUV
R2 R3
V UV_L = R1 + R2 x V THUV
R2
V OV_L = R1 + R2 + R3 x V THOV -I HYSUV x R1
R3
V OV_L = R8 + R9 x V THOV
R9
Note (1): Additional details omitted for clarity.
Figure 10. Programming the Undervoltage and Overvoltage Thresholds
The UV and OV thresholds can be individually programmed with a three-resistor divider connected to the
TPS2394 as shown in the typical application diagram, and again in Figure 10a. When the desired trip voltages
and undervoltage hysteresis have been established for the protected board, the resistor values needed can be
determined from the following equations. First, select the top leg of the divider (R1 in the diagram) to obtain the
threshold hysteresis. This value is calculated using Equation 9.
VHYS_UV
R1 =
10 μA
(9)
Where:
VHYS_UV is the undervoltage hysteresis value
For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input
supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then Equation 9 yields
R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and R3.
é
ù
VUV_L
1.4 ´ R1
ú
´ ê1 R2 =
-5
ê
VUV_L - 1.4
´ R1 ú
VOV_L + 10
ëê
ûú
(10)
(
)
(
)
13
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2394
TPS2394
SLVSAA9 – AUGUST 2010
R3 =
www.ti.com
1.4 × R1 × VUV_L
(VUV_L
- 1.4
) ´ (VOV_L + 10-5 × R1)
(11)
Where:
VUV_L is the UVLO threshold when the input supply is low; i.e., less than VUV, and
VOV_L is the OVLO threshold when the input supply is low; i.e., less than VOV
Referring to Figure 10a, Equation 10 and Equation 11 produce R2 = 4.909 kW (4.99 kΩ selected) and R3 =
3.951 kΩ (3.92 kΩ selected), as shown. For the selected values, the expected nominal supply thresholds are
VUV_L = 32.8 V, VUV_H = 30.8 V, and VOV_L = 72.6 V. The hysteresis of the overvoltage threshold, as seen at the
supply inputs, is given by the quantity (10 µA) × (R1 + R2). For the majority of applications, this value is almost
the same as the UV hysteresis, since typically R1 >> R2.
If more independent control is needed for the OVLO hysteresis, there are several options. One option is to use
separate dividers for both the UV and OV pins, as shown in Figure 10b. In this case, once R1 and R8 have been
selected for the required hysteresis per Equation 9, and values for the bottom resistors in the divider (R2 and R9
in Figure 10b) can be calculated using Equation 12.
VREF
R XVLO =
´ R(TOP)
VXV_L - VREF
(
)
(12)
Where:
RXVLO is R2 or R9
R(TOP) is R1 or R8 as appropriate for the threshold being set
VXV_L is the under (VUV_L) or overvoltage (VOV_L) threshold at the supply input, and
VREF is either VTHUV or VTHOV from the specification table, as required for the resistor being calculated.
Reverse Voltage Protection
In some applications, it may be necessary to protect the TPS2394 against reverse polarity supply connections or
input transients. If the potential at SOURCE pin rises above that of the RTN pin, device damage may result. If
the application environment is such that these conditions are anticipated, a small-signal diode should be inserted
between the supply return bus and the TPS2394 RTN pin, as shown in the Typical Application diagram. A 75-V
to 100-V rated device (VRRM), such as MMBD4148 or BAV19, is recommended.
14
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2394
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
TPS2394PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
TPS2394PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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