STMICROELECTRONICS VN5050AJTR-E

VN5050AJ-E
Single channel high side driver with analog
current sense for automotive applications
Features
Max supply voltage
VCC
41 V
Operating voltage range
VCC
4.5 to 36V
Max On-State resistance
RON
50 mΩ
Current limitation (typ)
ILIMH
16.5 A
Off state supply current
IS
2 µA
■
PowerSSO-12
– Reverse battery protection ( see
Application schematic)
– Electrostatic discharge protection
Application
General features
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
All types of resistive, inductive and capacitive
loads
■
Suitable as LED driver
Description
■
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
■
Protection
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shut down
Table 1.
■
The VN5050AJ-E is a monolithic device made
using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
with one side connected to ground. Active VCC pin
voltage clamp protects the device against low
energy spikes (see ISO7637 transient
compatibility table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Device summary
Order codes
Package
PowerSSO-12
September 2007
Tube
Tape and Reel
VN5050AJ-E
VN5050AJTR-E
Rev 4
1/32
www.st.com
32
Contents
VN5050AJ-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
4
6
2/32
3.1.1
Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . 22
3.1.2
Solution 2: diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . 23
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3
MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 24
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VN5050AJ-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
List of figures
VN5050AJ-E
List of figures
Figure 1.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3.
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4.
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5.
Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6.
IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7.
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8.
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9.
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28. PowerSSO-12 PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 25
Figure 30. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 26
Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . 26
Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 34. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/32
VN5050AJ-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
VCC
VCC
CLAMP
UNDERVOLTAGE
PwCLAMP
DRIVER
OUTPUT
GND
ILIM
VDSLIM
LOGIC
PwrLIM
INPUT
OVERTEMP.
IOUT
K
CURRENT
SENSE
CS_DIS
Table 2.
Pin function
Name
VCC
OUTPUT
GND
INPUT
Function
Battery connection
Power output
Ground connection. Must be reverse battery protected by an external
diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state
CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current
CS_DIS
Active high CMOS compatible pin, to disable the current sense pin
5/32
Block diagram and pin description
Figure 2.
VN5050AJ-E
Configuration diagram (top view)
TAB = Vcc
N.C.
GND
INPUT
CURRENT SENSE
CS_DIS
N.C.
Table 3.
N.C.
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
Suggested connections for unused and n.c. pins
Connection / Pin
Current sense
N.C.
Output
Input
CS_DIS
Floating
N.R.
X
X
X
X
To Ground
Through 1kΩ
resistor
X
N.R.(1)
Through 10kΩ
resistor
Through 10kΩ
resistor
1. Not recommended
6/32
12
11
10
9
8
7
1
2
3
4
5
6
VN5050AJ-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
VF
ICSD
IIN
IOUT
CS_DIS
OUTPUT
VCC
INPUT
ISENSE
CURRENT SENSE
VCSD
VIN
GND
VOUT
VSENSE
IGND
Note:
VF = VOUT - VCC during reverse battery condition
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
0.3
V
- IGND
DC reverse ground pin current
200
mA
Internally
limited
A
30
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
200
mA
VCC-41
+VCC
V
V
104
mJ
IOUT
- IOUT
IIN
ICSD
DC output current
Reverse DC output current
-ICSENSE DC Reverse CS pin current
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy (single pulse)
(L= 3mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
7/32
Electrical specifications
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VESD
Electrostatic discharge (Human Body Model: R=1.5kΩ; C=100pF)
- INPUT
- CURRENT SENSE
- CS_DIS
- OUTPUT
- VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Tj
Tstg
2.2
VN5050AJ-E
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Rthj-case Thermal resistance junction-case (MAX)
Rthj-amb Thermal resistance junction-ambient (MAX)
8/32
Max value
Unit
2.7
°C/W
See Figure 29.
°C/W
VN5050AJ-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless
otherwise specified
Table 6.
Power section
Symbol
Parameter
VCC
Operating supply
voltage
VUSD
Test conditions
Min. Typ. Max.
13
36
V
Undervoltage
shutdown
3.5
4.5
V
VUSDhyst
Undervoltage
shutdown hysteresis
0.5
RON
On state resistance
IOUT=2A; Tj=25°C
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
Vclamp
Clamp voltage
IS=20mA
IS
Supply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
Off state output current
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
Output - VCC diode
voltage
-IOUT=2A; Tj=150°C
IL(off)
VF
4.5
Unit
41
0
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
1.5
5(1)
3
µA
mA
0.01
3
5
µA
0.7
V
1. PowerMOS leakage included
Table 7.
Symbol
Switching (VCC=13V, Tj=25°C)
Parameter
Test conditions
Min.
Typ.
Max. Unit
td(on)
Turn-on delay time
RL= 6.5Ω (see Figure 8.)
20
µs
td(off)
Turn-off delay time
RL= 6.5Ω (see Figure 8.)
40
µs
(dVOUT/dt)on Turn-on voltage slope
RL= 6.5Ω
See
Figure 20
V/ µs
(dVOUT/dt)off Turn-off voltage slope
RL= 6.5Ω
See
Figure 22
V/ µs
WON
Switching energy losses
during twon
RL= 6.5Ω (see Figure 8.)
0.20
mJ
WOFF
Switching energy losses
during twoff
RL= 6.5Ω (see Figure 8.)
0.3
mJ
9/32
Electrical specifications
Table 8.
Symbol
VN5050AJ-E
Logic input
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Test conditions
VIN=0.9V
IIN=1mA
IIN=-1mA
CS_DIS low level voltage
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
Symbol
ICSD=1mA
ICSD=-1mA
2.1
V
10
V
5.5
7
V
V
0.9
V
-0.7
1
µA
2.1
V
10
µA
V
5.5
7
-0.7
Parameter
Test conditions
V
V
VCC = 13V
5V<VCC<36V
Short circuit current
VCC=13V TR<Tj<TTSD
during thermal cycling
TTSD
Shutdown
temperature
TR
Reset temperature
TRS
Thermal reset of
STATUS
Typ.
Max.
Unit
12
16.5
23
23
A
A
7
150
175
A
200
TRS + 1 TRS + 5
135
Thermal hysteresis
(TTSD-TR)
Turn-off output voltage
IOUT=2A; VIN=0; L=6mH
clamp
Output voltage drop
limitation
Min.
IOUT=0.1A; Tj= -40°C...+150°C
(see Figure 9.)
°C
°C
°C
7
°C
VCC-41 VCC-46 VCC-52
V
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles
10/32
µA
Protection and diagnostics(1)
IlimL
VON
V
0.25
DC Short circuit
current
VDEMAG
0.9
µA
VCSD=2.1V
IlimH
THYST
Unit
1
VCSD=0.9V
VCSD(hyst) CS_DIS hysteresis voltage
Table 9.
Max.
0.25
Input clamp voltage
CS_DIS clamp voltage
Typ.
VIN=2.1V
VCSDL
VCSCL
Min.
VN5050AJ-E
Electrical specifications
Table 10.
Symbol
K0
K1
dK1/K1
(1)
Parameter
dK2/K2(1)
K3
IOUT=0.05A; VSENSE=0.5V; VCSD=0V;
Tj= -40°C...150°C
IOUT/ISENSE
IOUT=1A; VSENSE=0.5V; VCSD=0V;
Tj=-40°C...150°C
IOUT=1A; VSENSE=0.5V; VCSD=0V;
Tj= 25°C...150°C
IOUT=1A; VSENSE= 0.5V;
Current sense ratio
VCSD=0V;
drift
TJ=-40 °C to 150 °C
ISENSE0
IOUT=2A; VSENSE=4V; VCSD=0V;
Tj=-40°C...150°C
IOUT=2A; VSENSE=4V; VCSD=0V;
Tj=25°C...150°C
IOUT=2 A; VSENSE= 4 V;
Current sense ratio
VCSD=0V;
drift
TJ=-40 °C to 150 °C
IOUT/ISENSE
(1)
Test conditions
IOUT/ISENSE
IOUT/ISENSE
K2
dK3/K3
Current sense (8V<VCC<16V)
IOUT=4A; VSENSE=4V; VCSD=0V;
Tj=-40°C...150°C
IOUT=4A; VSENSE=4V; VCSD=0V;
Tj=25°C...150°C
IOUT=4 A; VSENSE= 4 V;
Current sense ratio
VCSD=0V;
drift
TJ=-40 °C to 150 °C
Analog sense
leakage current
Min. Typ. Max. Unit
1100 2440 3480
1600 2030 2580
1630 2030 2430
-10
+10
%
1770 2000 2310
1800 2000 2200
-6
+6
%
1860 1970 2140
1870 1970 2120
-3
+3
%
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
0
0
1
2
µA
µA
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj=-40°C...150°C
0
1
µA
5
VSENSE
Max analog sense
output voltage
IOUT=2A; VCSD=0V
VSENSEH
Analog sense
output voltage in
overtemperature
condition
VCC=13V; RSENSE=10KΩ
9
V
ISENSEH
Analog sense
output current in
overtemperature
condition
VCC=13V, VSENSE=5V
8
mA
VSENSE<4V, 0.5A<Iout<4A
Delay Response
tDSENSE1H time from falling
ISENSE=90% of ISENSEmax
edge of CS_DIS pin (see Figure 4.)
V
50
100
µs
11/32
Electrical specifications
Table 10.
Symbol
VN5050AJ-E
Current sense (8V<VCC<16V)
Parameter
Test conditions
Min. Typ. Max. Unit
VSENSE<4V, 0.5A<Iout<4A
Delay response
tDSENSE1L time from rising
ISENSE=10% of ISENSEmax
edge of CS_DIS pin (see Figure 4.)
5
20
µs
Delay response
tDSENSE2H time from rising
edge of INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max
(see Figure 4.)
80
300
µs
Delay response
time between rising
edge of output
∆tDSENSE2H
current and rising
edge of current
sense
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX
IOUTMAX=2A (see Figure 5)
60
µs
Delay response
tDSENSE2L time from falling
edge of INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max
(see Figure 4.)
250
µs
100
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
12/32
tDSENSE1L
tDSENSE1H
tDSENSE2L
VN5050AJ-E
Electrical specifications
Figure 5.
Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
VIN
∆tDSENSE2H
t
IOUT
IOUTMAX
90% IOUTMAX
t
ISENSE
ISENSEMAX
90% ISENSEMAX
t
13/32
Electrical specifications
Figure 6.
VN5050AJ-E
IOUT/ISENSE Vs. IOUT (see Table 10. for details)
Iout / Isense
2800
2600
max Tj = -40 °C to 150 °C
2400
2200
max Tj = 25 °C to 150 °C
typical value
2000
min Tj = 25 °C to 150 °C
1800
min Tj = -40 °C to 150 °C
1600
1400
1200
1
1,5
2
2,5
3
3,5
4
4,5
IOUT (A)
Figure 7.
Maximum current sense ratio drift vs load current
dk/k(%)
15
10
5
0
-5
-10
-15
1
2
3
IOUT (A)
Note:
14/32
Parameter guaranteed by design; it is not tested
4
5
5
VN5050AJ-E
Electrical specifications
Table 11.
Truth table
INPUT
OUTPUT
SENSE (VCSD=0V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
Short circuit to GND
(Rsc ≤10 mΩ)
L
H
H
L
L
L
0
0 if Tj < TTSD
VSENSEH if Tj > TTSD
Short circuit to VCC
L
H
H
H
0
< Nominal
Negative output voltage
clamp
L
L
0
Conditions
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit
Figure 8.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
INPUT
td(on)
td(off)
t
15/32
Electrical specifications
Figure 9.
VN5050AJ-E
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
16/32
Iout
VN5050AJ-E
Electrical specifications
Table 12.
Electrical transient requirements
ISO 7637-2:
2004(E)
Test levels
Test pulse
III
IV
Number of
pulses or
test times
1
-75V
-100V
5000 pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37V
+50V
5000 pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100V
-150V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75V
+100V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6V
-7V
1 pulse
100 ms, 0.01
Ω
5b(2)
+65V
+87V
1 pulse
400 ms, 2 Ω
Burst cycle/pulse
repetition time
Delays and
Impedance
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
2a
3a
3b
4
5b(2)
C
C
C
C
C
C
C
C
C
C
C
C
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
E
17/32
Electrical specifications
VN5050AJ-E
Figure 10. Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
Tj
TR
TTSD
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT
current power
limitation limitation
thermal cycling
SHORTED LOAD
18/32
NORMAL LOAD
VN5050AJ-E
2.4
Electrical specifications
Electrical characteristics curves
Figure 11. Off state output current
Figure 12. High level input current
TBD
Figure 13. Input clamp voltage
Figure 14. Input low level
Figure 15. Input high level
Figure 16. Input hysteresis voltage
19/32
Electrical specifications
VN5050AJ-E
Figure 17. On state resistance vs. Tcase
Figure 18. On state resistance vs. VCC
Figure 19. Undervoltage shutdown
Figure 20. Turn-on voltage slope
Figure 21. ILIMH Vs. Tcase
Figure 22. Turn-off voltage slope
TBD
20/32
VN5050AJ-E
Figure 23. CS_DIS high level voltage
Electrical specifications
Figure 24. CS_DIS clamp voltage
Figure 25. CS_DIS low level voltage
21/32
Application information
3
VN5050AJ-E
Application information
Figure 26. Application schematic
+5V
VCC
Rprot
CS_DIS
Dld
µC
Rprot
INPUT
OUTPUT
Rprot
CURRENT SENSE
GND
RSENSE
Cext
VGND
RGND
DGND
.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1
Solution 1: resistor in the ground line (RGND only).
This can be used with any type of load.
The following show how to dimension the RGND resistor:
1.
RGND ≤600mV / (IS(on)max)
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0 during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
22/32
VN5050AJ-E
Application information
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2
Solution 2: diode (DGND) in the ground line.
Note that a resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives
an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (j600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than those shown in the ISO T/R 7637/1 table.
3.3
MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup ≤Rprot ≤(VOHµC-VIH-VGND) / IIHmax
Equation 1:
For the following conditions:
VCCpeak= - 100V
Ilatchup ≥ 20mA
VOHµC ≥ 4.5V
5kΩ ≤Rprot ≤65kΩ.
Recommended values are:
Rprot =10kΩ, CEXT=10nF
23/32
Application information
3.4
VN5050AJ-E
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn off current versus inductance
100
A
A
C
C
B
B
I (A)
10
1
0,1
1
L (mH)
10
100
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
24/32
Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.
VN5050AJ-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 28. PowerSSO-12 PC Board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
25/32
Package and PCB thermal data
VN5050AJ-E
Figure 30. PowerSSO-12 thermal impedance junction ambient single pulse
ZTH (°C/W)
Footprint
100
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time (s)
10
100
1000
Equation 2: pulse calculation formula
Z
THδ
= R
TH
⋅ δ+Z
THtp
( 1 – δ)
where δ = tP/T
Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12(a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered
26/32
VN5050AJ-E
Package and PCB thermal data
Table 13.
Thermal parameter
Area/island (cm2)
Footprint
2
8
R1 (°C/W)
0.6
R2 (°C/W)
2.8
R3 (°C/W)
6.5
R4 (°C/W)
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1 (W.s/°C)
0.001
C2 (W.s/°C)
0.0025
C3 (W.s/°C)
0.022
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
27/32
Package information
5
Package information
5.1
ECOPACK® packages
VN5050AJ-E
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 32. PowerSSO-12™ package dimensions
28/32
VN5050AJ-E
Package information
Table 14.
PowerSSO-12™ mechanical data
Millimeters
Symbol
Min
Typ
Max
A
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0°
8°
X
2.200
2.800
Y
2.900
3.500
ddd
0.100
29/32
Package information
5.3
VN5050AJ-E
Packing information
Figure 33. PowerSSO-12 tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 34. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
30/32
No components
500mm min
VN5050AJ-E
6
Revision history
Revision history
Table 15.
Document revision history
Date
Revision
24-Jan-2006
1
Initial release.
Jul-2006
2
Minor updates.
3
Document reformatted.
Table 14: PowerSSO-12™ mechanical data, X and Y values (slug
dimensions) updated.
Table 10: Current sense (8V<VCC<16V) tDSENSE2H entry updated.
Figure 27: Maximum turn off current versus inductance and Table 13:
Thermal parameter updated.
4
Document reformatted and restructured.
Contents and lists of tables and figures added.
Figure 2: Configuration diagram (top view) updated: pins 1-6-7-12
N.C. (not connected).
Table 4: Absolute maximum ratings: EMAX entries updated.
Table 10 : dk1/k1, dk2/k2, dk3/k3, ∆tDSENSE2H added.
Figure 5: Delay response time between rising edge of ouput current
and rising edge of current sense (CS enabled) added.
Figure 6: IOUT/ISENSE Vs. IOUT (see Table 10. for details) updated.
Figure 7: Maximum current sense ratio drift vs load current added.
Table 12: Electrical transient requirements : test level values III and
IV for test pulse 5b and notes updated.
Figure 30: PowerSSO-12 thermal impedance junction ambient single
pulse corrected.
06-Feb-2007
13-Sep-2007
Changes
31/32
VN5050AJ-E
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32/32