VNQ5050AK-E Quad channel high side driver with analog current sense for automotive applications Features Parameters Max supply voltage Symbol Value VCC 41 V Operating voltage range VCC 4.5 to 36 V Max on-state resistance (per ch.) RON 50 mΩ Current limitation (typ) ILIMH 19 A Off-state supply current IS 2 µA(1) PowerSSO-24 – Reverse battery protection (see Figure 25) – Electrostatic discharge protection Application ■ All types of resistive, inductive and capacitive loads. ■ Suitable as LED driver. 1. Typical value with all loads connected. ■ ■ ■ General features: – Inrush current active management by power limitation – Very low standby current – 3.0V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – In compliance with the 2002/95/EC European directive Diagnostic functions: – Proportional load current sense – High current sense precision for wide current range – Current sense disable – Thermal shutdown indication – Very low current sense leakage Protection: – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of VCC – Thermal shutdown Table 1. Description The VNQ5050AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to a safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as the fault condition disappears. Device summary Order codes Package PowerSSO-24 September 2013 Tube Tape and Reel VNQ5050AK-E VNQ5050AKTR-E Doc ID 13329 Rev 10 1/31 www.st.com 1 Contents VNQ5050AK-E Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 4 6 2/31 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20 3.1.2 Solution 2: a diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . 21 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Microcontroller I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 13329 Rev 10 VNQ5050AK-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 13329 Rev 10 3/31 List of figures VNQ5050AK-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. 4/31 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of output current and rising edge of current sense (CS enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 24 PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25 Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 13329 Rev 10 VNQ5050AK-E 1 Block diagram and pin configuration Block diagram and pin configuration Figure 1. Block diagram VCC UNDERVOLTAGE VCC CLAMP OUTPUT1 PwCLAMP 1 GND DRIVER 1 ILIM 1 INPUT1 VDSLIM 1 LOGIC INPUT2 INPUT2 VCC Control & Protection CURRENT Equivalent to SENSE2 channel1 OVERTEMP. 1 INPUT3 INPUT3 IOUT1 K1 INPUT4 PwrLIM 1 OUTPUT2 VCC OUTPUT3 VCC CURRENT SENSE3 Control & Protection to CURRENT Equivalent SENSE4 channel1 CS_DIS CURRENT SENSE2 Control & Protection to CURRENT Equivalent SENSE3 channel1 INPUT4 CURRENT SENSE1 OUTPUT4 CURRENT SENSE4 Table 2. Pin functions Name VCC OUTPUTn GND INPUTn Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state CURRENT SENSEn Analog current sense pin, delivers a current proportional to the load current CS_DIS Active high CMOS compatible pin, to disable the current sense pin Doc ID 13329 Rev 10 5/31 Block diagram and pin configuration Figure 2. VNQ5050AK-E Configuration diagram (top view) VCC OUTPUT1 GND OUTPUT1 INPUT1 OUTPUT1 CURRENT SENSE1 OUTPUT2 INPUT2 OUTPUT2 CURRENT SENSE2 OUTPUT2 INPUT3 OUTPUT3 CURRENT SENSE3 OUTPUT3 INPUT4 OUTPUT3 CURRENT SENSE4 OUTPUT4 CS_DIS. OUTPUT4 VCC OUTPUT4 TAB = VCC Table 3. Suggested connections for unused and not connected pins Connection/pin Current sense N.C. Output Input CS_DIS Floating N.R.(1) X X X X To ground Through 1 kΩ resistor X N.R. Through 10 kΩ resistor Through 10 kΩ resistor 1. Not recommended. 6/31 Doc ID 13329 Rev 10 VNQ5050AK-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions IS VCC OUTPUTn CS_DIS VOUTn ISENSEn IINn VINn VCC IOUTn ICSD VCSD VFn CURRENT SENSEn INPUTn VSENSEn GND IGND Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stress values that exceed those listed in the “Absolute maximum ratings” table can cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions greater than those, indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V -VCC Reverse DC supply voltage 0.3 V - IGND DC reverse ground pin current 200 mA Internally limited A 20 A DC input current -1 to 10 mA DC current sense disable input current -1 to 10 mA 200 mA VCC-41 +VCC V V 104 mJ IOUT DC output current - IOUT Reverse DC output current IIN ICSD -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (single pulse) (L=3 mH; RL=0 Ω; Vbat=13.5 V; Tjstart=150 ºC; IOUT = IlimL(Typ.)) Doc ID 13329 Rev 10 7/31 Electrical specifications Table 4. Absolute maximum ratings (continued) Symbol Value Unit VESD Electrostatic discharge (human body model: R=1.5KΩ; C=100pF) – Input – Current sense – CS_DIS – Output – VCC 4000 2000 4000 5000 5000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 °C Storage temperature -55 to 150 °C Tj Tstg 2.2 Parameter Thermal data Table 5. Symbol 8/31 VNQ5050AK-E Thermal data Parameter Max value Unit Rthj-case Thermal resistance junction-case (With one channel ON) 2.8 °C/W Rthj-amb Thermal resistance junction-ambient See Figure 29 °C/W Doc ID 13329 Rev 10 VNQ5050AK-E 2.3 Electrical specifications Electrical characteristics Values specified in this section are for 8 V<VCC<36 V, -40 °C<Tj<150 °C, unless otherwise stated. Table 6. Power section Symbol Parameter VCC Operating supply voltage 4.5 VUSD Undervoltage shutdown VUSDhyst Undervoltage shutdown hysteresis RON Vclamp IS IL(off) VF Test conditions Min. Typ. On-state resistance IOUT=2 A; Tj=25 °C IOUT=2 A; Tj=150 °C IOUT=2 A; VCC=5 V; Tj=25 °C Clamp voltage IS=20 mA Supply current Off-State; VCC=13 V; Tj=25 °C; VIN=VOUT=VSENSE=VCSD=0 V On-State; VCC=13 V; VIN=5 V; IOUT=0 A VIN=VOUT=0 V; VCC=13 V; Tj=25 °C Off-state output current(2) VIN=VOUT=0 V; VCC=13 V; Tj=125 °C Output - VCC diode voltage(2) Max. Unit 13 36 V - 3.5 4.5 V - 0.5 - V - - 50 100 65 mΩ mΩ mΩ 41 46 52 V 2(1) 5(1) µA 8 14 mA 0.01 3 - 0 0 -IOUT=2 A; Tj=150 °C µA 5 - - 0.7 V 1. PowerMOS leakage included. 2. For each channel. Table 7. Symbol Switching (VCC=13V) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL= 6.5 Ω (see Figure 6) - 20 - µs td(off) Turn-off delay time RL= 6.5 Ω (see Figure 6) - 45 - µs (dVOUT/dt)on Turn-on voltage slope RL= 6.5 Ω - See Figure 19 - V/µs (dVOUT/dt)off Turn-off voltage slope RL= 6.5 Ω - See Figure 21 - V/µs WON Switching energy losses during twon RL= 6.5 Ω (see Figure 6) - 0.15 - mJ WOFF Switching energy losses during twoff RL= 6.5 Ω (see Figure 6) - 0.3 - mJ Doc ID 13329 Rev 10 9/31 Electrical specifications Table 8. Symbol K0 K1 dK1/K1(1) K2 dK2/K2 Current sense (8V<VCC<16V) Parameter Test conditions IOUT/ISENSE IOUT= 0.05 A; VSENSE= 0.5 V; VCSD=0 V; Tj= -40 °C...150 °C IOUT/ISENSE IOUT= 1 A; VSENSE= 0.5 V; VCSD=0 V; Tj= -40 °C...150 °C Tj= 25 °C...150 °C IOUT= 1 A; VSENSE= 0.5 V; Current sense ratio drift VCSD= 0 V; TJ= -40 °C to 150 °C IOUT= 2 A; VSENSE= 4 V; VCSD= 0 V; Tj= -40 °C...150 °C Tj= 25 °C...150 °C IOUT/ISENSE (1) K3 dK3/K3(1) ISENSE0 10/31 VNQ5050AK-E IOUT= 2 A; VSENSE= 4 V; Current sense ratio drift VCSD= 0 V; TJ= -40 °C to 150 °C IOUT= 4 A; VSENSE= 4 V; VCSD= 0 V; Tj= -40 °C...150 °C Tj= 25 °C...150 °C IOUT/ISENSE IOUT= 4 A; VSENSE= 4 V; Current sense ratio drift VCSD= 0 V; TJ= -40 °C to 150 °C Analog sense leakage current Min. Typ. Max. Unit 1340 2420 3460 1370 1860 2510 1510 1860 2210 -10 - 10 % 1590 1760 2140 1600 1760 1930 -8 - 8 1650 1740 1950 1650 1740 1830 % - -5 - 5 % IOUT= 0 A; VSENSE= 0 V; VCSD= 5 V; VIN= 0 V; Tj= -40 °C...150 °C 0 - 1 µA VCSD= 0 V; VIN= 5 V; Tj= -40 °C...150 °C 0 - 2 µA IOUT= 2 A; VSENSE= 0 V; VCSD= 5 V; VIN= 5 V; Tj= -40 °C...150 °C 0 - 1 µA IOL Openload ON state current detection threshold VIN = 5 V, ISENSE= 5 µA 4 - 20 mA VSENSE Max analog sense output voltage IOUT= 4 A; VCSD= 0 V 5 - - V VSENSEH Analog sense output voltage in over temperature condition VCC= 13 V; RSENSE= 10 KΩ - 9 - V Doc ID 13329 Rev 10 VNQ5050AK-E Electrical specifications Table 8. Current sense (8V<VCC<16V) (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VCC= 13 V; VSENSE= 5 V - 8 - mA Delay response time tDSENSE1H from falling edge of CS_DIS pin VSENSE<4 V, 0.5 A<Iout<4 A ISENSE= 90 % of ISENSE max (see Figure 4) - 50 100 µs Delay response time from rising edge of CS_DIS pin VSENSE<4 V, 0.5 A<Iout<4 A ISENSE=10 % of ISENSE max (see Figure 4) - 5 20 µs Delay response time tDSENSE2H from rising edge of INPUT pin VSENSE<4 V, 0.5 A<Iout<4 A ISENSE=90 % of ISENSE max (see Figure 4) - 80 250 µs Delay response time between rising edge of ΔtDSENSE2H output current and rising edge of current sense VSENSE<4 V, ISENSE =90 % of ISENSEMAX, IOUT=90 % of IOUTMAX IOUTMAX=2 A (see Figure 5) - - 65 µs VSENSE<4 V, 0.5 A<Iout<4 A ISENSE=10 % of ISENSE max (see Figure 4) - 100 250 µs Analog sense output current in over temperature condition ISENSEH tDSENSE1L tDSENSE2L Delay response time from falling edge of INPUT pin 1. Parameter guaranteed by design; it is not tested. Table 9. Protection(1) Symbol Parameter Test conditions IlimH DC short circuit current VCC=13 V 5 V<VCC<36 V IlimL Short circuit current during thermal cycling VCC=13 V; TR<Tj<TTSD TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of STATUS THYST VDEMAG VON Min. Typ. Max. Unit 13.5 19 26.5 26.5 A A - 7 - A 150 175 200 °C - °C TRS + 1 TRS + 5 Thermal hysteresis (TTSD-TR) Turn-off output voltage clamp IOUT=2 A; VIN=0; L=6 mH Output voltage drop limitation IOUT=0.1 A; Tj=-40 °C...150 °C (see Figure 9) 135 - - °C - 7 - °C VCC-41 VCC-46 VCC-52 V - 25 - mV 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Doc ID 13329 Rev 10 11/31 Electrical specifications Table 10. VNQ5050AK-E Logic input Symbol Parameter VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Test conditions VIN= 0.9 V VIN= 2.1 V IIN= 1 mA IIN= -1 mA Input clamp voltage VCSDL CS_DIS low level voltage ICSDL Low level CS_DIS current VCSDH CS_DIS high level voltage ICSDH High level CS_DIS current VCSD=0.9 V VCSD=2.1 V VCSD(hyst) CS_DIS hysteresis voltage VCSCL Figure 4. CS_DIS clamp voltage ICSD= 1 mA ICSD= -1 mA Min. Typ. Max. Unit - - 0.9 V 1 - - µA 2.1 - - V - - 10 µA 0.25 - - V 7 V V 5.5 -0.7 - - 0.9 V 1 - - µA 2.1 - - V - - 10 µA 0.25 - - V 7 V V 5.5 -0.7 Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H 12/31 tDSENSE1L Doc ID 13329 Rev 10 tDSENSE1H tDSENSE2L VNQ5050AK-E Electrical specifications Figure 5. Delay response time between rising edge of output current and rising edge of current sense (CS enabled) VIN ΔtDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t Figure 6. Switching characteristics VOUT tWon tWoff 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) t Doc ID 13329 Rev 10 13/31 Electrical specifications VNQ5050AK-E Figure 7. IOUT/ISENSE vs IOUT Iout / Isense 2600 max Tj = -40 °C to 150 °C 2400 2200 2000 max Tj = 25 °C to 150 °C 1800 typical value min Tj = 25 °C to 150 °C 1600 1400 min Tj = -40 °C to 150 °C 1200 1000 1 1,5 2 2,5 3 3,5 4 IOUT (A) Figure 8. Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 1 1,5 2 2,5 IOUT (A) Note: Parameter guaranteed by design; it is not tested. 14/31 Doc ID 13329 Rev 10 3 3,5 4 4,5 5 VNQ5050AK-E Electrical specifications Table 11. Truth table Input Output Sense (VCSD=0 V)(1) Normal operation L H L H 0 Nominal Over temperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Short circuit to GND (Rsc ≤ 10 mΩ) L H H L L L 0 0 if Tj < TTSD VSENSEH if Tj > TTSD Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Conditions 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. Figure 9. Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Von/Ron(T) Doc ID 13329 Rev 10 Iout 15/31 Electrical specifications Table 12. VNQ5050AK-E Electrical transient requirements (part 1/3) ISO 7637-2: 2004(E) Test levels Number of pulses or test times Burst cycle/pulse repetition time Delays and Impedance test pulse III IV 1 -75 V -100 V 5000 pulses 0.5 s 5s 2 ms, 10 Ω 2a +37 V +50 V 5000 pulses 0.2 s 5s 50 µs, 2 Ω 3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω 3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω 4 -6 V -7 V 1 pulse - 100 ms, 0.01 Ω 5b(2) +65 V +87 V 1 pulse - 400 ms, 2 Ω Table 13. Electrical transient requirements (part 2/3) Test level results(1) ISO 7637-2: 2004(E) test pulse III IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b (2) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Table 14. 16/31 Electrical transient requirements (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 13329 Rev 10 VNQ5050AK-E 2.4 Electrical specifications Electrical characteristics curves Figure 10. Off-state output current Figure 11. Iloff (uA) High level input current Iih (uA) 0.09 5 4.5 0.08 Vin=2.1V Off state Vcc=13V Vin=Vout=0V 0.07 4 3.5 0.06 3 0.05 2.5 0.04 2 0.03 1.5 0.02 1 0.01 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Tc (°C) 75 100 125 150 175 Tc (°C) Figure 12. Input clamp voltage Figure 13. Input low level Vil (V) Vicl (V) 7 2 6.8 1.8 Iin=1mA 6.6 1.6 6.4 1.4 6.2 1.2 6 1 5.8 0.8 5.6 0.6 5.4 0.4 5.2 0.2 0 5 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 14. Input high level Figure 15. Input hysteresis voltage Vih (V) Vhyst (V) 4 1 3.5 0.9 0.8 3 0.7 2.5 0.6 2 0.5 1.5 0.4 0.3 1 0.2 0.5 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 13329 Rev 10 17/31 Electrical specifications VNQ5050AK-E Figure 16. On-state resistance vs Tcase Figure 17. On-state resistance vs VCC Ron (mOhm) Ron (mOhm) 100 100 90 90 Iout=2A Vcc=13V 80 80 70 70 60 60 50 50 40 40 Tc=150°C Tc=125°C 30 30 20 20 10 10 0 Tc=25°C Tc=-40°C 0 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 Tc (°C) 20 25 30 35 40 Vcc (V) Figure 18. Undervoltage shutdown Figure 19. Turn-on voltage slope Vusd (V) (dVout/dt)on (V/ms) 16 1000 900 14 Vcc=13V Rl=6.5Ohm 800 12 700 10 600 500 8 400 6 300 4 200 2 100 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 20. ILIMH vs Tcase Figure 21. Turn-off voltage slope Ilimh (A) (dVout/dt)off (V/ms) 1000 25 900 22.5 Vcc=13V Vcc=13V Rl=6.5Ohm 800 20 700 17.5 600 500 15 400 12.5 300 10 200 7.5 100 0 5 -50 -25 0 25 50 75 100 125 150 175 18/31 -50 -25 0 25 50 75 Tc (°C) Tc (°C) Doc ID 13329 Rev 10 100 125 150 175 VNQ5050AK-E Electrical specifications Figure 22. CS_DIS high level voltage Figure 23. CS_DIS clamp voltage Vcsdh (V) Vcsdcl (V) 4 8 3.5 7.5 3 7 2.5 6.5 2 6 1.5 5.5 1 5 0.5 4.5 Icsd=1mA 4 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 24. CS_DIS low level voltage Vcsdl (V) 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 13329 Rev 10 19/31 Application information 3 VNQ5050AK-E Application information Figure 25. Application schematic +5V VCC Rprot CS_DIS Dld μC Rprot IINPUT OUTPUT Rprot CURRENT SENSE GND RSENSE Cext VGND RGND DGND Note: Channel 2, 3, 4 have the same internal circuit as channel 1. 3.1 GND protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND ≤ 600 mV / (IS(on)max). 2. RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 20/31 Doc ID 13329 Rev 10 VNQ5050AK-E 3.1.2 Application information Solution 2: a diode (DGND) in the ground line. A resistor (RGND= 1 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. 3.3 Microcontroller I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V 5 kΩ ≤ Rprot ≤ 180 kΩ. Recommended values: Rprot = 10 kΩ, CEXT= 10 nF. Doc ID 13329 Rev 10 21/31 Application information VNQ5050AK-E Figure 26. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TR TTSD TRS INPUT CS_DIS ILIMH ILIML LOAD CURRENT VSENSEH SENSE CURRENT thermal cycling current power limitation limitation SHORTED LOAD 22/31 Doc ID 13329 Rev 10 NORMAL LOAD VNQ5050AK-E 3.4 Application information Maximum demagnetization energy (VCC = 13.5V) Figure 27. Maximum turn-off current versus inductance (for each channel) 100 A C B I (A) 10 1 0,1 1 L (mH) 10 100 A: Tjstart = 150°C single pulse B: Tjstart = 100°C repetitive pulse C: Tjstart = 125°C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL = 0 Ω. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 13329 Rev 10 23/31 Package and PC board thermal data VNQ5050AK-E 4 Package and PC board thermal data 4.1 PowerSSO-24 thermal data Figure 28. PowerSSO-24 PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77 mm x 86 mm, PCB thickness=1.6mm, Cu thickness=70 µm (front and back side), Copper areas: from minimum pad lay-out to 8 cm2). Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHj_amb(°C/W) 55 50 45 40 35 30 0 2 4 6 PCB Cu heatsink area (cm^2) 24/31 Doc ID 13329 Rev 10 8 10 VNQ5050AK-E Package and PC board thermal data Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) ZTH (°C/W) 1000 100 Footprint 2 cm2 8 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24(a) a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Doc ID 13329 Rev 10 25/31 Package and PC board thermal data VNQ5050AK-E Equation 1: pulse calculation formula Z THδ = R TH ⋅δ+Z THtp (1 – δ) where δ = tP/T Table 15. Thermal parameters Area/island (cm2) Footprint 2 8 0.4 - - R2=R8=R10=R12 (°C/W) 2 - - R3 (°C/W) 6 - - R4 (°C/W) 7.7 - - R5 (°C/W) 9 9 8 R6 (°C/W) 28 17 10 C1=C7=C9=C11 (W.s/°C) 0.001 - - C2=C8=C10=C12 (W.s/°C) 0.0022 - - C3 (W.s/°C) 0.025 - - C4 (W.s/°C) 0.75 - - C5 (W.s/°C) 1 4 9 C6 (W.s/°C) 2.2 5 17 R1=R7=R9=R11 (°C/W) 26/31 Doc ID 13329 Rev 10 VNQ5050AK-E Package and packing information 5 Package and packing information 5.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 PowerSSO-24™ mechanical data Table 16. PowerSSO-24™ mechanical data Millimeters Symbol Min. Typ. Max. A - - 2.45 A2 2.15 - 2.35 a1 0 - 0.10 b 0.33 - 0.51 c 0.23 - 0.32 D 10.10 - 10.50 E 7.4 - 7.6 e - 0.8 - e3 - 8.8 - G - - 0.1 G1 - - 0.06 H 10.1 - 10.5 h - - 0.4 k 0° - 8° L 0.55 - 0.85 N - - 10º X 4.1 - 4.7 Y 6.5 - 7.1 Doc ID 13329 Rev 10 27/31 Package and packing information VNQ5050AK-E Figure 32. PowerSSO-24™ package dimensions 28/31 Doc ID 13329 Rev 10 VNQ5050AK-E 5.3 Package and packing information Packing information Figure 33. PowerSSO-24 tube shipment (no suffix) C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.05) D1 (min) F (± 0.1) K (max) P1 (± 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets saled with cover tape. User direction of feed Doc ID 13329 Rev 10 29/31 Revision history 6 VNQ5050AK-E Revision history Table 17. 30/31 Document revision history Date Revision Changes 14-Sep-2004 1 Initial release. 12-Jan-2006 2 Major general update. 9-Mar-2007 3 Reformatted and restructured. Added contents, lists of tables and list of figures. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V). Added ECOPACK® packages information. Added new disclaimer. 22-Aug-2007 4 Figure 14: Input high level and Figure 15: Input hysteresis voltage corrected. 01-Oct-2007 5 Table 4: Absolute maximum ratings: changed EMAX value from 51 to 104 mJ. Table 8: Current sense (8V<VCC<16V): added dk1/k1, dk2/k2, dk3/k3, ΔtDSENSE2H. Added Figure 5: Delay response time between rising edge of output current and rising edge of current sense (CS enabled). Updated Figure 7: IOUT/ISENSE vs IOUT. Added Figure 8: Maximum current sense ratio drift vs load current. Table 12: Electrical transient requirements (part 1/3): added notes. Figure 31: Thermal fitting model of a double channel HSD in PowerSSO-24, added note. 04-Dec-2007 6 Updated Table 8: Current sense (8V<VCC<16V): – changed tDSENSE2H max value from 300 µs to 250µs. – added IOL parameter. 12-Feb-2008 7 Corrected typing error in Table 8: Current sense (8V<VCC<16V): changed IOL test condition from VIN = 0V to VIN = 5V. 14-May-2009 8 Table 16: PowerSSO-24™ mechanical data: – Updated a1 (max) from 0.075 to 0.10. 29-May-2009 9 Table 16: PowerSSO-24™ mechanical data: – Updated A (min) from 2.15 to - and A (max) from 2.47 to 2.45 – Updated A2 (max) from 2.40 to 2.35 – Updated k (min) from - to 0°, k (typ) from 5° to - and k (max) from - to 8° 22-Sep-2013 10 Updated Disclaimer. Doc ID 13329 Rev 10 VNQ5050AK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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