STMICROELECTRONICS VND5025LAK-E

VND5025LAK-E
Double channel high side driver with analog
current sense for automotive applications
Features
Max supply voltage
VCC
Operating voltage range
VCC 4.5 to 36V
41V
Max on-state resistance (per ch.)
RON
25mΩ
Current limitation (typ)
ILIMH
60A
Off state supply current
IS
2µA(1)
PowerSSO-24™
– Thermal shut down
– Reverse battery protection(a)
– Electrostatic discharge protection
1. Typical value with all loads connected
■
Features
– In-rush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
– Package: ECOPACK®
■ Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range
currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
■ Protection
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self-limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
Table 1.
Description
The VND5025LAK-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology, intended for driving resistive or
inductive loads with one side connected to
ground, and suitable for driving LEDs.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Order codes
Package
Tube
Tape and Reel
PowerSSO-24™
VND5025LAK-E
VND5025LAKTR-E
a. See Figure 26: Application schematic
March 2007
Rev 3
1/31
www.st.com
1
Contents
VND5025LAK-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
4
6
2/31
3.1.1
Solution 1: Resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2
Solution 2: Diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
µC I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 23
Package and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
PowerSSO-24™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VND5025LAK-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power section (8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise specified) . . . . . . . 8
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Current sense (8V < VCC < 16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VND5025LAK-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) and suggested connections for unused and N.C. pins . 5
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Delay response time between rising edge of ouput current and rising edge of current
sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IOUT/ISENSE vs IOUT (see Table 9 for details) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum turn off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-24™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb vs PCB copper area in open box free air condition (with one channel ON). . . . . . 24
PowerSSO-24™ thermal impedance junction to ambient single pulse
(with one channel ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Thermal fitting model of a double channel HSD in PowerSSO-24™(1) . . . . . . . . . . . . . . . 26
PowerSSO-24™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-24™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-24™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VND5025LAK-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
UNDERVOLTAGE
VCC
CLAMP
OUTPUT1
PwCLAMP 1
GND
CURRENT
SENSE1
DRIVER 1
ILIM 1
INPUT1
LOGIC
PwCLAMP 2
DRIVER 2
VDSLIM 1
PwrLIM 1
OUTPUT2
ILIM 2
OVERTEMP. 1
INPUT2
IOUT1
CURRENT
SENSE2
VDSLIM 2
K1
OVERTEMP. 2
IOUT2
K2
PwrLIM 2
CS_DIS
Table 2.
Pin functions
Name
VCC
OUTPUT1,2
GND
INPUT1,2
CURRENT SENSE1,2
CS_DIS
Figure 2.
Function
Battery connection
Power output
Ground connection; must be reverse battery protected by an external
diode/resistor network
Voltage controlled input pin with hysteresis, CMOS compatible; controls
output switch state
Analog current sense pin; delivers a current proportional to the load
current
Active high CMOS compatible pin to disable the current sense pin
Configuration diagram (top view) and suggested connections for unused
and N.C. pins
VCC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS.
VCC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
TAB = VCC
Connection / Pin
Floating
To Ground
Current Sense
N.C.
Output
Input
CS_DIS
N.R.
X
X
X
X
1kΩ resistor
X
N.R.
10kΩ resistor
10kΩ resistor
N.R. = Not recommended
5/31
Electrical characteristics
2
VND5025LAK-E
Electrical characteristics
Figure 3.
Current and voltage conventions
IS
VCC
ICSD
VCSD
CS_DIS
OUTPUT1
INPUT1
CURRENT
SENSE1
IIN2
IOUT2
VSENSE1
OUTPUT2
INPUT2
ISENSE2
VIN2
CURRENT
SENSE2
GND
VSENSE2
IGND
(*) VFn = VOUTn - VCC during reverse battery condition
6/31
VOUT1
ISENSE1
IIN1
VIN1
VF (*)
IOUT1
VOUT2
VCC
VND5025LAK-E
2.1
Electrical characteristics
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
VCC
DC supply voltage
41
-VCC
Reverse DC supply voltage
0.3
-IGND
DC reverse ground pin current
200
IOUT
DC output current
- IOUT
Reverse DC output current
IIN
ICSD
Unit
V
mA
Internally limited
A
24
DC input current
-1 to 10
DC current sense disable input current
-ICSENSE
DC reverse CS pin current
VCSENSE
Current sense maximum voltage
EMAX(1)
Maximum switching energy (single pulse)
(L = 0.3mH; RL = 0Ω; Vbat = 13.5V; Tjstart = 150°C;
IOUT = IlimL(Typ.) )
mA
200
VCC - 41 to +VCC
V
109
mJ
VESD
Electrostatic Discharge
(Human Body Model: R = 1.5kΩ; C = 100pF)
- Input
- Current sense
- CS_DIS
- Output
- VCC
4000
2000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Tj
Tstg
Junction operating temperature
-40 to 150
Storage temperature
-55 to 150
°C
1. See Section 3.4 for details.
2.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Rthj-case Thermal resistance junction-case (MAX) (with one channel ON)
Rthj-amb
Thermal resistance junction-ambient (MAX)
Max Value
Unit
1.35
°C/W
See Figure 29
7/31
Electrical characteristics
Table 5.
VND5025LAK-E
Power section (8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise
specified)
Symbol
Parameter
VCC
Operating supply
voltage
VUSD
VUSDhyst
RON
Vclamp
IS
IL(off)
VF
Test conditions
Min Typ Max Unit
13
36
Undervoltage shutdown
3.5
4.5
Undervoltage shutdown hysteresis
0.5
On state resistance
4.5
(1)
Clamp voltage
Supply current
IOUT = 3A; Tj = 25°C
25
IOUT = 3A; Tj = 150°C
50
IOUT = 3A; VCC = 5V; Tj = 25°C
35
IS = 20 mA
41
Off State; VCC = 13V; Tj = 25°C;
VIN = VOUT = VSENSE = VCSD = 0V
On State; VCC = 13V; VIN = 5V;
IOUT = 0A
Off state output
current(1)
Output - VCC diode
voltage(1)
VIN = VOUT = 0V; VCC = 13V; Tj = 25°C
0
VIN = VOUT = 0V; VCC = 13V; Tj = 125°C
0
V
mΩ
46
52
V
2(2)
5(2)
µA
3
6
mA
0.01
3
µA
-IOUT = 4A; Tj = 150°C
5
0.7
V
1. For each channel
2. PowerMOS leakage included
Table 6.
Symbol
Switching (VCC = 13V; Tj = 25°C)
Parameter
td(on)
Turn-on delay time
td(off)
Turn-off delay time
(dVOUT/dt)on Turn-on voltage slope
(dVOUT/dt)off Turn-off voltage slope
8/31
WON
Switching energy losses
during tWON
WOFF
Switching energy losses
during tWOFF
Test conditions
RL = 4.3Ω
(see Figure 8)
Min
Typ
Max
Unit
35
µs
50
(see Figure 21)
RL = 4.3Ω
V/µs
(see Figure 22)
0.45
RL = 4.3Ω
(see Figure 8)
mJ
0.35
VND5025LAK-E
Electrical characteristics
Table 7.
Symbol
Logic input
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
VCSD(hyst)
CS_DIS hysteresis voltage
Symbol
Unit
0.9
V
µA
2.1
V
10
µA
0.25
IIN = 1mA
5.5
7
V
-0.7
0.9
VCSD = 0.9V
1
µA
2.1
V
VCSD = 2.1V
10
µA
7
V
Max
Unit
0.25
ICSD = 1mA
5.5
-0.7
Protection and diagnostics(1)
Parameter
ILIML
Short circuit current
during thermal cycling
TTSD
Shutdown temperature
Test conditions
VCC = 13V
Min
Typ
43
60
85
5V < VCC < 36V
TR
Reset temperature
TRS
Thermal reset of STATUS
VON
Max
1
ICSD = -1mA
DC short circuit current
VDEMAG
Typ
VIN = 2.1V
CS_DIS clamp voltage
ILIMH
THYST
Min
IIN = -1mA
CS_DIS low level voltage
Table 8.
VIN = 0.9V
Input clamp voltage
VCSDL
VCSCL
Test conditions
A
VCC = 13V;
TR < Tj < TTSD
24
150
175
TRS + 1
TRS + 5
200
°C
135
Thermal hysteresis
(TTSD-TR)
7
Turn-off output voltage
clamp
IOUT = 2A;
VIN = 0;
L = 6mH
Output voltage drop
limitation
IOUT = 0.2A;
Tj = -40°C to +150°C
(see Figure 9)
VCC - 41 VCC - 46 VCC - 52
V
40
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
9/31
Electrical characteristics
Table 9.
Symbol
Current sense (8V < VCC < 16V)
Parameter
Test conditions
Min
Typ
Max Unit
KLED
IOUT/ISENSE
IOUT = 0.05A; VSENSE = 0.5V; VCSD = 0V;
1450 3300 5180
Tj = -40°C to 150°C
K0
IOUT/ISENSE
IOUT = 0.5A; VSENSE = 0.5V; VCSD = 0V;
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 2A; VSENSE = 4V;
VCSD = 0V;
Tj = -40°C
Tj = 25°C to 150°C
Current sense
ratio drift
IOUT = 2A; VSENSE = 4V;
VCSD = 0V;
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 3A; VSENSE = 4V;
VCSD = 0V;
Tj = -40°C
Tj = 25°C to150°C
Current sense
ratio drift
IOUT = 3A; VSENSE = 4V; VCSD = 0V;
Tj = -40°C to 150°C
IOUT/ISENSE
IOUT = 10A; VSENSE = 4V;
VCSD = 0V;
Tj = -40°C
Tj = 25°C to 150°C
Current sense
ratio drift
IOUT = 10A; VSENSE = 4V; VCSD = 0V;
Tj = -40°C to 150°C
K1
dK1/K1(1)
K2
dK2/K2(1)
K3
dK3/K3(1)
ISENSE0
10/31
VND5025LAK-E
Analog sense
leakage current
1720 3020 4360
1940 2810 3740
2230 2810 3390
-10
+10
%
2250 2790 3450
2400 2790 3180
-7
+7
%
2610 2760 2970
2650 2760 2870
-3
+3
%
IOUT = 0A; VSENSE = 0V;
VCSD = 5V; VIN = 0V; Tj = -40°C to 150°C
VCSD = 0V; VIN = 5V; Tj = -40°C to 150°C
0
0
1
2
µA
µA
IOUT = 2A; VSENSE = 0V;
VCSD = 5V; VIN = 5V; Tj = -40°C to 150°C
0
1
µA
IOUT = 3A; VCSD = 0V
5
VSENSE
Max analog
sense output
voltage
VSENSEH
Analog sense
output voltage in
VCC = 13V; RSENSE = 3.9kΩ
overtemperature
condition
9
ISENSEH
Analog sense
output current in
VCC = 13V; VSENSE = 5V
overtemperature
condition
8
V
mA
VND5025LAK-E
Electrical characteristics
Table 9.
Current sense (8V < VCC < 16V) (continued)
Symbol
Parameter
Test conditions
Min
Typ
Max Unit
tDSENSE1H
Delay response
VSENSE < 4V, 0.5 < IOUT < 10A
time from falling
= 90% of ISENSEMAX (see
I
edge of CS_DIS SENSE
Figure 4)
pin
50
100
tDSENSE1L
Delay response
VSENSE < 4V, 0.5 < IOUT < 10A
time from rising
= 10% of ISENSEMAX (see
I
edge of CS_DIS SENSE
Figure 4)
pin
5
20
tDSENSE2H
Delay response
time from rising
edge of INPUT
pin
70
300
Delay response
time between
rising edge of
∆tDSENSE2H
output current
and rising edge
of current sense
tDSENSE2L
Delay response
time from falling
edge of INPUT
pin
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 90% of ISENSEMAX (see
Figure 4)
µs
VSENSE < 4V,
ISENSE = 90% of ISENSEMAX,
IOUT = 90% of IOUTMAX, IOUTMAX = 3A
(see Figure 5)
VSENSE < 4V, 0.5 < IOUT < 10A
ISENSE = 10% of ISENSEMAX (see
Figure 4)
110
100
250
1. Parameter guaranteed by design; it is not tested.
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
tDSENSE1L
tDSENSE1H
tDSENSE2L
11/31
Electrical characteristics
Figure 5.
VND5025LAK-E
Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)
VIN
∆tDSENSE2H
t
IOUT
IOUTMAX
90% IOUTMAX
t
ISENSE
ISENSEMAX
90% ISENSEMAX
t
12/31
VND5025LAK-E
Figure 6.
Electrical characteristics
IOUT/ISENSE vs IOUT (see Table 9 for details)
IOUT/ISENSE
4000
M ax -40°C to 150°C
3500
M ax 25°C to 150°C
3000
Typ 25°C
M in 25°C to 150°C
2500
2000
M in -40°C to 150°C
1500
1000
500
0
2
3
4
5
6
8
10
IOUT (A)
13/31
Electrical characteristics
Figure 7.
VND5025LAK-E
Maximum current sense ratio drift vs load current
dK/K (%)
15
10
5
0
-5
-10
-15
2
3
4
5
6
7
8
9
10
IOUT (A)
Note: Parameter guaranteed by design; it is not tested.
Table 10.
Truth table
Conditions
Input
Output
Sense (VCSD = 0V)(1)
L
L
0
H
H
Nominal
Normal operation
L
Overtemperature
0
L
H
VSENSEH
L
Undervoltage
L
0
H
L
Short circuit to GND (RSC ≤ 10mΩ)
0
L
H
0 if Tj < TTSD
VSENSEH if Tj > TTSD
L
Short circuit to VCC
Negative output voltage clamp
0
H
H
L
< Nominal
L
0
1. If the VCSD is high, the SENSE output is at a high impedance; its potential depends on leakage currents
and external circuit.
14/31
VND5025LAK-E
Electrical characteristics
Figure 8.
Switching characteristics
tWoff
tWon
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
tf
10%
t
INPUT
td(on)
td(off)
t
Figure 9.
Output voltage drop limitation
VCC - VOUT
Tj = 150oC
Tj = 25oC
Tj = -40oC
Von
Von/Ron(T)
IOUT
15/31
Electrical characteristics
Table 11.
ISO 7637-2:
2004(E)
Test pulse
VND5025LAK-E
Electrical transient requirements
Test levels(1)
III
IV
1
-75V
-100V
2a
+37V
3a
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Min
Max
5000 pulses
0.5s
5s
2 ms, 10Ω
+50V
5000 pulses
0.2s
5s
50µs, 2Ω
-100V
-150V
1h
90ms
100ms
0.1µs, 50Ω
3b
+75V
+100V
1h
90ms
100ms
0.1µs, 50Ω
4
-6V
-7V
1 pulse
100ms, 0.01Ω
+65V
+87V
1 pulse
400ms, 2Ω
(2)
5b
ISO 7637-2:
2004E
Test pulse
III
VI
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
Class
Test level results
Contents
C
All functions of the device performed as designed after exposure to disturbance.
E
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
16/31
Delays and
Impedance
VND5025LAK-E
Electrical characteristics
Figure 10. Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
< Nominal
< Nominal
OVERLOAD OPERATION
TR
Tj
TTSD
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT
Current
limitation
Power
limitation
Thermal cycling
SHORTED LOAD
NORMAL LOAD
17/31
Electrical characteristics
VND5025LAK-E
Figure 11. Off state output current
Figure 12. High level input current
Iih(uA)
Iloff (uA)
0.5
5
0.45
4.5
Off State
Vcc=13V
Vin=Vout=0V
0.4
Vin=2.1V
4
3.5
0.35
0.3
3
0.25
2.5
0.2
2
0.15
1.5
0.1
1
0.05
0.5
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Tc (°C)
Figure 13. Input clamp voltage
Figure 14. Input high level
Vicl (V)
Vih (V)
7
4
6.75
3.5
Iin=1mA
6.5
3
6.25
2.5
6
2
5.75
1.5
5.5
1
5.25
0.5
5
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
75
Tc (°C)
Figure 15. Input low level
Figure 16. Input hysteresis voltage
Vil (V)
Vhyst (V)
2
1
1.8
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
-50
-25
0
25
50
75
Tc (°C)
18/31
50
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
VND5025LAK-E
Electrical characteristics
Figure 17. On state resistance vs Tcase
Figure 18. On state resistance vs VCC
Ron (mOhm)
Ron (mOhm)
100
80
90
70
Iout=3A
Vcc=13V
80
60
70
50
60
50
40
40
Tc=150°C
30
Tc= 125°C
20
Tc= 25°C
Tc= -40°C
30
20
10
10
0
0
-50
-25
0
25
50
75
100
125
150
175
0
5
10
15
Tc (°C)
20
25
30
35
40
125
150
175
150
175
Vcc (V)
Figure 19. Undervoltage shutdown
Figure 20. ILIMH vs Tcase
Vusd (V)
Ilimh (A)
16
100
90
14
Vcc=13V
80
12
70
10
60
50
8
40
6
30
4
20
2
10
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
Tc (°C)
Tc (°C)
Figure 21. Turn-on voltage slope
Figure 22. Turn-off voltage slope
(dVout/dt)on (V/ms)
(dVout/dt)off (V/ms)
1000
1000
900
900
Vcc=13V
Rl=4.3Ohm
800
Vcc=13V
Rl=4.3Ohm
800
700
700
600
600
500
500
400
400
300
300
200
200
100
100
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
19/31
Electrical characteristics
VND5025LAK-E
Figure 23. CS_DIS high level voltage
Vcsdh (V)
Vcsdl (V)
4
4
3.5
3.5
3
3
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Vcsdcl (V)
8
7.5
Icsd=1mA
7
6.5
6
5.5
5
4.5
4
-50
-25
0
25
50
75
Tc (°C)
-50
-25
0
25
50
75
Tc (°C)
Figure 25. CS_DIS clamp voltage
20/31
Figure 24. CS_DIS low level voltage
100
125
150
175
100
125
150
175
VND5025LAK-E
3
Application information
Application information
Figure 26. Application schematic
+5V
VCC
Rprot
CS_DIS
Dld
µC
Rprot
INPUT
OUTPUT
Rprot
CURRENT SENSE
GND
CEXT
RSENSE
VGND
RGND
DGND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1
Solution 1: Resistor in the ground line (RGND only)
This first solution can be used with any type of load.
The following formulas indicate how to dimension the RGND resistor:
1.
RGND ≤ 600mV / (IS(on)max)
2.
RGND ≥ (-VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC < 0 during reverse battery situations) is:
PD = (-VCC)2 / RGND
This resistor can be shared among several different HSDs. Please note that the value of this
resistor is calculated with formula (1), where IS(on)max becomes the sum of the maximum onstate currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground, the RGND
produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This
shift varies depending on how many devices are ON in the case of several high-side drivers
sharing the same RGND.
21/31
Application information
VND5025LAK-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor, then ST suggests to utilize the following Solution 2.
3.1.2
Solution 2: Diode (DGND) in the ground line
If the device drives an inductive load, insert a resistor (RGND = 1kΩ) in parallel to DGND.
This small signal diode can be safely shared among several different HSDs. Also in this
case, the presence of the ground network produces a shift (j600mV) in the input threshold
and in the status output values if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than the ones shown in the ISO 7637-2:2004E table.
3.3
µC I/Os protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins are pulled negative. ST suggests to insert an in-line resistor (Rprot) to
prevent the µC I/Os pins from latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak = -100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ
Recommended values: Rprot = 10kΩ, CEXT = 10nF
22/31
VND5025LAK-E
3.4
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn off current versus inductance (for each channel)
ILMAX (A)
100
A
B
C
10
1
0.1
1
10
100
L (mH)
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
23/31
Package and thermal data
VND5025LAK-E
4
Package and thermal data
4.1
PowerSSO-24™ thermal data
Figure 28. PowerSSO-24™ PC board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area = 77mm x 86mm, PCB
thickness = 1.6mm, Cu thickness = 70µm (front and back side), Copper areas: from minimum pad layout to 8cm2).
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (with one
channel ON)
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
PCB Cu heatsink area (cm^2)
24/31
8
10
VND5025LAK-E
Package and thermal data
Figure 30. PowerSSO-24™ thermal impedance junction to ambient single pulse
(with one channel ON)
ZTH (°C/W)
1000
100
Footprint
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Pulse calculation formula:
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = t p ⁄ T
25/31
Package and thermal data
VND5025LAK-E
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24™(1)
1. Values are given in Table 12
Table 12.
Thermal parameters
Area/Island (cm2)
26/31
Footprint
2
8
R1 (°C/W)
0.28
R2 (°C/W)
0.9
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
R7 (°C/W)
0.28
R8 (°C/W)
0.9
C1 (W.s/°C)
0.001
C2 (W.s/°C)
0.003
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
C7 (W.s/°C)
0.001
C8 (W.s/°C)
0.003
VND5025LAK-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of Second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
5.2
Package mechanical
Table 13.
PowerSSO-24™ mechanical data
Millimeters
Symbol
Min
Typ
Max
A
1.9
2.22
A2
1.9
2.15
a1
0
0.07
b
0.34
c
0.23
0.32
D
10.2
10.4
E
7.4
7.6
0.4
e
0.8
e3
8.8
0.46
G
0.1
G1
0.06
H
10.1
h
L
10.5
0.4
0.55
N
0.85
10°
X
3.9
4.3
Y
6.1
6.5
27/31
Package and packing information
Figure 32. PowerSSO-24™ package dimensions
28/31
VND5025LAK-E
VND5025LAK-E
5.3
Package and packing information
Packing information
Figure 33. PowerSSO-24™ tube shipment (no suffix)
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
C
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 34. PowerSSO-24™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (±0.1)
P
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
29/31
Revision history
6
VND5025LAK-E
Revision history
Table 14.
30/31
Document revision history
Date
Revision
Changes
16-Feb-2007
1
Initial release
23-Feb-2007
2
Table 9: Current sense (8V < VCC < 16V): Error in dK3/K3 current
sense ratio drift row corrected.
28-Mar-2007
3
Protection section updated to correct editing error.
VND5025LAK-E
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31/31