VN5012AK-E Single channel high side driver with analog current sense for automotive applications Datasheet − production data Features Max supply voltage VCC 41 V Operating voltage range VCC 4.5 to 36 V Max on-state resistance (per ch.) RON 12 mΩ Current limitation (typ) ILIMH 65 A IS 2 µA(1) Off-state supply current (typ) 1. Typical value with all loads connected ■ General features – Inrush current active management by power limitation – Very low stand-by current – 3.0 V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – In compliance with the 2002/95/EC european directive – Reverse battery protection – Electrostatic discharge protection Application ■ All types of resistive, inductive and capacitive loads Description ■ Diagnostic functions – Proportional load current sense – High current sense precision for wide range currents – Current sense disable – Thermal shutdown indication – Very low current sense leakage ■ Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of VCC – Thermal shutdown Table 1. PowerSSO-24 The VN5012AK-E is a monolithic device made using STMicroelectronics VIPower® M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Device summary Order codes Package PowerSSO-24 September 2013 This is information on a product in full production. Tube Tape and reel VN5012AK-E VN5012AKTR-E Doc ID 13240 Rev 9 1/30 www.st.com 1 Contents VN5012AK-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 4 6 2/30 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 22 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 5 GND Protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 PowerSSO-24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 13240 Rev 9 VN5012AK-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching (VCC = 13 V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8 V < VCC < 16 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 13240 Rev 9 3/30 List of figures VN5012AK-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. 4/30 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of output current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 24 Thermal fitting model of a single channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 24 PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Doc ID 13240 Rev 9 VN5012AK-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC VCC CLAMP UNDERVOLTAGE PwCLAMP DRIVER OUTPUT GND ILIM LOGIC VDSLIM PwrLIM INPUT OVERTEMP. IOUT K CURRENT SENSE CS_DIS Table 2. Pin function Name VCC OUTPUT GND INPUT CURRENT SENSE1,2 CS_DIS Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Analog current sense pin, delivers a current proportional to the load current. Active high CMOS compatible pin, to disable the current sense pin. Doc ID 13240 Rev 9 5/30 Block diagram and pin description Figure 2. VN5012AK-E Configuration diagram (top view) VCC GND NC NC INPUT NC CURRENT SENSE NC CS_DIS NC NC VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC NC NC OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT NC NC NC TAB = VCC Table 3. Suggested connections for unused and not connected pins Connection / Pin Current Sense N.C. Output Input CS_DIS Floating N.R.(1) X X X X To ground Through 1 KΩ resistor X N.R. Through 10 KΩ resistor Through 10 KΩ resistor 1. Not recommended. 6/30 Doc ID 13240 Rev 9 VN5012AK-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions IS VCC VF VCC IOUT ICSD OUTPUT CS_DIS VOUT VCSD IIN INPUT ISENSE CURRENT SENSE VSENSE VIN GND IGND Note: VF = VOUT - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V -VCC Reverse DC supply voltage 0.3 V -IGND DC reverse ground pin current 200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current -30 A DC input current -1 to 10 mA DC current sense disable input current -1 to 10 mA 200 mA VCC-41 +VCC V V IIN ICSD -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage Doc ID 13240 Rev 9 7/30 Electrical specifications Table 4. VN5012AK-E Absolute maximum ratings (continued) Symbol Value Unit EMAX Maximum switching energy (L = 1.25 mH; RL = 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; IOUT = IlimL(typ.)) 508 mJ VESD Electrostatic discharge (Human Body Model: R = 1.5 KΩ; C = 100 pF) – INPUT – CURRENT SENSE – CS_DIS – OUTPUT – VCC 4000 2000 4000 2000 4000 5000 5000 V V V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 °C Storage temperature -55 to 150 °C Tj Tstg 2.2 Parameter Thermal data Table 5. Thermal data Symbol Parameter Max value Unit 0.4 °C/W See Figure 29 °C/W Rthj-case Thermal resistance junction case (max) (with one channel on) Rthj-amb 2.3 Thermal resistance junction ambient (max) Electrical characteristics 8 V < VCC < 36 V; -40°C < Tj < 150°C, unless otherwise specified. Table 6. Power section Symbol Parameter VCC Operating supply voltage VUSD VUSDhyst RON Vclamp 8/30 Test conditions Min. Typ. Max. Unit 13 36 V Undervoltage shutdown 3.5 4.5 V Undervoltage shutdown hysteresis 0.5 On-state resistance(2) Clamp voltage 4.5 V IOUT = 5 A; Tj = 25 °C 12 mΩ IOUT = 5 A; Tj = 150 °C 24 mΩ IOUT = 5 A; VCC = 5 V; Tj = 25 °C 16 mΩ 52 V IS = 20 mA Doc ID 13240 Rev 9 41 46 VN5012AK-E Electrical specifications Table 6. Power section (continued) Symbol IS IL(off) VF Parameter Test conditions Supply current Off-state output current(2) Output - VCC diode voltage(2) Min. Typ. Max. Unit Off-state; VCC = 13 V; Tj = 25 °C; VIN = VOUT = VSENSE = VCSD = 0 V 2(1) 5(1) µA On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A 1.5 3 μΑ 0.01 3 µA 5 µA 0.7 V VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 °C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 °C 0 -IOUT = 8 A; Tj = 150 °C 1. PowerMOS leakage included. 2. For each channel. Table 7. Symbol Switching (VCC = 13 V; Tj = 25°C) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 2.6 Ω (see Figure 8) 30 µs td(off) Turn-off delay time RL = 2.6 Ω (see Figure 8) 55 µs dVOUT/dt(on) Turn-on voltage slope RL = 2.6 Ω See Figure 21 V/µs dVOUT/dt(off) Turn-off voltage slope RL = 2.6 Ω See Figure 22 V/µs WON Switching energy losses during twon RL = 2.6 Ω (see Figure 8) 1.2 mJ WOFF Switching energy losses during twoff RL = 2.6 Ω (see Figure 8) 0.7 mJ Table 8. Symbol Logic input Parameter VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL Test conditions VIN = 0.9 V CS_DIS low level voltage ICSDL Low level CS_DIS current VCSDH CS_DIS high level voltage ICSDH High level CS_DIS current Max. Unit 0.9 V 1 µA 2.1 V 10 0.25 7 -0.7 VCSD = 2.1 V Doc ID 13240 Rev 9 V V 0.9 VCSD = 0.9 V µA V 5.5 IIN = -1 mA VCSDL Typ. VIN = 2.1 V IIN = 1 mA Input clamp voltage Min. V 1 µA 2.1 V 10 µA 9/30 Electrical specifications Table 8. Symbol VN5012AK-E Logic input (continued) Parameter Test conditions Min. VCSD(hyst) CS_DIS hysteresis voltage VCSCL Table 9. Symbol CS_DIS clamp voltage Parameter V 5.5 7 -0.7 Test conditions IlimL Short circuit current during thermal cycling TTSD Shutdown temperature V V VCC = 13 V Min. Typ. Max. Unit 45 65 90 A 90 A 5 V < VCC < 36 V VCC = 13 V; TR < Tj < TTSD TR Reset temperature TRS Thermal reset of STATUS VON ICSD = 1 mA Unit Protections and diagnostics (1) DC Short circuit current VDEMAG Max. 0.25 ICSD = -1 mA IlimH THYST Typ. 24 150 175 TRS + 1 TRS + 5 A 200 °C 135 Thermal hysteresis (TTSD - TR) °C °C 7 °C Turn-off output voltage clamp IOUT = 2 A; VIN = 0 V; L = 6 mH VCC - 41 VCC - 46 VCC - 52 V Output voltage drop limitation IOUT = 0.5 A; Tj = -40 °C to 150 °C (see Figure 9) 25 mV 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 10. Symbol K0 K1 dK1/K1(1) K2 dK2/K2(1) 10/30 Current sense (8 V < VCC < 16 V) Parameter Test conditions Min. Typ. Max. Unit IOUT/ISENSE IOUT = 0.25 A; VSENSE = 0.5 V; VCSD = 0 V; Tj = -40 °C to 150 °C IOUT/ISENSE IOUT = 5 A; VSENSE = 0.5 V; VCSD = 0 V; 3590 4480 5370 Tj = -40 °C to 150 °C IOUT = 5 A; VSENSE = 0.5 V; VCSD = 0 V; 3790 4480 5170 Tj = 25 °C to 150 °C Current sense ratio drift IOUT = 5 A; VSENSE = 0.5 V; VCSD = 0 V; Tj = -40 °C to 150 °C IOUT/ISENSE IOUT = 10 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C IOUT = 10 A; VSENSE = 4 V; VCSD = 0 V; Tj = 25 °C to 150 °C Current sense ratio drift IOUT = 10 A; VSENSE = 4 V; VCSD = 0 V; TJ = -40 °C to 150 °C Doc ID 13240 Rev 9 3090 5080 7070 -8 +8 % 4080 4510 4980 4160 4510 4860 -5 +5 % VN5012AK-E Electrical specifications Table 10. Symbol K3 dK3/K3(1) ISENSE0 Current sense (8 V < VCC < 16 V) (continued) Parameter IOUT/ISENSE Current sense ratio drift Analog sense leakage current Test conditions IOUT = 25 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C IOUT = 25 A; VSENSE = 4 V; VCSD = 0 V; Tj = 25 °C to 150 °C Min. Typ. Max. Unit 4420 4600 4780 4460 4600 4740 IOUT = 25 A; VSENSE = 4 V; VCSD = 0 V; Tj = -40 °C to 150 °C -4 +4 % IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V; VIN = 0 V; Tj = -40 °C to 150 °C 0 1 µA IOUT = 0 A; VSENSE = 0 V; VCSD = 0 V; VIN = 5 V; Tj = -40 °C to 150 °C 0 2 µA IOUT = 2 A; VSENSE = 0 V; VCSD = 5 V; VIN = 5 V; Tj = -40 °C to 150 °C 0 1 µA 45 mA IOL Openload on-state current detection threshold VIN = 5 V; ISENSE = 5 µA 10 VSENSE Max analog sense output voltage IOUT = 15 A; VCSD = 0 V 5 Analog sense output voltage in over VSENSEH VCC = 13 V; RSENSE = 2.2 KΩ temperature condition ISENSEH Analog sense output current in over VCC = 13 V; VSENSE = 5 V temperature condition V 9 V 8 mA Delay response time VSENSE < 4 V; 1.5 A < IOUT < 25 A; tDSENSE1H from falling edge of ISENSE = 90 % of ISENSE max (see Figure 4) CS_DIS pin 50 100 µs Delay response time VSENSE < 4 V; 1.5 A < IOUT < 25 A; tDSENSE1L from rising edge of ISENSE = 10 % of ISENSE max (see Figure 4) CS_DIS pin 5 20 µs Delay response time VSENSE < 4 V; 1.5 A < IOUT < 25 A; tDSENSE2H from rising edge of ISENSE = 90 % of ISENSE max (see Figure 4) INPUT pin 270 400 µs 300 µs 250 µs Delay response time between rising edge ΔtDSENSE2H of output current and rising edge of current sense VSENSE < 4 V; ISENSE = 90 % of ISENSEMAX; IOUT = 90 % of IOUTMAX; IOUTMAX = 5 A (see Figure 5) Delay response time VSENSE < 4 V; 1.5 A < IOUT < 25 A; tDSENSE2L from falling edge of ISENSE = 10 % of ISENSE max INPUT pin (see Figure 4) 100 1. Parameter guaranteed by design, it is not tested. Doc ID 13240 Rev 9 11/30 Electrical specifications Figure 4. VN5012AK-E Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H Figure 5. tDSENSE1L tDSENSE1H tDSENSE2L Delay response time between rising edge of output current and rising edge of current sense (CS enabled) VIN ΔtDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t 12/30 Doc ID 13240 Rev 9 VN5012AK-E Electrical specifications Figure 6. IOUT/ISENSE vs IOUT ,287,6(16( PD[7M &WR& PD[7M &WR& W\SLFDOYDOXH PLQ7M &WR& PLQ7M &WR& ,287$ Figure 7. *$3*&)7 Maximum current sense ratio drift vs load current ELL Note: ,287$ *$3*&)7 Parameter guaranteed by design; it is not tested. Doc ID 13240 Rev 9 13/30 Electrical specifications Table 11. VN5012AK-E Truth table Input Output Sense (VCSD = 0 V)(1) Normal operation L H L H 0 Nominal Over temperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Short circuit to GND (Rsc ≤ 10 mΩ) L H H L L L 0 0 if Tj < TTSD VSENSEH if Tj > TTSD Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Conditions 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. Figure 8. Switching characteristics VOUT tWon tWoff 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% tr tf t INPUT td(on) td(off) t Figure 9. Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Von/Ron(T) 14/30 Doc ID 13240 Rev 9 Iout VN5012AK-E Electrical specifications Table 12. ISO 7637-2: 2004(E) Electrical transient requirements (part 1/3) Test levels(1) Number of pulses or test times Burst cycle/pulse repetition time Delays and impedance test pulse III IV 1 -75V -100V 5000 pulses 0.5 s 5s 2 ms, 10 Ω 2a +37V +50V 5000 pulses 0.2 s 5s 50 µs, 2 Ω 3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω 3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω 4 -6V -7V 1 pulse 100 ms, 0.01 Ω 5b(2) +65V +87V 1 pulse 400 ms, 2 Ω Table 13. Electrical transient requirements (part 2/3) Test level results(1) ISO 7637-2: 2004(E) test pulse III IV 1 C C 2 C C 3a C C 3b C C 4 C C 5(2) C C 1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Table 14. Electrical transient requirements (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the Doc ID 13240 Rev 9 15/30 Electrical specifications VN5012AK-E Figure 10. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TTSD TR TRS INPUT CS_DIS ILIMH ILIML LOAD CURRENT VSENSEH SENSE CURRENT thermal cycling current power limitation limitation SHORTED LOAD 16/30 Doc ID 13240 Rev 9 NORMAL LOAD VN5012AK-E Electrical specifications 2.4 Electrical characteristics curves Figure 11. Off-state output current Figure 12. High level input current Iih (uA) Iloff (uA) 0.3 5 4.5 Vin=2.1V 0.25 Off State Vcc=13V Vin=Vout=0V 0.2 4 3.5 3 0.15 2.5 2 0.1 1.5 1 0.05 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 50 75 100 125 150 175 100 125 150 175 Tc (°C) Figure 13. Input clamp voltage Figure 14. Input high level Vicl (V) Vih (V) 7 4 6.8 3.5 lin=1mA 6.6 3 6.4 2.5 6.2 6 2 5.8 1.5 5.6 1 5.4 0.5 5.2 5 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (°C) 50 75 Tc (°C) Figure 15. Input low level Figure 16. Input hysteresis voltage Vil (V) Vihyst (V) 2 1 1.8 0.9 1.6 0.8 1.4 0.7 1.2 0.6 1 0.5 0.8 0.4 0.6 0.3 0.4 0.2 0.2 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (°C) -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 13240 Rev 9 17/30 Electrical specifications VN5012AK-E Figure 17. On-state resistance vs Tcase Figure 18. On-state resistance vs VCC Ron (mOhm) Ron (mOhm) 18 20 17 18 Iout=5A Vcc=13V 16 Tc=150°C 16 15 Tc=125°C 14 14 13 12 12 Tc=25°C 10 11 8 10 9 Tc=-40°C 6 8 -50 -25 0 25 50 75 100 125 150 0 175 5 10 15 20 25 30 35 40 150 175 150 175 Vcc (V) Tc (°C) Figure 19. Undervoltage shutdown Figure 20. ILIMH vs Tcase Vusd (V) Ilimh (A) 16 100 90 14 Vcc=13V 80 12 70 10 60 50 8 40 6 30 4 20 2 10 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Figure 21. Turn-on voltage slope 75 100 125 Figure 22. Turn-off voltage slope (dVout/dt)on (V/ms) (dVout/dt)off (V/ms) 1000 1000 900 900 Vcc=13V RI=2.6Ohm 800 Vcc=13V RI=2.6Ohm 800 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 18/30 50 Tc (°C) Tc (°C) -50 -25 0 25 50 75 Tc (°C) Doc ID 13240 Rev 9 100 125 VN5012AK-E Electrical specifications Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage Vcsdcl (V) Vcsdh (V) 8 8 7 7.5 6 7 5 6.5 4 6 3 5.5 2 5 1 4.5 Icsd=1mA 4 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 25. CS_DIS low level voltage Vcsdl (V) 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) Doc ID 13240 Rev 9 19/30 Application information 3 VN5012AK-E Application information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld μC Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE VGND Cext RGND DGND 3.1 GND Protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to select the RGND resistor. 1. RGND ≤ 600 mV / (IS(on)max). 2. RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC < 0: during reverse battery situations) is: PD = (-VCC)2/RGND. This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 20/30 Doc ID 13240 Rev 9 VN5012AK-E 3.1.2 Application information Solution 2: a diode (DGND) in the ground line A resistor (RGND=1 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/O pins from latching-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Calculation example: For VCCpeak = -100 V and Ilatchup ≥ 20 mA; VOHμC ≥ 4.5 V 5 kΩ ≤ Rprot ≤ 180 kΩ. Recommended values: Rprot = 10 kΩ, CEXT = 10 nF. Doc ID 13240 Rev 9 21/30 Application information 3.4 VN5012AK-E Maximum demagnetization energy (VCC = 13.5V) Figure 27. Maximum turn-off current versus inductance " # ,$ $ /P+ *$3*&)7 A: Tjstart = 150°C single pulse B: Tjstart = 100°C repetitive pulse C: Tjstart = 125°C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: 22/30 Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 13240 Rev 9 VN5012AK-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 PowerSSO-24 thermal data Figure 28. PowerSSO-24 PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area = 77 mm x 86 mm,PCB thickness = 1.6mm, Cu thickness = 70 µm (front and back side), Copper areas: from minimum pad layout to 8 cm2). Figure 29. Rthj-amb vs PCB copper area in open box free air condition RTHj_amb(°C/W) 55 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) Doc ID 13240 Rev 9 23/30 Package and PCB thermal data VN5012AK-E Figure 30. Rthj-amb vs PCB copper area in open box free air condition =7+&: )RRWSULQW )RRWSULQ FP FP 7LPHV *$3*&)7 Equation 1: pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-24 1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 24/30 Doc ID 13240 Rev 9 VN5012AK-E Package and PCB thermal data Table 15. Thermal parameter Area/island (cm2) Footprint R1 (°C/W) 0.1 R2 (°C/W) 0.3 R3 (°C/W) 6 R4 (°C/W) 7.7 R5 (°C/W) 2 8 9 9 8 R6 (°C/W) 28 17 10 C1 (W.s/°C) 0.0025 C2 (W.s/°C) 0.0024 C3 (W.s/°C) 0.025 C4 (W.s/°C) 0.75 C5 (W.s/°C) 1 4 9 C6 (W.s/°C) 2.2 5 17 Doc ID 13240 Rev 9 25/30 Package and packing information VN5012AK-E 5 Package and packing information 5.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 PowerSSO-24 package mechanical data Figure 32. PowerSSO-24 package dimensions 26/30 Doc ID 13240 Rev 9 VN5012AK-E Package and packing information Table 16. PowerSSO-24 mechanical data Millimeters Symbol Min. Typ. Max. A - - 2.45 A2 2.15 - 2.35 a1 0 - 0.1 b 0.33 - 0.51 c 0.23 - 0.32 D 10.10 - 10.50 E 7.4 - 7.6 e - 0.8 - e3 - 8.8 - G - - 0.1 G1 - - 0.06 H 10.1 - 10.5 h - - 0.4 L 0.55 - 0.85 N - - 10deg X 4.1 - 4.7 Y 6.5 - 7.1 Doc ID 13240 Rev 9 27/30 Package and packing information 5.3 VN5012AK-E PowerSSO-24 packing information Figure 33. PowerSSO-24 tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) C B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) 1000 1000 330 1.5 13 20.2 24.4 100 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.05) D1 (min) F (± 0.1) K (max) P1 (± 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 All dimensions are in mm. End Start Top cover tape No components Components 500mm min Empty components pockets saled with cover tape. User direction of feed 28/30 Doc ID 13240 Rev 9 No components 500mm min VN5012AK-E 6 Revision history Revision history Table 17. Document revision history Date Revision 24-Jan-2006 1 Initial release. 13-Feb-2007 2 Document reformatted and restructured. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V). 3 Document reformatted and restructured. Added lists of tables and figures. Added ECOPACK® packages information. Table 4: Absolute maximum ratings: changed EMAX value from 283 to 508 mJ. Table 10: Current sense (8 V < VCC < 16 V): added dk1/k1, dk2/k2, dk3/k3, ΔtDSENSE2H parameters. Added Figure 5: Delay response time between rising edge of output current and rising edge of current sense (CS enabled). Updated Figure 6: IOUT/ISENSE vs IOUT. Added Figure 7: Maximum current sense ratio drift vs load current. Table : - Updated test level values III and IV for test pulse 5b and notes. 13-Dec-2007 4 Updated Table 10: Current sense (8 V < VCC < 16 V): – changed dk1/k1 values from ± 7 to ± 8 % – changed dk2/k2 values from ± 3 to ± 5 % – changed dk3/k3 values from ± 2 to ± 4 % – changed tDSENSE2H max value from 600 µs to 400 µs – changed ΔtDSENSE2H max value from 250 µs to 300 µs – added IOL parameter. Updated Figure 7: Maximum current sense ratio drift vs load current with new dk/k values. 12-Feb-2008 5 Corrected typing error in Table 10: Current sense (8 V < VCC < 16 V): changed IOL test condition from VIN = 0V to VIN = 5V. 01-Aug-2008 6 Updated Table 16: PowerSSO-24 mechanical data: changed a1 max. value from 0.075 mm to 0.1 mm. 01-Jun-2009 7 Updated Table 16: PowerSSO-24 mechanical data: – Changed A (min) value from 2.15 mm to - and A (max) from 2.47 mm to 2.45 mm – Changed A2 (max) from 2.40 mm to 2.35 mm 18-Oct-2012 8 Updated Description 23-Sep-2013 9 Updated Disclaimer. 03-Oct-2007 Changes Doc ID 13240 Rev 9 29/30 VN5012AK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 30/30 Doc ID 13240 Rev 9