STMICROELECTRONICS VND5160J-E

VND5160J-E
Double channel high side driver for automotive applications
Features
Max supply voltage
VCC
41V
Operating voltage range
VCC
4.5 to 36V
Max on-state resistance
RON
160 mΩ
Current limitation (typ)
ILIMH
5A
Off state supply current (typ)
IS
PowerSSO-12
– Electrostatic discharge protection
(1)
2 µA
1. Typical value with all loads connected.
Application
■
■
■
■
General
– Inrush current active management by
power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
European directive
Description
The VND5160J-E is a monolithic device made
using STMicroelectronics VIPower M0-5
technology. It is intended for driving resistive or
inductive loads with one side connected to
ground. Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table).
Diagnostic functions
– Open drain status output
– On state open load detection
– Off state open load detection
– Thermal shutdown indication
Protection
– Undervoltage shut-down
– Overvoltage clamp
– Output stuck to Vcc detection
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of VCC
– Thermal shut down
– Reverse battery protection (see Figure 28)
Table 1.
All types of resistive, inductive and capacitive
loads
The device detects open load condition in both
ON and OFF states, when STAT_DIS is left open
or driven low. Output shorted to VCC is detected in
the OFF state.
When STAT_DIS is driven high, the STATUS pin is
in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long duration
overload, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears.
Device summary
Order codes
Package
PowerSSO-12
December 2007
Part number (Tube)
Part number (Tape & Reel)
VND5160J-E
VND5160JTR-E
Rev 5
1/31
www.st.com
31
Contents
VND5160J-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
4
6
2/31
3.1.1
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 20
3.1.2
Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . 21
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
5
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VND5160J-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Status pin (VSD=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/31
List of figures
VND5160J-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Openload On state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Openload Off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn - On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Turn - Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Maximum turn Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24
PowerSSO-12™ Thermal impedance junction ambient single pulse (one channel ON) . . 25
Thermal fitting model of a double channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VND5160J-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
VCC
OUTPUT1
VCC
CLAMP
GND
UNDERVOLTAGE
INPUT1
CLAMP 1
STATUS1
DRIVER 1
STAT_DIS
LOGIC
INPUT2
CLAMP 2
DRIVER 2
ILIM 1
PWRLIM1
ILIM 2
VDSLIM 1
VDSLIM 2
STATUS2
OPENLOAD ON 1
OPENLOAD ON 2
OPENLOAD OFF 1
OPENLOAD OFF 2
OVERTEMP. 1
OVERTEMP. 2
OUTPUT2
PWRLIM 2
Table 2.
Pin functions
Name
VCC
OUTPUTn
GND
INPUTn
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/
resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
STATUSn
Open Drain digital diagnostic pin.
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin.
5/31
Block diagram and pin description
Figure 2.
VND5160J-E
Configuration diagram (top view)
TAB = Vcc
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
Table 3.
12
11
10
9
8
7
Vcc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
Vcc
Suggested connections for unused and N.C. pins
Connection / Pin
STATUS
N.C.
OUTPUT
INPUT
STAT_DIS
Floating
X
X
X
X
X
To ground
N.R.(1)
X
N.R.
Through 10kΩ
resistor
Through 10kΩ
resistor
1. Not recommended.
6/31
1
2
3
4
5
6
VND5160J-E
2
Electrical specifications
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
IOUTn
ISD
STAT_DIS
VSD
VFn VCC
IINn
OUTPUTn
STATUSn
INPUTn
VINn
ISTATn
VOUTn
VSTATn
GND
IGND
Note:
VFn = VOUTn - VCCn during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in this section for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
0.3
V
-IGND
DC reverse ground pin current
IOUT
DC output current
-IOUT
Reverse DC output current
IIN
DC input current
ISTAT
DC status current
ISTAT_DIS DC status disable current
EMAX
Maximum switching energy
(L=12mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C;
IOUT = IlimL(Typ.) )
200
mA
Internally limited
A
6
A
+10 / -1
mA
+10 / -1
mA
+10 / -1
mA
33
mJ
7/31
Electrical specifications
Table 4.
Absolute maximum ratings (continued)
Symbol
Value
Unit
VESD
Electrostatic discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– INPUT
– STATUS
– STAT_DIS
– OUTPUT
– VCC
4000
4000
4000
5000
5000
V
V
V
V
V
VESD
Charge device model (CDM-AEC-Q100-011)
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
Tj
Tstg
2.2
VND5160J-E
Parameter
Thermal data
Table 5.
Symbol
Thermal data
Parameter
Rthj-case Thermal resistance junction-case (max.) (with one channel ON)
Rthj-amb
8/31
Thermal resistance junction-ambient
Max value
Unit
8
°C/W
See Figure 32
°C/W
VND5160J-E
2.3
Electrical specifications
Electrical characteristics
Values specified in this section are for 8V<VCC<36V; -40°C<Tj<150°C, unless otherwise
stated.
.
Table 6.
Power section
Symbol
Parameter
VCC
Operating supply voltage
VUSD
VUSDhyst
RON
Vclamp
IS
IL(off1)
Min. Typ. Max. Unit
13
36
V
Undervoltage shutdown
3.5
4.5
V
Undervoltage Shut-down
hysteresis
0.5
On state
resistance(2)
4.5
IOUT= 1A; Tj= 25°C
IOUT= 1A; Tj= 150°C
IOUT= 1A; VCC= 5V; Tj= 25°C
Clamp voltage
IS= 20mA
Supply current
Off State; VCC=13V; VIN=VOUT=0
Tj= 25°C;
On State; VCC=13V; VIN=5V;
IOUT= 0A
Off state output
current(2)
41
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
VIN=0V; VOUT=4V
IL(off2)
VF
Test conditions
Output - VCC diode
voltage(2)
0
0
V
160
320
210
mΩ
mΩ
mΩ
46
52
V
2(1)
3
5(1)
6
µA
mA
0.01
3
5
µA
-75
0
-IOUT=0.6A; Tj=150°C
0.7
V
1. PowerMOS leakage included.
2. For each channel.
Table 7.
Symbol
Switching (VCC = 13V; Tj = 25°C)
Parameter
Test conditions
Min. Typ. Max. Unit
td(on)
Turn-On delay time
RL=13Ω (see Figure 6)
10
µs
td(off)
Turn-Off delay time
RL=13Ω (see Figure 6)
15
µs
dVOUT/dt(on) Turn-On voltage slope
RL=13Ω
See Figure 21
V/ µs
dVOUT/dt(off) Turn-Off voltage slope
RL=13Ω
See Figure 22
V/ µs
WON
Switching energy losses during twon RL=13Ω (see Figure 6)
0.07
mJ
WOFF
Switching energy losses during twoff RL=13Ω (see Figure 6)
0.04
mJ
9/31
Electrical specifications
Table 8.
Symbol
VND5160J-E
Status pin (VSD=0)
Parameter
Test conditions
Min. Typ. Max. Unit
VSTAT
Status low output voltage
ISTAT= 1.6 mA, VSD=0V
0.5
V
ILSTAT
Status leakage current
Normal operation or VSD=5V,
VSTAT= 5V
10
µA
CSTAT
Status pin input capacitance
Normal operation or VSD=5V,
VSTAT= 5V
100
pF
VSCL
Status clamp voltage
ISTAT= 1mA
ISTAT= - 1mA
7
V
V
Table 9.
Symbol
Parameter
Test conditions
DC short circuit current
VCC= 13V
5V<VCC<36V
IlimL
Short circuit current during
thermal cycling
VCC= 13V TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of STATUS
Min.
Typ.
Max.
Unit
3.5
5
7.5
7.5
A
A
2
150
175
A
200
TRS + 1 TRS + 5
Thermal hysteresis (TTSD-TR)
°C
7
Status delay in overload
conditions
Tj>TTSD
VDEMAG
Turn-Off output voltage
clamp
IOUT=1A; VIN=0; L=20mH
Output voltage drop
limitation
IOUT= 0.03A;
Tj= -40°C...+150°C
(see Figure 5)
°C
20
µs
VCC-41 VCC-46 VCC-52
V
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
10/31
°C
°C
135
tSDL
VON
-0.7
Protection(1)
IlimH
THYST
5.5
VND5160J-E
Electrical specifications
Table 10.
Openload detection
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
10
See
Figure 19
40
mA
200
µs
IOL
Openload On state
detection threshold
VIN = 5V, 8V<VCC<18V
tDOL(on)
Openload On state
detection delay
IOUT = 0A, VCC=13V
(see Figure 4)
tPOL
Delay between INPUT falling
edge and STATUS rising
IOUT = 0A (see Figure 4)
edge in Openload condition
VOL
Openload Off state voltage
detection threshold
VIN = 0V, 8V<VCC<16V
tDSTKON
Output short circuit to Vcc
detection delay at turn Off
See Figure 4
Table 11.
Symbol
500
1000
µs
2
See
Figure 20
4
V
tPOL
µs
180
Logic input
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VSDL
STAT_DIS low level voltage
ISDL
Low level STAT_DIS current
VSDH
STAT_DIS high level voltage
ISDH
High level STAT_DIS current
Test conditions
STAT_DIS clamp voltage
Min.
Typ. Max. Unit
0.9
VIN= 0.9V
µA
2.1
V
10
0.25
IIN= 1mA
IIN= -1mA
VCSD= 0.9V
µA
V
5.5
7
V
V
0.9
V
-0.7
1
µA
2.1
V
VCSD= 2.1V
10
0.25
ISD= 1mA
ISD= -1mA
V
1
VIN= 2.1V
VSD(hyst) STAT_DIS hysteresis voltage
VSDCL
200
µA
V
5.5
7
-0.7
V
V
11/31
Electrical specifications
Figure 4.
VND5160J-E
Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
OPEN LOAD STATUS TIMING (with external pull-up)
IOUT < IOL
VIN
VOUT < VOL
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OUTPUT STUCK TO Vcc
OVER TEMP STATUS TIMING
Tj > TTSD
IOUT > IOL
VIN
VOUT > VOL
VIN
VSTAT
VSTAT
tDOL(on)
Figure 5.
tSDL
tDSTKON
Output voltage drop limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
12/31
Iout
tSDL
VND5160J-E
Electrical specifications
Table 12.
Truth table
Conditions
INPUTn
OUTPUTn
STATUSn (VSD=0V)(1)
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output Voltage > VOL
L
H
H
H
L(2)
H
Output Current < IOL
L
H
L
H
H(3)
L
1. If the VSD is high, the STATUS pin is in a high impedance.
2. The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
3. The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Figure 6.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
tr
10%
tf
t
INPUT
td(on)
td(off)
t
13/31
Electrical specifications
Table 13.
ISO 7637-2:
2004(E)
VND5160J-E
Electrical transient requirements
Test levels(1)
test pulse
III
IV
Number of
pulses or
test times
1
-75V
-100V
5000 pulses
0.5 s
5s
2 ms, 10 Ω
2a
+37V
+50V
5000 pulses
0.2 s
5s
50 µs, 2 Ω
3a
-100V
-150V
1h
90 ms
100 ms
0.1 µs, 50 Ω
3b
+75V
+100V
1h
90 ms
100 ms
0.1 µs, 50 Ω
4
-6V
-7V
1 pulse
100 ms, 0.01 Ω
5b(2)
+65V
+87V
1 pulse
400 ms, 2 Ω
Burst cycle/pulse
repetition time
Delays and
impedance
Test level results(1)
ISO 7637-2:
2004(E)
test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
14/31
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
VND5160J-E
Electrical specifications
Figure 7.
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
STAT_DIS
LOAD CURRENT
undefined
STATUS
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
VOL
VOUT>VOL
STATUS
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
IOUT<IOL
tPOL
LOAD CURRENT
STATUS
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
IOUT>IOL
LOAD VOLTAGE
VOUT>VOL
VOL
STATUS
tDSTKON
OVERLOAD OPERATION
Tj
TR TTSD
TRS
INPUT
STAT_DIS
ILIMH
ILIML
LOAD CURRENT
STATUS
current power
limitation limitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
15/31
Electrical specifications
VND5160J-E
2.4
Electrical characteristics curves
Figure 8.
Off state output current
Figure 9.
Iloff1 (uA)
Input clamp voltage
Vicl (V)
8
0.25
7.75
Off state
Vcc=13V
Vin=Vout=0V
0.2
Iin=1mA
7.5
7.25
0.15
7
6.75
0.1
6.5
0.05
6.25
0
6
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C )
Figure 10. High level input current
Figure 11. Input high level
Iih (uA)
Vih (V)
5
4
4.5
3.5
Vin=2.1V
4
3
3.5
2.5
3
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C )
75
Tc (°C )
Figure 12. Input low level
Figure 13. Input hysteresis voltage
Vil (V)
Vihyst (V)
4
2
3.5
1.75
3
1.5
2.5
1.25
2
1
1.5
0.75
1
0.5
0.5
0.25
0
0
-50
-25
0
25
50
75
Tc (°C )
16/31
50
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
100
125
VND5160J-E
Electrical specifications
Figure 14. Status low output voltage
Figure 15. Status leakage current
Ilstat (uA)
Vstat (V)
0.08
0.9
0.8
0.072
Istat=1.6mA
Vstat=5V
0.7
0.064
0.6
0.056
0.5
0.4
0.048
0.3
0.04
0.2
0.032
0.1
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 16. Status clamp voltage
Figure 17. On state resistance vs Tcase
Ron (mOhm)
Vscl (V)
300
9
270
8.5
Istat=1mA
8
Iout=1A
Vcc=13V
240
7.5
210
7
180
6.5
150
6
120
5.5
90
5
60
4.5
30
0
4
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C )
Tc (°C )
Figure 18. On state resistance vs VCC
Figure 19. Openload On state detection
threshold
Ron (mOhm)
Iol (mA)
300
100
275
90
Tc=150°C
250
225
Vin=5V
80
Tc=125°C
70
200
60
175
50
150
Tc=25°C
40
125
30
Tc=-40°C
100
20
75
10
50
0
0
5
10
15
20
Vcc (V)
25
30
35
40
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
17/31
Electrical specifications
VND5160J-E
Figure 20. Openload Off state voltage
detection threshold
Figure 21. Turn - On voltage slope
Vol (V)
dVout/dt(on) (V/ms)
5
1000
4.5
900
Vin=0V
4
Vcc=13V
Ri=6.5Ohm
800
3.5
700
3
600
2.5
500
2
400
1.5
300
1
200
0.5
100
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Tc (°C )
Ilimh (A)
1000
10
900
9
800
8
700
7
Vcc=13V
Ri=13Ohm
5
400
4
300
3
200
2
100
1
0
0
0
25
125
150
175
Vcc=13V
6
500
-25
100
Figure 23. ILIM vs Tcase
dVout/dt(off) (V/ms)
-50
75
Tc (°C )
Figure 22. Turn - Off voltage slope
600
50
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
150
175
Tc (°C )
Tc (°C )
Figure 24. Undervoltage shutdown
Figure 25. STAT_DIS clamp voltage
Vusd (V)
Vsdcl (V)
14
14
12
12
10
10
8
8
6
6
4
4
2
2
Isd=1mA
0
0
-50
-25
0
25
50
75
Tc (°C )
18/31
100
125
150
175
-50
-25
0
25
50
75
Tc (°C )
100
125
VND5160J-E
Electrical specifications
Figure 26. High level STAT_DIS voltage
Figure 27. Low level STAT_DIS voltage
Vsdh (V)
Vsdl (V)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-50
-25
0
25
50
75
Tc (°C )
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C )
19/31
Application information
3
VND5160J-E
Application information
Figure 28. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUT
Rprot
STATUS
µC
OUTPUT
GND
VGND
RGND
DGND
Note:
Channels 2, has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
20/31
VND5160J-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2: a diode (DGND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈ 600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage transient suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤Rprot ≤(VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤Rprot ≤180kΩ.
Recommended Rprot values is 10kΩ.
3.4
Open load detection in Off state
Off state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2.
no misdetection when load is disconnected: in this case the Vout has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
21/31
Application information
VND5160J-E
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical characteristics
section.
Figure 29. Open load detection in Off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
R
STATUS
VOL
GROUND
22/31
RL
VND5160J-E
3.5
Application information
Maximum demagnetization energy (VCC = 13.5V)
Figure 30. Maximum turn Off current versus inductance (for each channel)
10
A
B
C
I (A)
1
0,1
0,1
1
L (mH)
10
100
A: Tjstart = 150°C single pulse
B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves A and B.
23/31
Package and PCB thermal data
VND5160J-E
4
Package and PCB thermal data
4.1
PowerSSO-12™ thermal data
Figure 31. PowerSSO-12™ PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).
Figure 32. Rthj-amb vs. PCB copper area in open box free air condition (one channel
ON)
RTHj_amb(°C/W)
65
60
55
50
45
40
35
30
0
2
4
6
PCB Cu heatsink area (cm^2)
24/31
8
10
VND5160J-E
Package and PCB thermal data
Figure 33. PowerSSO-12™ Thermal impedance junction ambient single pulse (one
channel ON)
ZTH (°C/W)
100
Footprint
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time (s)
10
100
1000
Pulse calculation formula
Z
THδ
= R
TH
⋅ δ+Z
THtp
( 1 – δ)
where δ = tP/T
Figure 34. Thermal fitting model of a double channel HSD in PowerSSO-12™(a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PCB thermal data
Table 14.
26/31
VND5160J-E
Thermal parameters
Area/island (cm2)
Footprint
R1=R7 (°C/W)
1.2
R2=R8 (°C/W)
6
R3 (°C/W)
7
R4 (°C/W)
2
8
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1=C7 (W.s/°C)
0.0008
C2=C8 (W.s/°C)
0.0016
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
VND5160J-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™ package information
Figure 35. PowerSSO-12™ package dimensions
27/31
Package and packing information
Table 15.
VND5160J-E
PowerSSO-12™ mechanical data
Millimeters
Symbol
Min.
Max.
A
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0°
8°
X
1.900
2.500
Y
3.600
4.200
ddd
28/31
Typ.
0.100
VND5160J-E
5.3
Package and packing information
Packing information
Figure 36. PowerSSO-12™ tube shipment (no suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 37. PowerSSO-12™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
29/31
Revision history
6
VND5160J-E
Revision history
Table 16.
Document revision history
Date
Revision
7-Jan-2004
1
Initial release.
3-Feb-2006
2
Major series of updates incorporated.
3
Reformatted.
Added list of tables and list of figures.
Added Section 3.5: Maximum demagnetization energy
(VCC = 13.5V).
Added new disclaimer.
4
Updated Table 4: Absolute maximum ratings: EMAX entries.
Updated Table 13: Electrical transient requirements :Test level
values III and IV for test pulse 5b and notes.
Figure 34: Thermal fitting model of a double channel HSD in
PowerSSO-12™ added note.
5
Updated Section 4.1: PowerSSO-12™ thermal data:
– Changed Figure 32: Rthj-amb vs. PCB copper area in open
box free air condition (one channel ON).
– Changed Figure 33: PowerSSO-12™ Thermal impedance
junction ambient single pulse (one channel ON).
– Updated Table 14: Thermal parameters:
R1 and R7 values changed from 1.2 to 0.1 °C/W.
R2 = R8 values changed from 6 to 0.2 °C/W.
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10/10/9 to 8/8/7 °C/W.
C1=C7 values changed from 0.0008 to 0.0001 °C/W.
C2=C8 values changed from 0.0016 to 0.002 °C/W.
20-Mar-2007
01-Jun-2007
17-Dec-2007
30/31
Changes
VND5160J-E
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31/31