PRELIMINARY DATA SHEET For information only TS4405P - Single P-Channel 1.8V Specified MicroSURF™ General Description Taiwan Semiconductor’s new low cost, state of the art MicroSURF™ lateral MOSFET process technology in chipscale bondwireless packaging minimizes PCB space and RDS(ON) plus provides an ultralow Qg X RDS(ON) figure of merit. MicroSURF™ for Load Switching Features and PA Switch • -4.9A, -12V RDS(ON) = 50mΩ at -4.5 Volts • -4.4A, -12V RDS(ON) = 70mΩ at -2.5 Volts • -4.0A, -12V Patent Pending RDS(ON) = 90mΩ at -1.8 Volts • Low profile package: less than 0.8mm height when mounted on PCB. • Occupies only 1.21 mm2 of PCB area. S S D G Less than 30% of the area of a SC-70. • Excellent thermal characteristics. • Lead free solder bumps available. Bump Side View Absolute Maximum Ratings TA=25°C unless otherwise noted Symbol Parameter VDSS VGSS ID PD TJ, TSTG Drain-Source Voltage Gate-Source Voltage Drain Current – Continuous – Pulsed Power Dissipation (Steady State) Operating and Storage Junction Temperature Range Ratings Units -12 +8 -4.9 -10 1.5 -55 to +150 V V A W ºC Thermal Characteristics RθJA RθJR RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Ball Thermal Resistance, Junction-to-Case 85 20 1.8 1 °C/W 6/8/03 Rev0 PRELIMINARY DATA SHEET Electrical Characteristics V(BD)SS IDSS IGSS VGS(t h) rDS(o n) Parameter Test Condition Min Typ Max Units Drain-Source Breakdow n Voltage VGS =0V, ID=-250µA -11 V Zero Gate Voltage Drain Current VDS =-12V, VGS =0V -1 µA Zero Gate Voltage Drain Current VDS =-12V, VGS =0V, T=70°C -5 µA ±100 nA Gate-Body Leakage Gate Threshold Voltage VGS =±8V, VDS =0V VDS =VGS , ID=-250µA -0,58 V Drain-Source On-State Resistance VGS =-4.5V, ID=-1A 50 mΩ Drain-Source On-State Resistance VGS =-2.5V, ID=-1A 70 mΩ Drain-Source On-State Resistance VGS =-1.8V, ID=-1A 90 mΩ Cis s Input Capacitance VDS =-12V, VG=0V, F=1MHZ 300 pF Co s s Output Capacitance VDS =-12V, VG=0V, F=1MHZ 200 pF Crs s Reverse Transfer Capacitance VDS =-12V, VG=0V, F=1MHZ 80 pF Qg Total Gate Charge VGS =-4.5V, ID=-4A, VDS =-8V 10 nC Qg s Gate Source-Charge VGS =-4.5V, ID=-4A, VDS =-8V 2 nC Qg d Gate Drain-Charge VGS =-4.5V, ID=-4A, VDS =-8V 1 nC VSD Diode Forw ard Voltage 0.7 V IS =-4A, VGS =0V 2 TS4405P Symbol TA=25°C unless otherwise specified 6/8/03 Rev0 PRELIMINARY DATA SHEET Dimensional Outline and Pad Layout TS4405P Ø 0.25mm Solder Mask Ø ~ 0.35mm S S 0.50mm G SILICON D 0.27mm 0.50mm 0.80mm MAX D = Drain Pad S = Source Pad G = Gate Pad LAND PATTERN RECOMMENDATION 1.10mm 0.30mm 1.10mm 0.50mm 44XXX MARK ON BACKSIDE OF DIE Bump Ø 0.37mm 0.50mm 0.30mm XXX = Date/Lot Traceability Code Bumps are Eutectic solder 63/37 Sn/Pb 3 6/8/03 Rev0