TSC TS8405P

PRELIMINARY DATA SHEET
For information only
TS8405P - Single P-Channel 1.8V Specified MicroSURF™
General Description
Taiwan Semiconductor’s new low cost,
state of the art MicroSURF™ lateral
MOSFET process technology in chipscale
bondwireless packaging minimizes PCB
space and RDS(ON) plus provides an ultralow Qg X RDS(ON) figure of merit.
MicroSURF™ for Load Switching
Features
and PA Switch
• -4.9A, -12V RDS(ON) = 50mΩ at -4.5 Volts
• -4.4A, -12V RDS(ON) = 70mΩ at -2.5 Volts
• -4.0A, -12V
Patent Pending
RDS(ON) = 90mΩ at -1.8 Volts
• Low profile package: less than 0.8mm height
when mounted on PCB.
D
D
S
G
• Occupies only 2.25 mm2 of PCB area.
Less than 25% of the area of a SSOT-6.
• Excellent thermal characteristics.
• Lead free solder bumps available.
Bump Side View
Absolute Maximum Ratings
TA=25°C unless otherwise noted
Symbol Parameter
VDSS
VGSS
ID
PD
TJ, TSTG
Drain-Source Voltage
Gate-Source Voltage
Drain Current
– Continuous
– Pulsed
Power Dissipation (Steady State)
Operating and Storage Junction Temperature Range
Ratings
Units
-12
+8
-4.9
-10
1.5
-55 to +150
V
V
A
W
ºC
Thermal Characteristics
RθJA
RθJR
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Balls
85
12
1
°C/W
9/14/03 Rev5
PRELIMINARY DATA SHEET
Electrical Characteristics
IGS S
VGS (th)
r
DS (on )
Zero Gate Voltage Drain Current
VDS =-12V, VGS =0V
-1
µA
Zero Gate Voltage Drain Current
VDS =-12V, VGS =0V, T=70°C
-5
µA
±100
nA
Gate-Body Leakage
Gate Threshold Voltage
VGS =±8V, VDS =0V
VDS =VGS , ID=-250µA
-0.7
V
Drain-Source On-State Resistance
VGS =-4.5V, ID=-1A
50
mΩ
Drain-Source On-State Resistance
VGS =-2.5V, ID=-1A
70
mΩ
Drain-Source On-State Resistance
VGS =-1.8V, ID=-1A
90
mΩ
Cis s
Input Capacitance
VDS =-12V, VGS =0V, F=1MHZ
800
pF
Cos s
Output Capacitance
VDS =-12V, VGS =0V, F=1MHZ
250
pF
Crs s
Reverse Transfer Capacitance
VDS =-12V, VGS =0V, F=1MHZ
100
pF
Qg
Total Gate Charge
VGS =-4.5V, ID=-1A, VDS =-6V
9.0
nC
-0.71
V
40
ns
VS D
trr
Diode Forward Voltage
Source-Drain Reverse Recovery Time
IS =-1A, VGS =0V
IS =-1A, VGS =0V, di/dt=100A/µs
2
TS8405P
IDS S
TA=25°C unless otherwise specified
9/14/03 Rev5
TS8405P
3
9/14/03 Rev5
TS8405P
4
9/14/03 Rev5
TS8405P
5
9/14/03 Rev5
TS8405P
6
9/14/03 Rev5
TS8405P
7
9/14/03 Rev5
TS8405P
8
9/14/03 Rev5
TS8405P
9
9/14/03 Rev5
TS8405P
10
9/14/03 Rev5
TS8405P
11
9/14/03 Rev5
PRELIMINARY DATA SHEET
Dimensional Outline and Pad Layout
TS8405P
Ø 0.30mm
Solder Mask Ø ~ 0.40mm
D
D
0.80mm
G
SILICON
S
0.27mm
0.80mm
0.80mm
MAX
D = Drain Pad
S = Source Pad
G = Gate Pad
LAND PATTERN
RECOMMENDATION
1.50mm
0.35mm
1.50mm
0.80mm
EXXXX
BACKSIDE VIEW (NO BUMP SIDE VIEW)
Bump Ø 0.37mm
0.80mm 0.35mm
Mark on backside of die
Bumps are Eutectic solder 63/37 Sn/Pb
E = 8405P Product Code
XXXX = Lot Traceability Code
Mark is located in lower right quadrant
on top of Source pad. Gate pad is located
in lower left quadrant.
11
9/14/03 Rev5