TPS65162 www.ti.com SLVS771 – MAY 2007 Compact LCD Bias IC With High Speed Amplifiers for TV-LCD Panels • • • FEATURES • • • • • • • 8-V to 14.4-V Input Voltage Range 500 kHz / 750 kHz Fixed Switching Frequency Boost Output Voltage up to 19 V – 1%-Accurate Boost With 2.8-A Switch Current Overvoltage Protection Input-to-Output Isolation Switch for Vs Short-Circuit protection for Boost 2.5-A Step-Down Converter Regulated Positive Charge-Pump Driver VGH Regulated Negative Charge-Pump Driver VGL Gate Voltage Shaping for VGH Soft Start for all Converters Two Integrated High-Speed Opamps – 50-MHz, 3-dB Bandwidth – Slew Rate 55 V / µs – 215-mA Short-Circuit Current 48 Pin 7x7 mm QFN Package • APPLICATIONS • • LCD TV LCD Monitor DESCRIPTION The TPS65162 is a compact LCD bias IC with two high-speed operational amplifiers for the Vcom supply. The high current capability of the device is ideal for large LCD-monitor and LCD-TV applications. L1 10 mH AVIN R1 39 kW C8 C9 22 mF 22 mF C7 220 pF Vs 15 V/1.5 A C10 22 mF R2 3.6 kW D2D3 DRVP D S VIN VGH C16 470 nF C17 470 nF R5 62 kW FBP SS C12 22 nF CE C14 100 pF Enable Gate Voltage shaping VDD VDPM SWB Buck Converter FBB FBN R4 51 kW R8 1.5 KW C20 100 nF SWB S D DRVN C18 470 nF VGH 25 V/50 mA R7 10 KW R10 1 KW CBOOT D4D5 R3 200 kW Vs RE VFLK VFLK R6 3.3 kW VGHM Gate Voltage Shaping VC C13 22 nF C7 470 nF SWI SW SW FREQ C12 1 mF FB Boost Converter EN2 VGL -5V/50mA SWO EN1 PVIN C4 22 mF C11 1 mF C11 1 mF C5 10 mF C2 22 mF PVIN C1 22 mF D1 SUP Vin 8 V to 14 V L2 10 mH D5 Vlogic 3.3 V/2.5 A C21 R11 2.4 kW 470 pF C22 22 mF C23 22 mF REF DLY1 AGND PGND3 PGND2 PGND1 POS2 NEG2 C24 10 nF R12 1.5 kW DLY2 2 POS1 OUT1 NEG1 OGND 1 OUT2 C19 220 nF GND C25 22 nF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS65162 www.ti.com SLVS771 – MAY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The TPS65162 generates all four voltage rails for a TFT LCD (Vs, Vlogic, VGH and VGL) and includes two op-amps to generate the VCOM supply rail. An input-to-output isolation switch is integrated into the device, providing short-circuit protection for the boost converter. A current-limit function is implemented in the input-to-output isolation switch to allow soft turn-on during start-up. The device also features gate voltage shaping for improved TFT-LCD picture quality. The device consists of a boost converter to provide the source voltage Vs, and a step-down converter to provide the logic voltage for the system. A positive and a negative charge-pump driver provide adjustable regulated output voltages VGH and VGL to bias the TFT. Both boost and buck converter, as well as the charge-pump drivers, operate with a fixed switching frequency of 500 kHz or 750 kHz, selectable by the FREQ pin. The device includes adjustable power-on sequencing. The safety features of the device are overvoltage protection for boost converter, short-circuit protection for Vs, Vlogic and VGH, and thermal shutdown. ORDERING INFORMATION (1) (1) TA ORDERING QFN PACKAGE PACKAGE MARKING –40°C to 85°C TPS65162RGZR 48 pin QFN TPS65162 The RGZ package is available taped and reeled and shipped in quantities of 2500 devices per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VI VALUE UNIT Input voltage range VIN, PVIN (2) –0.3 to 16.8 V Voltage range at EN1, EN2, FREQ, VDPM, VFLK Voltage on pin – 0.3 to 16.8 V AVIN, SUP 25 V VGH, VGHM, RE 35 V SW, SWI, SWO 25 V SWB 20 V Continuous total power dissipation See Dissipation Rating Table TJ Operating junction temperature range –40 to 150 °C TA Operating ambient temperature range –65 to 85 °C Tstg Storage temperature range –65 to 150 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) (1) PACKAGE RθJA TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 48 pin QFN 30°C/W 3.33 W 1.83 W 1.33 W Exposed thermal die is soldered to the PCB using thermal vias. Refer to Texas Instruments Application report (SLUA271) QFN/SON PCB Attachment. RECOMMENDED OPERATING CONDITIONS MIN 2 VIN, PVIN Input voltage range TA Operating ambient temperature TJ Operating junction temperature MAX UNIT 14.4 V –40 85 °C –40 125 °C 8 Submit Documentation Feedback TYP TPS65162 www.ti.com SLVS771 – MAY 2007 ELECTRICAL CHARACTERISTICS Vin=12 V, EN1=EN2=FREQ=high, Vs=15 V, Vlogic=3.3 V ,TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 14.4 V SUPPLY CURRENT VI ISD Input voltage range 8 Shutdown current into VIN EN1=EN2=GND 0.03 1 Shutdown current into PVIN EN1=EN2=GND 0.01 1 µA IQIN Quiescent current into VIN 1.7 4 mA ISUP Shutdown current into SUP EN1=EN2=GND 0.01 1 µA Shutdown current into AVIN EN1=EN2=GND 50 220 µA 8 10 mA IAVIN Quiescent current into AVIN VUVLO Undervoltage lockout threshold VREF Reference voltage Thermal shutdown Vin falling 1.253 Temperature rising Thermal shutdown hysteresis 7.6 7.95 1.265 1.277 V V 160 °C 10 °C LOGIC SIGNALS EN1, EN2, FREQ, VFLK, VDPM VIH High level input voltage EN1, EN2, VDPM, FREQ VIL Low level input voltage EN1, EN2, VDPM, FREQ VIH High level input voltage VFLK VIL lOW level input voltage VFLK II Input leakage current 2.0 V 0.8 1.7 EN1=EN2=FREQ=VFLK=VDPM=GND or VIN V V 0.01 0.4 V 0.1 µA CONTROL AND SOFT START DLY1, DLY2, SS Ichrg DLY1, DLY2 charge current ISS SS charge current Vthr Delay threshold Vthreshold = 1.280 V 3.5 5 6 6 9.2 12 1.280 µA V INTERNAL OSCILLATOR fosc Oscillator frequency FREQ = high 600 750 900 FREQ = low 400 500 600 1.255 1.268 1.280 V 10 100 nA 130 200 mΩ 9 15 Ω 1 A kHz BOOST CONVERTER (Vs) VS Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current RDS(on) 19 N-MOSFET on-resistance (Q1) Vs = 15 V, I(SW) = 500 mA P-MOSFET on-resistance (Q2) Vs = 15 V,I(SW) = 200 mA IMAX Maximum P-MOSFET peak switch current ILIM N-MOSFET switch current limit (Q1) Ileak Switch leakage current V(SW) = 15 V Vswovp Switch overvoltage protection Vout rising Line Regulation 8V≤Vin≤14V, Iout = 2mA Load Regulation 2.8 19.5 V 3.6 4.2 A 1 10 µA 20 21 V 0.007 %/V 2mA≤Iout≤1.5A 0.03 %/A ISW = 1 A, Vs = 15 V 200 ISOLATION SWITCH RDSon Isolation switch RDSon I Switch current ISC Short circuit current limit mΩ 2 SWI = 12V, SWO = 0V Submit Documentation Feedback 350 A mA 3 TPS65162 www.ti.com SLVS771 – MAY 2007 ELECTRICAL CHARACTERISTICS (continued) Vin=12 V, EN1=EN2=FREQ=high, Vs=15 V, Vlogic=3.3 V ,TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE VOLTAGE SHAPING VGHM VHVIN Input voltage 35 VGH to VGHM RDSon (Q1) VFLK = high, I = 20 mA 10 15 VGHM to RE RDSon VFLK = LOW, I = 20 mA 60 100 ICE CE capacitor charge current VCE = 1.265 V 57 65 VCE CE threshold voltage GVDD VDD voltage gain RDSon 44 1.284 VVDD = 1 V V Ω µA V 5 V/V STEP-DOWN CONVERTER (Vlogic) Vlogic Output voltage range VFB Feedback regulation voltage 1.5 IFB Feedback input bias current RDS(on) N-MOSFET on-resistance (Q1) ILIM N-MOSFET switch current limit (Q1) Ileak Switch leakage current V(SW) = 0 V Line regulation 8V≤Vin≤14V, Iout = 2mA Load regulation 2mA≤Iout≤2.5A 5 1.240 PVIN = 12 V, I(SW) = 500 mA 2.8 V 1.265 1.290 V 10 100 nA 180 320 mΩ 3.6 4.2 A 1 10 µA 0.006 %/V 0.06 %/A NEGATIVE CHARGE PUMP VGL VGL Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current RDS(on) Q4 P-Channel switch RDSon VDropN Current source voltage drop (1) Load regulation -2 V 0 48 mV 10 100 nA 4 8 Ω I(DRVN) = 50 mA, V(FBN) = V(FBNnominal)– 5% 115 200 I(DRVN) = 100 mA, V(FBN) = V(FBNnominal)– 5% 230 400 1 mA ≤ IO ≤ 100 mA, VGL = –5 V 0.01 –48 IO = 20 mA mV %/mA POSITIVE CHARGE PUMP OUTPUT VGH VGH Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current RDSon Q3 N-Channel switch RDSon VDropP Current source voltage drop (Vsup–VDRP)(1) Load regulation 34 1.228 1.302 V 10 100 nA Ω IOUT = 20 mA 1.0 1.8 IDRP = 50 mA, VFBP = VFBPnominal– 5% 430 680 IDRP = 100 mA, VFBP = VFBPnominal– 5% 950 1600 1 mA ≤ Iout ≤ 50 mA, VGH = 27 V V 1.265 0.073 mV %/mA OPERATIONAL AMPLIFIERS 1, 2 Vos Input offset voltage VCM = Vs/2 IB Input bias current VCM = Vs/2 VCM Common Mode Input Voltage Range CMRR Common Mode Rejection Ratio VCM = 7.5 V 70 AVOL Open Loop Gain 0.5 V ≤ VOUT≤ 14.5 V, No load 50 VOL Output Voltage Swing Low IOUT = 10 mA VOH Output Voltage Swing High IOUT = 10 mA Isc Short Circuit Current Io Output Current PSRR Power Supply Rejection Ratio SR Slew Rate BW – 3db Bandwidth GBWP Gain Bandwidth Product (1) 4 –15 0.05 0 VOUT = 7.5 V , Input offset voltage 10 mV 18 mV 3 µA Vs V dB dB 60 200 mV Vs-200 Vs-100 mV 120 215 mA 90 170 mA 80 dB AV = 1, VIN = 2 Vpp 55 V/µs AV = 1, VOUT = 60 mVpp 50 MHz 36 MHz The maximum charge pump output current is typically one-half the drive current of the internal current source. Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 OUT2 POS2 NEG2 AVIN SWO FB NC SWI 1 48 47 46 45 44 43 42 41 40 39 OUT1 SW OGND POS1 SW NEG1 PIN ASSIGNMENT Top View 38 3736 PGND3 2 35 PGND2 VDD 3 34 PGND1 CE 4 33 EN1 VFLK 5 32 EN2 VDPM 6 31 VC 30 SS Exposed Thermal Pad 28 FREQ FBP 10 27 VIN GND 11 26 PVIN 25 PVIN 16 17 18 19 20 NC 15 AGND 14 DRVN 12 13 SUP DRVP 21 22 23 24 SWB 9 SWB VGH CBOOT DLY2 FBB 29 NC 8 DLY1 VGHM REF 7 FBN RE NOTE: The thermally-enhanced PowerPAD is connected to PGND1 (Device power Ground). NC pin is internally not connected. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. POS1 1 I Non inverting input of Operational Amplifier 1 OUT1 2 O Output of Operational Amplifier 1. VDD 3 I Threshold voltage of gate voltage shaping. The five times of voltage applied to this pin set the threshold discharge voltage for the gate voltage shaping function CE 4 I Delay of gate voltage shaping. Sets the delay between the falling edge of VFLK to the falling edge of VGHM VFLK 5 I Control of gate voltage shaping. VDPM 6 I Enable of gate voltage shaping block. RE 7 O Slope adjustment of gate voltage shaping. Connecting a resistor to this pin allows to adjust the slop of gate voltage shaping. VGHM 8 O Output of the gate voltage shaping block. VGH 9 I High voltage for gate voltage shaping block. Connect the output of the positive charge pump to this pin. FBP 10 I Feedback of the positive charge pump. GND 11 DRVP 12 O Drive pin of the positive charge pump. SUP 13 I Supply pin of the positive charge pump DRVN 14 O Drive pin of the negative charge pump AGND 15 FBN 16 Ground for positive and negative charge pump. Analog ground I Feedback of the negative charge pump. Submit Documentation Feedback 5 TPS65162 www.ti.com SLVS771 – MAY 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME 6 NO. I/O DESCRIPTION REF 17 O Internal reference output. Connect 220-nF capacitor directly from this pin to AGND to minimize possible noise coupling into the reference of the IC. DLY1 18 O Connecting a capacitor from this pin to GND allows setting the delay time between the step down converter and negative charge pump VGL NC 19, 20, 40 FBB 21 I Feedback of the buck converter. CBOOT 22 I N-channel MOSFET gate drive voltage for the buck converter. Connect a capacitor from this pin to SWB. SWB 23, 24 O Switch pin of the buck converter PVIN Not connected. 25, 26 I Power input for the buck converter. VIN 27 I Analog input voltage of the device. This pin should be bypassed with a 1-µF capacitor for good filtering. FREQ 28 I Frequency selection pin. With FREQ=high, the device operates with 750 kHz. With FREQ=low, the device operates with 500kHz. DLY2 29 O Connecting a capacitor from this pin to GND allows setting the delay time between the step down converter and positive charge pump VGH. SS 30 O soft-start of the boost converter. Connect a capacitor from this pin to GND. VC 31 O Compensation pin of the boost converter. EN2 32 I Enable pin of the boost converter block. EN1 33 I Enable pin of the buck converter and negative charge pump. When this pin is pulled high, the buck converter starts up, and after a delay time set by DLY1, the negative charge pump starts up. A logic high enables the device and a logic low shut down the device. PGND1 34 PGND2 35 PGND3 36 Power ground. Ground for boost converter. SW 37, 38 I Switch pin of the boost converter SWI 39 I Input of the isolation switch. The SWI pin is connected to internal overvoltage protection comparator. FB 41 I Feedback of the boost converter generating Vs SWO 42 O Output of the isolation switch AVIN 43 I Power input voltage pin for Operational Amplifier. Bypass this pin with a 1-µF bypass capacitor NEG2 44 I Inverting input of Operational Amplifier 2 POS2 45 I Non inverting input of Operational Amplifier 2 OUT2 46 O Output of Operational Amplifier 2 OGND 47 NEG1 48 Ground for Operational Amplifier. I Inverting input of Operational Amplifier 1 Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 FUNCTIONAL BLOCK DIAGRAM L1 10 mH AVIN R1 39 kW C8 C9 22 mF 22 mF C7 220 pF Vs 15 V/1.5 A C10 22 mF R2 3.6 kW D2D3 DRVP D S VIN VGH C16 470 nF C17 470 nF R5 62 kW FBP SS C12 22 nF CE C14 100 pF Enable Gate Voltage shaping VDD VDPM SWB Buck Converter C18 470 nF FBB FBN R4 51 kW R8 1.5 KW C20 100 nF SWB S D DRVN VGH 25 V/50 mA R7 10 KW R10 1 KW CBOOT D4D5 R3 200 kW Vs RE VFLK VFLK R6 3.3 kW VGHM Gate Voltage Shaping VC C13 22 nF L2 10 mH D5 Vlogic 3.3 V/2.5 A C21 R11 2.4 kW 470 pF C22 22 mF C23 22 mF REF DLY1 AGND PGND3 PGND2 PGND1 POS2 NEG2 C24 10 nF R12 1.5 kW DLY2 2 POS1 OUT1 NEG1 1 OUT2 C19 220 nF OGND C7 470 nF SWI SW SW FREQ C12 1 mF FB Boost Converter EN2 VGL -5V/50mA SWO EN1 PVIN C4 22 mF C11 1 mF C11 1 mF C5 10 mF C2 22 mF PVIN C1 22 mF D1 SUP Vin 8 V to 14 V GND Submit Documentation Feedback C25 22 nF 7 TPS65162 www.ti.com SLVS771 – MAY 2007 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Main Boost Converter (Vs) η Efficiency vs Load current Figure 1 Soft start Figure 2 PWM operation at nominal load current Figure 3 PWM operation at light load current Figure 4 Load transient response Figure 5 Short-circuit protection Figure 6 Overvoltage protection Figure 7 Step-Down Converter (Vlogic) η Efficiency vs Load current Figure 8 PWM operation at nominal load current Figure 9 PWM operation at light load current Figure 10 Soft start Figure 11 Load transient response Figure 12 System Performance Powerup sequencing EN2 connected to VIN Figure 13 Powerup sequencing EN2 enabled separately Figure 14 Gate voltage shaping Figure 15 Negative Charge Pump Driver VGL vs VGL Load current Figure 16 VCOM BUFFERS –3 dB bandwidth, opamp Figure 17 Slew rate, opamp Figure 18 BOOST CONVERTER (Vs) η EFFICIENCY vs LOAD CURRENT SOFT-START 100 VI = 14 V 90 VO 10 V/div VI = 12 V VI = 8 V 80 Efficiency - % VI = 12 V, VO = 15 V/1.2 A C(SS) = 22 nF VSW 10 V/div 70 60 VS = 15 V, VGH, VGL, VLOGIC no Load Switching OpAmp no Load Operating 50 II 1 A/div 40 0 0.5 1 IO - Output Current - A 1.5 Figure 1. 8 2.5 ms/div Figure 2. Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 PWM OPERATION AT NOMINAL LOAD CURRENT PWM OPERATION, LIGHT LOAD CURRENT VI = 12 V, VO = 15 V/1.5 A VI = 12 V, VO = 15 V/10 mA VSW 10 V/div VSW 10 V/div VO 50 mV/div VO 50 mV/div IL 1 A/div IL 500 mA/div 1 ms/div 1 ms/div Figure 3. Figure 4. LOAD TRANSIENT RESPONSE SHORT CIRCUIT PROTECTION VI = 12 V, VO = 15 V Output shorted VO 200 mV/div VO 5 V/div IL 500 mA/div IO 500 mA/div VI = 12 V, VO = 15 V/div 500 ms/div 100 ms/div Figure 5. Figure 6. Submit Documentation Feedback 9 TPS65162 www.ti.com SLVS771 – MAY 2007 OVERVOLTAGE PROTECTION VSW 10 V/div VO 2 V/div VI = 12 V, VO = 15 V/100 mA IL 2 A/div 500 ms/div Figure 7. STEP-DOWN CONVERTER (Vlogic) η EFFICIENCY vs LOAD CURRENT PWM OPERATION, NOMINAL LOAD CURRENT 90 Efficiency - % 80 VI = 8 V VI = 12 V VI = 14 V 70 VSW 5 V/div 60 VO 20 mV/div 50 VLOGIC = 3.3 V, VS, VGH, VGL No Load Switching OpAmp No Load, Operating IL 1 A/div 40 0 0.5 1 1.5 IO - Output Current - mA 2 2.5 Figure 8. 10 VI = 12 V, VO = 3.3 V/1.5 A 500 ns/div Figure 9. Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 PWM OPERATION, LIGHT LOAD CURRENT SOFT START VI = 12 V, VO = 3.3 V/45 mA VI = 12 V, VO = 3.3 V/1.2 A VSW 5 V/div VO 1 V/div VO 20 mV/div IL 1 A/div IL 200 mA/div 500 ms/div 500 ns/div Figure 10. Figure 11. LOAD TRANSIENT RESPONSE VI = 12 V, VO = 3.3 V VO 100 mV/div IO 1 A/div 100 ms/div Figure 12. Submit Documentation Feedback 11 TPS65162 www.ti.com SLVS771 – MAY 2007 SYSTEM PERFORMANCE POWERUP SEQUENCING vs EN2 CONNECTED TO VIN POWERUP SEQUENCING vs EN2 ENABLED SEPARATELY VLOGIC 2 V/div VLOGIC 2 V/div VS 5 V/div VS 5 V/div VGH 10 V/div VGH 10 V/div VGL 5 V/div EN2 10 V/div 2.5 ms/div 2.5 ms/div Figure 13. Figure 14. GATE VOLTAGE SHAPING VGHM 10 V/div VDD = 2 V, RE = 33 kW, VGH = NO LOAD IO 2 V/div 5 ms/div Figure 15. 12 Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 NEGATIVE CHARGE PUMP DRIVER VGL vs VGL LOAD CURRENT -4.94 VS = 15 V, VGL = -5 V -4.96 TA = 85°C VGL - V -4.98 -5 TA = -40°C -5.02 TA = 25°C -5.04 -5.06 -5.08 -5.10 0 10 20 30 40 50 60 70 80 IO - Output Current - mA 90 100 Figure 16. VCOM BUFFERS Magnitude - dB –3-dB BANDWIDTH, OPAMP SLEW RATE, OPAMP Output: No load 0 dB 1 dB/div IN 1 V/div OUT 1 V/div 1 10 f - Frequency - MHz 100 Figure 17. Output: no load Input: 1.6 V Step 10 ns/div Figure 18. Submit Documentation Feedback 13 TPS65162 www.ti.com SLVS771 – MAY 2007 APPLICATION INFORMATION THERMAL SHUTDOWN The thermal-shutdown feature prevents damage from excessive heat and power dissipation. Typically, the thermal-shutdown threshold is 160°C. When the temperature drops below the thermal shutdown threshold, the device restarts again automatically. UNDERVOLTAGE LOCKOUT To avoid device malfunction at low input voltages, an undervoltage lockout is included, which shuts down the device at voltages lower than 7.6 V. REFERENCE OUTPUT, REF The device provides a reference output that is used to regulate the negative charge pump. In order to have a stable reference voltage, a 220-nF bypass capacitor is required, connected directly from REF to AGND. The reference output has a current capability of 30 µA which should not be exceeded. Because of this, the feedback resistor from FBN to REF should not be smaller than 40 kΩ. START-UP SEQUENCING The start-up sequencing can be set by adjusting the capacitors connected to DLY1 and DLY2, and is controlled by the signals EN1 and EN2. Pulling EN1 high enables the step-down converter. After the step down converter has reached its power-good threshold, the other sequence timings are started. DLY1 sets the delay time between the step-down converter and the negative charge-pump driver. This delay starts when the power-good threshold of the step-down converter is reached. A high level on EN2 enables the boost converter. The boost converter starts when the power-good threshold of the step down converter is reached and EN2 is pulled high. DLY2 sets the delay time for the positive charge pump. This delay time starts when the power good threshold of the step down converter is reached. After the delay time has expired, the positive charge pump and op-amps start up. As the positive charge pump power-good threshold is reached, then the GPM block is enabled if VDPM is high as well. See Figure 19. EN1 EN2 DLY 2 VGHM with VFLK =high, VDPM=high Vs Fall time depends on output capacitors value and load current V logic VGL DLY 1 Figure 19. Power-On Sequencing With EN2 Always High (EN2=VIN) 14 Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 APPLICATION INFORMATION (continued) If EN2 goes high after the step down converter is already enabled, then the delay DLY2 starts when EN2 goes high. See Figure 20. EN1 EN2 DLY 2 VGHM with VFLK =high, VDPM=high Vs Fall time depends on output capacitors value and load current Vlogic VGL DLY 1 Figure 20. Power-on Sequencing Using EN1 and EN2 SETTING THE DELAY TIMES DLY1, DLY2 Connecting an external capacitor to the DLY1 and DLY2 pin sets the delay time. If no delay time is required these pins can be left open. To set the delay time the external capacitor connected to DLY1 and DLY2 is charged with a constant current source of typically 5 µA. The delay time is terminated when the capacitor voltage has reached the internal reference voltage of VREF=1.280 V. The external delay capacitor is calculated using Equation 1: 5 mA ´ t d 5 mA ´ t d C dly = = VREF 1.280 V (1) where td = Desired delay time Example for setting a delay time of 5.3 ms: 5 mA 5.3 ms C dly + + 20.7 nF [ 22 nF 1.280 V Submit Documentation Feedback (2) 15 TPS65162 www.ti.com SLVS771 – MAY 2007 APPLICATION INFORMATION (continued) BOOST CONVERTER The TPS65162 boost converter block is shown in Figure 21. The boost converter operates with PWM (Pulse Width Modulation) at a fixed switching frequency of 500 kHz or 750 kHz, selected by the FREQ pin. The converter uses an unique fast-response, voltage-mode controller scheme with input-voltage feedforward. This achieves excellent line and load regulation (0.03%/A load regulation typical), and allows the use of small external components. To add more flexibility to the selection of external component values, the device uses external loop compensation. Although the boost converter looks like a non-synchronous boost converter topology operating in discontinuous-conduction mode under a light load, the TPS65162 remains in continuous-conduction mode even under light load currents. (Figure 4) This is achieved with a novel architecture using an external Schottky diode with an integrated MOSFET in parallel connected between the SW pin and the SUP pin. This MOSFET allows the current to go below ground, which is the case under light load conditions. For this use, a small integrated P-Channel MOSFET (Q2) with typically 9 Ω RDSon is sufficient. When the inductor current is positive, the external Schottky diode, with the lower forward voltage, carries the current. This causes the converter to operate with a fixed frequency in continuous-conduction mode over the entire load-current range. This avoids ringing on the switch pin as seen with a standard non-synchronous boost converter, and allows a simpler compensation circuit for the boost converter. VIN FREQ SW SWI SW SWO IDLY D Vref SS Control logic EN D S S Q2 D EN Clock COMP 500kHz/ 750KHz Oszillator Comparator Control Logic D S Q1 Sawtooth Generator FB PGND2 Overvoltage Comparator OVP VFB 1.268V GM Amplifier Low Gain Vref VFB 1.268V SUP Current limit and Soft Start GM Amplifier SUP Figure 21. Boost Converter Block TPS65162 16 S Vds Sensor Soft start Submit Documentation Feedback PGND3 TPS65162 www.ti.com SLVS771 – MAY 2007 APPLICATION INFORMATION (continued) Soft Start To minimize inrush current during startup, the boost converter has an adjustable soft-start, and the input-to-output isolation switch has current-limit control. The current limit of the input-to-output isolation switch is slowly ramped up for a soft turn-on. The VDS sensor of the input-to-output isolation switch monitors the voltage difference between SWI and SWO, and controls the current through the isolation switch. With VDS = 12 V, the current-limit threshold through the isolation switch is typically 330 mA. This current-limit threshold will linearly increase by factor of two till VDS reaches 3 V; current limiting is disabled when VDS is below 3 V. The boost converter is enabled when VDS is below 0.5 V. An external capacitor connected to the soft-start pin, SS, is used to slowly ramp up the internal switch current limit of the boost converter. The capacitor connected to the SS pin is charged with a constant current that increases the voltage on the SS pin. The internal current limit is proportional to the voltage on the SS pin. When the threshold voltage of the internal-switch soft-start comparator is reached, the full current limit is released. The larger the soft-start capacitor value, the longer the soft-start time. A 22-nF capacitor is usually sufficient for typical applications. Overvoltage Protection The boost converter has an overvoltage-protection circuit to prevent the switch voltage from exceeding the absolute-maximum switch voltage rating in the event of a system fault. The device protects itself if the feedback pin is connected to ground or floated, and clamps the voltage of the output of the boost converter to 20 V. To implement the overvoltage protection, the overvoltage comparator shown in Figure 21 monitors the output voltage via the SWI pin. As soon as the output voltage exceeds the overvoltage threshold (typically 20 V), the device stops switching until the output voltage drops below the comparator threshold again. The typical waveform when the device is in overvoltage protection is shown in Figure 7. Short CIrcuit Protection The boost converter has a short-circuit protection circuit to prevent the inductor or rectifier diode from overheating when the output is shorted. The VDS sensor in the input-to-output isolation switch monitors the voltage difference between SWI and SWO. If the boost output is shorted, and the voltage difference between SWI and SWO exceeds the threshold (typically 1.4 V in full operation), then the boost converter shuts down, and the input-to-output isolation switch limits VS current. Input Capacitor Selection (VIN, SUP) Low ESR ceramic capacitors are recommended for good input-voltage filtering. The TPS65162 has an analog input (VIN) as well as a power supply input (SUP) powering all the internal rails. A 1-µF bypass capacitor is required as close as possible from VIN to GND, and from SUP to GND. Depending on the overall load current, two or three 22-µF input capacitors are required. For better input-voltage filtering, the input capacitor values can be increased. Refer to Table 1 and the Typical Applications schematic for input capacitor recommendations. Table 1. Input Capacitor Selection CAPACITOR COMPONENT SUPPLIER COMMENTS 22 µF / 16 V Taiyo Yuden EMK316BJ226ML Pin VIN, PVIN 2 ×10 µF / 25 V Taiyo Yuden TMK316BJ106KL Pin VIN, PVIN (Alternative) 1 µF / 35 V Taiyo Yuden GMK107BJ105KA Pin SUP, AVIN, VIN 1 µF / 25 V Taiyo Yuden TMK107BJ105KA Pin SUP, AVIN, VIN Frequency Select Pin, FREQ The frequency-select pin FREQ selects the switching frequency of the entire device to 500 kHz (FREQ=low) or 750 kHz (FREQ=high). A lower switching frequency gives a higher efficiency with a slightly reduced load-transient regulation. Submit Documentation Feedback 17 TPS65162 www.ti.com SLVS771 – MAY 2007 Boost Converter Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. To simplify the calculation, the fastest approach is to estimate the converter efficiency, by taking the efficiency numbers from the provided efficiency curves, or to use a worst-case assumption for the expected efficiency, e.g., 80%. With the efficiency number it is possible to calculate the steady-state values of the application. Vin h Vout 1. Converter Duty Cycle: D +1* 2. Maximum output current: Iout + Isw * Vin D 2 ƒs L 3. Peak switch current: I I swpeak + Vin D ) out 2 ƒs L 1 * D ǒ Ǔ (1 * D) With Isw = converter switch current (minimum switch current limit = 2.8 A) ƒs = converter switching frequency (typical 500kHz or 750 kHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency curves or 0.8 as an estimation) The peak switch current is the steady-state peak switch current that the integrated switch, inductor and external Schottky diode must be able to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest. Inductor Selection The TPS65162 typically operates with a 10-µH inductor. The main parameter for inductor selection is the inductor saturation current, which should be higher than the peak switch current, as calculated above, with additional margin to handle heavy load transients. An alternative more conservative approach is to choose an inductor with a saturation current at least as high as the typical switch current limit of 3.6 A. The second important parameter is the inductor DC resistance. Usually, the lower the DC resistance, the higher the efficiency of the converter. The choice of inductor can affect converter efficiency by as much as 10%. Example inductors are shown in Table 2. Table 2. Inductor Selection (Boost Converter) INDUCTOR VALUE COMPONENT SUPPLIER DIMENSIONS in mm Isat/DCR 10 µH Coilcraft DO3316P-103 12.95 × 9.4 × 5.51 3.9 A / 38 mΩ 10 µH Sumida CDRH8D43-100 8.3 × 8.3 × 4.5 4.0 A / 29 mΩ 10 µH Wuerth Elektronik 744066100 10 × 10 × 3.8 4.0 A / 25 mΩ Output Capacitor For best output-voltage filtering, a low-ESR output capacitor is recommended. Ceramic capacitors have a low ESR value and work best with the TPS65162. One 10-µF ceramic output capacitor before the input-to-output isolation switch, SWI, and six 10-µF or three 22-µF ceramic output capacitors in parallel after the input-to-output isolation switch, SWO, are sufficient for most applications. To improve the load transient regulation, add more capacitors after the input-to-output isolation switch. Refer to Table 3 for the selection of the output capacitor. Table 3. Output Capacitor Selection 18 CAPACITOR COMPONENT SUPPLIER 10 µF/25 V Taiyo Yuden TMK316BJ106KL 22 µF/25 V TDK C4532X7R1E226M Submit Documentation Feedback COMMENTS Alternative solution TPS65162 www.ti.com SLVS771 – MAY 2007 Rectifier Diode Selection To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the converter. The current rating for the Schottky diode is calculated as the off time of the converter times the typical switch current of the TPS65162: V Iavg = (1 - D) × ISW = in ´ 3.6 A Vout (3) where ISW=typical switch current of the TPS65162 (3.6 A) A Schottky diode with 2-A maximum average rectified forward current rating is sufficient for most applications. The Schottky rectifier must have adequate power dissipation. The dissipated power is the average rectified forward current times the diode forward voltage. PD = Iavg × VF = ISW × (1 - D) × VF (4) where ISW=typical switch current of the TPS65162 (3.6 A) Table 4. Rectifier Diode Selection (Boost Converter) Iavg Vr Vforward RθJA SIZE COMPONENT SUPPLIER 3A 2A 20 V 0.36 at 3 A 46°C/W SMC MBRS320, International Rectifier 20 V 0.44 V at 2 A 75°C/W SMB 2A SL22, Vishay Semiconductor 20 V 0.5 at 2 A 75°C/W SMB SS22, Fairchild Semiconductor Setting the Output Voltage and Selecting the Feedforward Capacitor The output voltage is set by the external resistor divider and is calculated as: V out + 1.268 V ǒ1 ) R1 Ǔ R2 (5) Across the upper resistor a bypass capacitor is required to speed up the circuit during load transients. The capacitor is caluculated as: 1 C ff = 2 × p × f z × R1 (6) Depending on the inductor value, the zero frequency needs to be set. fz is 19 kHz for a 10 µH inductor, and 9 kHz for a 22 µH inductor. A value coming closest to the calculated value should be used. Compensation (VC) The regulator loop can be compensated by adjusting the external components connected to the VC pin. The VC pin is the output of the internal transconductance error amplifier. A single capacitor connected to this pin sets the low frequency gain. A 22-nF capacitor is usually sufficient for most applications. Submit Documentation Feedback 19 TPS65162 www.ti.com SLVS771 – MAY 2007 POSITIVE CHARGE PUMP The positive charge pump provides a regulated output voltage set by the external resistor divider. The TPS65162 positive charge pump block is shown in Figure 22. SUP 500 kHz/ 750 KHz Oscillator IDRVP Current Control Softstart DRVP Q5 GND Vref 1.265V FBP Figure 22. Positive Charge Pump Block TPS65162 Since the flying capacitor-voltage sits on top of the drive-pin voltage, the maximum output voltage is VSUP+VS– Vdrop. Vdrop is the voltage drop across the external diodes and internal charge pump MOSFETs. If higher output voltages are required, another charge pump stage can be added to the output. Setting the output voltage: V out + VREF ǒ1 ) R5 Ǔ + 1.265 V ǒ1 ) R5 Ǔ R6 R6 (7) To minimize noise and leakage current sensitivity, we recommend a value of approximately 20 kΩ for the lower feedback divider resistor R6. 20 Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 NEGATIVE CHARGE PUMP The negative charge pump provides a regulated output voltage set by the external resistor divider. The TPS65162 negative charge pump block is shown in Figure 23. The negative charge pump operates very similar to the positive charge pump, with the difference that it runs from the input voltage VIN. The maximum negative output voltage is VGL=(–VIN)+Vdrop. Vdrop is the voltage drop across the external diodes and internal charge-pump MOSFETs. The output voltage is calculated by: V out + *VREF R3 + *1.265 V R4 R3 R4 (8) Since the reference-output driver current should not exceed 30uA (typical), the lower feedback resistor value R4 should be in a range of 40 kΩ to 120 kΩ. Overall feedback resistance should be in the range from 500 kΩ to 1 MΩ. The negative charge pump requires two external Schottky diodes. The peak current rating of the Schottky diode must be twice the load current of the output. For a 20-mA output current, the dual Schottky diode BAV99 is a good choice. VIN 500 kHz/ 750 KHz Oscillator Q7 DRVN Control Logic Softstart IDRVN GND FBN Vref 0V Figure 23. Negative Charge Pump Block TPS65162 GATE VOLTAGE SHAPING The gate voltage shaping reduces the flickering effect of an LCD panel, and isolates VGHM from the source voltage VGH. For correct operation of this block, it is not recommend to connect an output capacitor to VGHM. To reduce the voltage ripple on VGHM, add more capacitors on VGH. The TPS65162 gate voltage shaping block is shown in Figure 24. The corresponding timing diagram is shown in Figure 26. The gate voltage shaping block responds to VFLK under the following conditions: • The device is enabled with VDPM = high • The input voltage is above the undervoltage lockout • The positive charge pump is in regulation When VGH is pulled below its power-good level, Q1 and Q2 are turned off and VGHM is discharged via the 1-kΩ resistor over Q3. With VFLK = high, Q1 and Q4 are turned on and Q2 is turned off. VGH is present at VGHM when Q1 is on, and at the same time, the capacitor connected to the CE pin is discharged by Q4 to Submit Documentation Feedback 21 TPS65162 www.ti.com SLVS771 – MAY 2007 GND. When VFLK is taken low, Q4 is turned off, and the capacitor connected to the CE pin is charged by a constant current source, typically 60 µA. When the capacitor voltage reaches the internal reference voltage of 1.284 V and VFLK is low, Q1 is turned off and Q2 is turned on. With Q2 on, VGHM is discharged by the resistor connected to the RE pin. Once VGHM is discharged to five times VDD, Q2 is turned off and VGHM is high impedance. In the application of not using this function, connect VDPM, VFLK with high. VGH VDPM Q1 VGHM 1K 4R Q3 R Q2 S RE Q R INT_REG IDLY VDD Vref CE SZ Q RZ Thermal shutdown Q4 Power good from FBP UVLO VFLK Figure 24. Gate Voltage Shaping Block TPS65162 VGH VGHM 5 x VDD Gate voltage shaping delay time Charge CE capacitor to its threshold voltage VFLK Discharge CE capacitor Figure 25. Gate Voltage Shaping Block TPS65162 22 Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 STEP-DOWN CONVERTER The TPS65162 step down converter block is shown in Figure 26. The non-synchronous step down converter operates at a fixed switching frequency using a fast response voltage mode topology with input voltage feedforward. This topology allows simple internal compensation and it is designed to operate with ceramic output capacitors. The converter drives an internal 2.8 A N-Channel MOSFET switch. The MOSFET driver is referenced to the switch pin SWB. The N-Channel MOSFET requires a gate drive voltage higher than the switch pin to turn the N-Channel MOSFET on. This is accomplished by a boost strap gate drive circuit running of the step down converter switch pin. When the switch pin SWB is at ground the boot strap capacitor is charged to 8 V. This way the N-Channel Gate drive voltage is typically around 8 V. Soft Start To avoid high inrush current during startup, an internal soft-start is implemented. When the step down converter is enabled over EN1, its reference voltage slowly rises from zero to its power good threshold of typically 90% of Vref. When the reference voltage reaches this power good threshold, the Error amplifier is released to its normal operation with its normal duty cycle. To further limit the inrush current during soft-start the converter frequency is set to 1/4 of the switching frequency ƒs and 1/2 of ƒs by the comparator that monitors the feedback voltage. refer to the internal block diagram. The typical soft-start is typically completed within 1ms. Short Circuit Protection To limit the short circuit current, the device has a cycle-by-cycle current limit. To prevent the short-circuit current from rising above the internal current limit when the output is shorted to GND, the switching frequency is reduced as well. This is implemented by two comparators monitoring the feedback voltage. The step-down converter switching frequency is reduced to 1/2 of ƒfs when the feedback is below 0.9 V, and 1/4 of the switching frequency when the feedback voltage is below 0.6 V. PVIN Regulator 8V BOOT Q3 PVIN SWB SWB Control Logic Current limit Error Amplifier FBB Vref Compensation and Softstart Sawtooth Generator Clock/2 Logic 0.9V Clock/4 0.6V Clock Clock 500/750 kHz Clock select for short circuit and softstart Figure 26. Step Down Converter Block TPS65162 Submit Documentation Feedback 23 TPS65162 www.ti.com SLVS771 – MAY 2007 Setting the Output Voltage The step-down converter uses an external voltage divider to set the output voltage. The output voltage is calculated as: V out + 1.265 V ǒ1 ) R5 Ǔ R6 (9) At load currents <1 mA, the device operates in discontinuous conduction mode. When the load current is reduced to zero the output voltage rises slightly above the nominal output voltage. At zero load current, the device skips clock cycles, but does not completely stop switching, thus the output voltage sits slightly above the nominal output voltage. Therefore, the lower feedback resistor is selected to be around 1.2 kΩ to maintain around 1 mA minimum load current. Selecting the Feedforward Capacitor The feedforward capacitor across the upper feedback resistor divider forms a zero around 135 kHz, and is calculated as: 1 1 Cz + + + 471.6 pF [ 470 pF 2 p 135kHz R5 2 p 135kHz 2.5kW (10) Usually the standard capacitor value closest to the calculated value is selected. Inductor Selection The TPS65162 step-down converter typically operates with a 10-µH inductor. For high efficiency, the inductor should have a low DC resistance to minimize conduction loss. This must be considered when selecting the appropriate inductor. In order to avoid inductor saturation, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current that will be calculated by: 1 * Vout DI Vin DI L + Vout I Lmax + I outmax ) L 2 L ƒ (11) where ƒ = Switching Frequency (750 kHz, 500 kHz minimal) L = Inductor Value (typically 10 µH) ∆IL= Peak to Peak inductor ripple current ILmax = Maximum Inductor current The highest inductor current occurs at maximum Vin. A more conservative approach is to select the inductor current rating just for the typical switch-current limit of 3.5 A. Table 5. Inductor Selection INDUCTOR VALUE 24 COMPONENT SUPPLIER DIMENSIONS in mm Isat/DCR 10 µH Coilcraft DO3316P-103 12.95 × 9.4 × 5.51 3.9 A/38 mΩ 10 µH Sumida CDRH8D43-100 8.3 × 8.3 × 4.5 4.0 A/29 mΩ 10 µH Wuerth Elektronik 744066100 10 × 10 × 3.8 4.0 A/25 mΩ Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 Rectifier Diode Selection To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the step-down converter. The averaged rectified forward current for which the Schottky diode should be rated is calculated as the off time of the step-down converter times the minimum switch current of the TPS65162: V D = OUT VIN (12) Iavg = (1 - D) × ISW = (1 - VOUT ) × 2.8 A VIN (13) where Isw = minimum switch current of the TPS65162 (2.8 A) Usually a Schottky diode with 2 A maximum average rectified forward current rating is sufficient for most of the applications. Secondly the Schottky rectifier has to be able to dissipate the power. The dissipated power is the average rectified forward current times the diode forward voltage. P D + I avg VF + Isw (1 * D) VF with ISW = minimum switch current of the TPS65162 (2.8 A) Table 6. Rectifier Diode Selection (Step-Down Converter) CURRENT RATING Iavg Vr Vforward RθJA SIZE COMPONENT SUPPLIER 3A 20 V 0.36 V at 3 A 46°C/W SMC MBRS320, International Rectifier 2A 20 V 0.44 V at 2 A 75°C/W SMB SL22, Vishay Semiconductor 2A 20 V 0.5 V at 2 A 75°C/W SMB SS22, Fairchild Semiconductor Output Capacitor Selection The device is designed to work with ceramic output capacitors. Two 22-µF output capacitors are sufficient for most of the applications. Larger output capacitance improves the load transient response. Table 7. Output Capacitor Selection Step-Down Converter CAPACITOR COMPONENT SUPPLIER 22 µF/6.3 V Taiyo Yuden JMK212BJ226MG Submit Documentation Feedback COMMENT 25 TPS65162 www.ti.com SLVS771 – MAY 2007 OPERATIONAL AMPLIFIER 1 AND 2 The TPS65162 has two integrated operational amplifiers. The operational amplifiers can be used as a gamma-correction buffer or as a VCOM buffer. AVIN POS2 OUT2 NEG2 POS1 2 OUT1 NEG1 1 3.3R 10nF Proper termination when not in use Series resistor for driving capacitive loads Figure 27. Operational Amplifier Block TPS65162 The power supply pin for the opamps is the AVIN pin connected to the boost converter Vs. To achieve good performance and minimize the output noise, a 1-µF bypass capacitor is required directly from the AVIN pin to ground. The opamps are not designed to drive capacitive loads, therefore it is not recommended to connect a capacitor directly to the output of the opamps. If capacitive loads are driven, use a series resistor at the output to provide stable operation. With a 3.3-Ω series resistor, a capacitive load of 10 nF can be driven, which is usually sufficient for typical LCD applications. Operational Amplifier Termination For some applications, not all of the amplifiers are used. To minimize device quiescent current the terminals should be terminated. The negative terminal is connected to the output of the operational amplifier and positive terminal is connected to GND and the output is left open. This termination minimizes device quiescent current and maintains correct functionality of the device. PCB LAYOUT DESIGN GUIDELINES 1. Place the power components outlined in bold first on the PCB. 2. Rout the traces outlined in bold with wide PCB traces. 3. Place a 1-µF bypass capacitor directly from the SUP pin to GND and from AVIN to GND. 26 Submit Documentation Feedback TPS65162 www.ti.com SLVS771 – MAY 2007 4. 5. 6. 7. Use a short and wide trace to connect the SUP pin to the output of the boost converter Vs. Place the 220-nF reference capacitor directly from REF to GND close to the IC pins. The feedback resistor for the negative charge pump between FBN and REF should be >40 kΩ. Use short traces for the charge-pump drive pin (DRVN) of VGL because the traces carry switching waveforms. 8. Solder the PowerPad™ of the QFN package to GND, and use thermal vias to lower the thermal resistance. 9. For more layout recommendations, refer to the TPS65162 evaluation module (EVM) L1 10 mH 27 C11 1 mF 30 C12 22 nF 31 C13 22 nF FB SWI VDD 3 VDPM DRVN SWB FBB R8 1.5 KΩ C20 100 nF 24 L2 10 mH 21 D5 DLY1 AGND POS1 NEG2 OUT2 POS2 DLY2 OUT1 C19 220 nF 47 R7 10 KΩ R10 1 KΩ FBN REF 48 2 1 44 46 45 34 35 GND VGH 25V/50mA Vs CBOOT 22 SWB 23 C17 470nF R6 3.3kΩ RE 7 PGND3 15 R5 62kΩ VC PGND2 R4 51 kW C16 470 nF VGHM 8 PGND1 17 D2D3 SS C18 470 nF 16 41 VGH 9 10 FBP NEG1 R3 200 kW 14 C10 22 mF 12 VIN OGND C7 470 nF D4D5 C9 22 uF DRVP 5 VFLK VFLK VGL -5 V/50 mA 6 C8 22 mF C7 220 pF R2 3.6 kΩ FREQ 28 CE C14 100 pF Enable Gate Voltage shaping R1 39 kΩ 13 32 EN2 28 Vs 15 V/1.5 A C12 1 mF 39 42 43 AVIN 38 SW 37 SWO EN1 26 SW 25 PVIN C4 22 mF 33 C11 1 mF C5 10 mF C2 22 mF PVIN C1 22 mF D1 SUP Vin 8 V to 14 V Vlogic 3.3 V/2.5 A C21 R11 2.4 kΩ 470 pF C22 22 mF C23 22mF 18 29 11 C24 10nF R12 1.5 kΩ C25 22nF 36 Figure 28. PCB Layout Recommendation TPS65162 Submit Documentation Feedback 27 TPS65162 www.ti.com SLVS771 – MAY 2007 TYPICAL APPLICATION L1 10 mH AVIN C8 C9 22 mF 22 mF C7 220 pF D2D3 DRVP S VGH C16 470 nF C17 470 nF R5 62 kW FBP SS C12 22 nF CE C14 100 pF Enable Gate Voltage shaping VDD VDPM SWB Buck Converter C18 470 nF FBB FBN R4 51 kW R8 1.5 KW C20 100 nF SWB S D DRVN L2 10 mH D5 Vlogic 3.3 V/2.5 A C21 R11 2.4 kW 470 pF REF DLY1 AGND PGND3 PGND2 PGND1 POS2 NEG2 C24 10 nF DLY2 2 POS1 OUT1 NEG1 OGND 1 OUT2 C19 220 nF VGH 25 V/50 mA R7 10 KW R10 1 KW CBOOT D4D5 R3 200 kW Vs RE VFLK VFLK R6 3.3 kW VGHM Gate Voltage Shaping VC C13 22 nF 28 R1 39 kW Vs 15 V/1.5 A C10 22 mF R2 3.6 kW D VIN C7 470 nF SWI SW SW FREQ C12 1 mF FB Boost Converter EN2 VGL -5V/50mA SWO EN1 PVIN C4 22 mF C11 1 mF C11 1 mF C5 10 mF C2 22 mF PVIN C1 22 mF D1 SUP Vin 8 V to 14 V GND Submit Documentation Feedback C25 22 nF R12 1.5 kW C22 22 mF C23 22 mF PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device TPS65162RGZR 29-May-2007 Package Pins RGZ 48 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) FRB 330 16 7.3 7.3 1.5 12 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TPS65162RGZR RGZ 48 FRB 342.9 336.6 28.58 Pack Materials-Page 2 W Pin1 (mm) Quadrant 16 Q2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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