TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Compact LCD Bias Supply for TFT-LCD TV Panels FEATURES APPLICATIONS • • • • • • • 1 2 • • • • • • • • • • • • • • 6 V to 14 V Input Voltage Range Vs Output Voltage Range up to 19 V Boost Converter With 3.5-A Switch Current Boost Converter Overvoltage Protection 2.5-A Step-Down Converter With 3.3-V Fixed or Adjustable Output 750 kHz Fixed Switching Frequency 150 mA Negative Charge Pump Driver for VGL 50 mA Positive Charge Pump for VGH LDO Controller for Logic Supply Gate Voltage Shaping for VGH Temperature Sensor Output TPS65167 - High Voltage Stress Test Vs and VGH TPS65167A - High Voltage Stress Test Vs only Adjustable Sequencing Gate Drive Signal for Isolation Switch Short-Circuit Protection Internal Soft-start Thermal Shutdown Available in 6 × 6 mm 40 Pin QFN Package TPS65167 12 V Boost Converter High-Voltage Stress Test Positive Charge Pump Gate Voltage Shaping Negative Charge Pump Temperature Sensor Vs 15 V/1.7 A VGH 30 V/50 mA LCD TV Panel LCD Monitor DESCRIPTION The TPS65167 offers a compact power supply solution to provide all voltages required by a LCD panel for large size monitor and TV panel applications running from a 12-V supply rail. The device generates all 3 voltage rails for the TFT LCD bias (Vs, VGL and VGH). In addition to that it includes a step-down converter and a LDO controller to provide two logic voltage rails. The device incorporates a high voltage switch that can be controlled by a logic signal from the external timing controller (TCON). This function allows gate voltage shaping for VGH. The device also features a high voltage stress test where the output voltage of VGH is set to typically 30 V and the output voltage of Vs is programmable to any higher voltage. The high voltage stress test is enabled by pulling the HVS pin high. The device consists of a boost converter to provide the source voltage Vs operating at a fixed switching frequency of 750 kHz. A fully integrated positive charge pump, switching automatically between doubler and tripler mode provides an adjustable regulated TFT gate on voltage VGH. A negative charge pump driver provides adjustable regulated output voltages VGL. To minimize external components the charge pumps for VGH and VGL operate at a fixed switching frequency of 1.5 MHz. The device includes safety features like overvoltage protection of the boost converter, short-circuit protection of VGH and VGL as well as thermal shutdown. VGL –5 V/150 mA Vtemp Buck Converter Vlogic 3.3 V/2.5 A LDO Controller Vaux 1.8 V/500 mA 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA High voltage Stress Test (HVS) ORDERING Available on Vs and VGH TPS65167RHAR Available on Vs only TPS65167ARHA R –40°C to 85°C (1) (2) PACKAGE (2) PACKAGE MARKING 40 pin QFN TPS65167A TPS65167 The RHA package is available taped and reeled. Add R suffix to the device type (TPS65167RHAR) to order the device taped and reeled. The RHA package has quantities of 3000 devices per reel. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) AVIN, VINB, SUPN, GD, BASE VI Voltage on pin (2) VALUE UNIT –0.3 to 16.5 V EN, HVS, CTRL(2) –0.3 to 6 V FB, FBB, FBP, FBN, FBLDO, RSET(2) –0.3 to 6 V SW, SUP 25 V SWB(2) 20 V POUT, VGH, DRN(2) 36 V (2) TJ Continuous power dissipation Tstg Operating junction temperature range –40 to 150 °C Storage temperature range –65 to 150 °C (1) (2) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) (1) PACKAGE RθJA TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING 40 pin QFN 30°C/W 3.3 W 1.8 W 1.3 W See the Texas Instruments Application report SLMA002 regarding thermal characteristics of the PowerPAD package. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VI Input voltage range 6 14 V TA Operating ambient temperature –40 85 °C TJ Operating junction temperature –40 125 °C 2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS AVIN=VINB=SUPN=12V, EN=REGOUT, Vs = 15V, Vlogic = 3.3V , Vaux = 1.8V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI IQ UVLO Input voltage range 6 14 Quiescent current into AVIN Not switching, FB = FB + 5% Quiescent current into VINB Quiescent current into SUP Undervoltage lockout threshold VI falling 4.7 5.2 5.7 Undervoltage lockout threshold VI rising 4.9 5.45 5.9 V 1.5 mA Not switching, FBB = FBB + 5% 0.15 mA Not switching, FB = FBB = FBN = FBP = + 5% 275 Thermal shutdown Thermal shutdown hysteresis µA V V 155 °C 5 °C REFERENCE VOLTAGE REF Vref VI = 6 V to 14 V, Iref = 10 µA Reference voltage 1.205 1.213 1.219 V LOGIC SIGNALS CTRL, HVS VIH High level input voltage 6 V ≤ VIN ≤ 14 V VIL Low level input voltage 6 V ≤ VIN ≤ 14 V Ilkg Input leakage current EN = CTRL = HVS = GND or 6 V 1.4 V 0.4 V 0.01 0.1 µA 4.8 6.2 µA SEQUENCING GDLY/EN EN/GDLY Charge current V(threshold) = 1.213 V 3.6 EN/GDLY threshold EN/GDLY pulldown resistor 1.23 V 4.5 kΩ SWITCHING FREQUENCY fs Switching frequency 600 750 900 kHz 4.6 4.8 5 V 19 V 1.136 1.146 1.154 V 10 100 nA REGULATOR REGOUT VO Regulator output voltage Ireg = 1 mA BOOST CONVERTER (Vs) VO Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current RDS(on) N-MOSFET on-resistance (Q1) I(SW) = 500 mA 160 270 mΩ P-MOSFET on-resistance (Q2) I(SW) = 200 mA 14 20 Ω 1 A IMAX Maximum P-MOSFET peak switch current ILIM N-MOSFET switch current limit (Q1) Ilkg Switch leakage current V(SW) = 15 V Line Regulation 6 V ≤ Vin ≤ 14 V, IO = 2 mA Load Regulation 2 mA ≤ Iout ≤ 1.8 A 3.5 4.2 4.9 A 1 10 µA 0.006 %/V 0.06 %/A BOOST CONVERTER (Vs) OVERVOLTAGE PROTECTION Switch overvoltage protection Vs rising 19.5 Switch overvoltage protection hysteresis 20.2 21 0.6 V V GATE DRIVE (GD) AND BOOST CONVERTER PROTECTION I(GD) Gate drive sink current R(GD) Gate drive internal pull up resistance ton Gate on time during short-circuit toff Gate off time during short-circuit 9 µA 5 kΩ Vs < 4.8 V 1 ms Vs < 4.8 V 60 ms EN = high TEMPERATURE SENSOR (TEMP) VO Output voltage range 1.2 Drive current VO Output voltage at TA = 85°C TA = 85°C, I = 200 µA, device not switching, FB = FBnominal + 5% Temperature accuracy V µA 2.037 –6 Temperature coefficient 2.5 200 V 6 5.7 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A °C mV/°C 3 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) AVIN=VINB=SUPN=12V, EN=REGOUT, Vs = 15V, Vlogic = 3.3V , Vaux = 1.8V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STEP-DOWN CONVERTER (Vlogic) Output voltage range 5 V 3.3V fixed output voltage accuracy FBB = GND –2% 3.3 2% V VFB Feedback regulation voltage FBB connected to resistor divider, –2% 1.213 2% V IFB Feedback input bias current 10 100 nA RDS(on) N-MOSFET on-resistance (Q1) 200 330 mΩ ILIM N-MOSFET switch current limit (Q1) 3.5 4.2 A Ilkg Switch leakage current V(SW) = 0 V 1 10 µA Line regulation 6 V ≤ Vin ≤ 14 V, IO = 1.8 mA Load regulation 1.8 mA ≤ IO ≤ 2.5 A VO 1.5 I(SW) = 500 mA 2.8 0.006 %/V 0.06 %/A STEP-DOWN CONVERTER FEEDBACK SELECT THRESHOLD FBB VFB Feedback select threshold Adjustable version select 0.25 V 14 V NEGATIVE CHARGE PUMP VGL VI Input supply range VO Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current RDS(on) Q4 P-Channel switch RDS(on) Current source voltage drop (1) 6 –36 –2 V 0 36 mV 10 100 nA IO = 20 mA 4.4 8 Ω I(DRVN) = 50 mA, V(FBN) = V(FBNnominal) –5% 120 I(DRVN) = 100 mA, V(FBN) = V(FBNnominal) –5% 235 mV Line regulation 9.5 V ≤ Vin ≤ 14 V, IO = 1 mA 0.098 %/V Load regulation 1 mA ≤ IO ≤ 100 mA, VGL = –5 V 0.055 %/mA POSITIVE CHARGE PUMP (POUT) VO Output voltage range VFB Feedback regulation voltage IFB Feedback input bias current 30 CTRL = GND, VGH = open 1.187 Doubler Mode (x2); I(POUT) = 20 mA Effective output resistance 1.238 V 10 100 nA 98 Doubler Mode (x2); I(POUT) = 50 mA 63 Tripler Mode (x3); I(POUT) = 20 mA Ω 143 Tripler Mode (x3); I(POUT) = 50 mA Load regulation V 1.214 91 1 mA ≤ Iout ≤ 51 mA, VGH = 23.9 V 0.0022 %/mA HIGH VOLTAGE SWITCH VGH RDS(on) I(DRN) POUT to VGH RDS(on) CTRL = high, POUT = 27 V, I = 20 mA 10 18 DRN to VGH RDS(on) CTRL = low, V(DRN) = 5 V, I = 20 mA 40 60 DRN input current CTRL = low, V(DRN) = 10 V tdly CTRL to VGH propagation delay R(VGH) VGH pull down resistance µA 10 CTRL = high to low, POUT = 27 V, V(DRN) = GND 120 CTRL= low to high, POUT = 27 V, V(DRN) = GND 140 EN = low, I = 20 mA Ω ns 1 kΩ LINEAR REGULATOR CONTROLLER Vaux VEB Emitter voltage range VFB Feedback regulation voltage I(BASE) Base sink current 2.3 –2% V(BASE) = 3.3 V-1V, VFBLDO = 1.15 V 25 V(BASE) = 2.5 V-1V, VFBLDO = 1.15 V 15 Power supply rejection ratio LDO input Line regulation 6V ≤ Vin ≤ 14 V, I(load) = 1 mA, Vaux = 1.6 V Load regulation 1 mA ≤ IO ≤ 500 mA, VI = 3.3 V, Vaux = 1.6 V 15 1.213 V 2% mA 65 dB 0.007 %/V 0.48 %/A HIGH VOLTAGE STRESS TEST (HVS), RHVS (1) 4 The maximum charge pump output current is half the drive current of the internal current source or sink Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) AVIN=VINB=SUPN=12V, EN=REGOUT, Vs = 15V, Vlogic = 3.3V , Vaux = 1.8V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER 37 36 35 TEMP 38 PGND 39 PGND 40 33 32 31 SW SW TPS65167A, TPS65167, HVS = low, V(RHVS) = 5 V GD RHVS leakage current GND TPS65167A, TPS65167, HVS = high, I(HVS) = 100 µA AVIN RHVS pull down resistance FBLDO TPS65167, HVS = high 34 MIN TYP MAX 29 30 31 V 450 650 850 Ω 100 nA VINB 1 30 COMP BOOT 2 29 FB SWB 3 28 RHVS SWB 4 27 HVS PGND 5 26 EN PGND 6 25 GDLY VLOGIC 7 24 CTRL FBB 8 23 DRN REGOUT 9 22 VGH 21 POUT 18 19 UNIT 20 FBP 17 SUP C1P 16 C2N 15 C2P 14 C1N 13 GND 12 DRVN 10 11 FBN REF Exposed Thermal Die (See NOTE) SUPN Ilkg TEST CONDITIONS Positive charge pump output voltage BASE V(POUT) NOTE: The thermally enhance PowerPAD is connected to GND. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION VINB 1 I Power input for the buck converter. BOOT 2 I This pin generates the gate drive voltage for the Buck converter. Connect a 100 nF from this pin to the switch pin of the step-down converter SWB. SWB 3, 4 O Switch pin of the step-down converter PGND 5 Power ground for the step-down converter PGND 6 Power ground for the negative charge pump VLOGIC 7 I Output sense of the step-down converter FBB 8 I Feedback pin of the step-down converter REGOUT 9 O Output of the internal 5V regulator. Connect a 1-µF bypass capacitor to this pin. REF 10 O Internal reference output typically 1.213 V FBN 11 I Feedback pin of negative charge pump SUPN 12 I Power supply pin for the negative charge pump driver. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 5 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. DRVN 13 GND 14 Power ground for the positive charge pump C1P 15 Positive charge pump flying capacitor C1N 16 Positive charge pump flying capacitor C2P 17 Positive charge pump flying capacitor C2N 18 Positive charge pump flying capacitor SUP 19 FBP 20 Feedback of the positive charge pump POUT 21 Output of the positive charge pump converter VGH 22 Output of the high voltage switch and gate shaping function block DRN 23 Termination of the low side switch of the gate voltage shaping block CTRL 24 I Control input for the gate voltage shaping block. Connect this pin to REGOUT if the gate voltage shaping function is not used. GDLY 25 O Connecting a capacitor from this pin to GND allows to set the delay time between the boost converter Vs and VGH. Note that VGH is controlled by CTRL as well. EN 26 I This is the enable pin of the boost converter Vs, negative charge pump VGL and positive charge pump POUT. This pin is a dual function pin. EN can be held high if no start-up delay is desired or a capacitor can be connected to this pin. The capacitor determines the start-up delay time. HVS 27 I Logic control input to force the device into High Voltage Stress Test. With HVS = low the high voltage stress test disabled. With the TPS65167 and HVS = high the high voltage stress test is enabled for Vs and for VGH. With the TPS65167A and HVS = high the high voltage stress test is enabled for Vs only. RHVS 28 I/O This resistor sets the voltage of the boost converter Vs when the High Voltage Stress test is enabled. (HVS = high). With HVS = high the RHVS pin is pulled to GND which sets the voltage for the boost converter during High Voltage Stress. When HVS is disabled (HVS = low) the RHVS pin is high impedance. FB 29 I COMP 30 I/O Compensation for the regulation loop of the boost converter generating Vs. Typically a 22 nF compensation capacitor is connected to this pin. TEMP 31 O This is the output of the internal device temperature sensor. The output voltage is proportional to the chip temperature. PGND 32, 33 SW 34, 35 I/O Switch pin of the boost converter generating Vs GD 36 I/O Gate drive. This pin controls the external isolation MOSFET GND 37 AVIN 38 I Analog input voltage of the device. Bypass this pin with a 0.47µF bypass capacitor FBLDO 39 I Feedback of the LDO controller BASE 40 I/O PowerPAD ™ 6 I/O I/O Drive pin of the negative charge pump. Power supply pin of the positive charge pump and control voltage for the boost regulator Vs. Connect this pin with a short and wide PCB trace to the output of the boots converter Feedback of the boost converter Vs Power Ground for the boost converter Vs Analog Ground for the internal reference BASE drive of the external pnp transistor. Analog GND for the internal reference Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 FUNCTIONAL BLOCK DIAGRAM Temperature Output C2 1nF L1 10uH 1 C2 1uF 38 5 26 C11 1uF SW SUPN SUP Boost Converter VINB Positive Charge Pump x2 and x3 Mode S C13 10nF C2N REGOUT Gate Voltage Shaping HVS 24 CTRL 11 VINB Step Down Converter FBN 10 14 37 PGND 6 32 33 20 C9 0.33 uF 17 C10 1uF 18 DRN 23 Vlogic 7 BOOT 2 SWB 4 SWB 3 FBLDO R4 300kW 21 22 FBB C1N PGND C1P R3 82kW 28 VGH 15 GND C20 0.33uF 16 R8 39kW DRVN Negative Charge SUPN Pump Driver BASE D4 R7 160kW 13 PGND C15 0.33uF GND C16 2.2uF D3 REF VGL -5V/150 mA FBP C2P EN 25 GDLY 27 C8 47 pF R2 30kW 29 POUT PGND COMP R1 365kW C7 22 uF FB RHVS D AVIN C6 22 uF 19 31 SUP 34 TEMP 35 9 C12 22nF 30 R6 0W GD 12 Vin 6V to 14 V Vs 15 V/1.5A C5 1uF C4 22 uF C3 10uF 36 C25 470 nF C1 22 uF C3 10 uF SW C24 1nF D1 C25 100 pF R5 16kW VGH 23 V/ 50 mA C14 100nF L2 10 uH Vlogic 3.3V/ 2.5A D2 C19 22 uF C18 22 uF 8 39 40 Vaux 1.5V/500mA Q1 C21 220nF C22 1uF R11 1.6kW R13 1kW C23 10uF R12 6.8kW Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 7 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS Table 1. Table of Graphs FIGURE Main Boost Converter (Vs) η Efficiency boost converter vs Load currents Figure 1 Softstart boost converter vs Load currents Figure 2 PWM operation at nominal load current Figure 3 PWM operation at light load current Figure 4 Overvoltage protection Figure 5 Short-circuit power down cycling Figure 6 Load transient response boost converter Figure 7 Step-Down Converter (Vlogic) η Efficiency buck converter vs Load currents Figure 8 PWM operation at nominal load current Figure 9 PWM operation at light load current Figure 10 Softstart buck converter Figure 11 Load transient response buck converter Figure 12 LDO Controller Vaux Load transient response LDO controller Figure 13 Negative Charge Pump Driver VGL vs Load current - doubler stage Figure 14 vs Load current Figure 15 vs Temperature Figure 16 Positive Charge Pump Driver VGH Temperature Sensor VTemp System Performance Gate voltage shaping VGH 8 Figure 17 Power up sequencing EN connected to REGOUT Figure 18 Power up sequencing External capacitor connected to EN Figure 19 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 EFFICIENCY BOOST CONVERTER (Vs) vs LOAD CURRENT SOFTSTART BOOST CONVERTER (Vs) vs LOAD CURRENT 100 Vsw 90 Efficiency - % 80 Vout VIN 70 60 VI = 12 V, VO = 15 V 50 Input Current 40 0 500 1000 1500 VI = 12 V, VO = 15 V, IO = 500 mA 2000 IO - Output Current - mA Figure 1. Figure 2. PWM OPERATION AT NOMINAL LOAD CURRENT PWM OPERATION AT LIGHT LOAD CURRENT Vsw Vsw Vout Vout VI = 12 V, VO = 15 V/50 mA Inductor Current Inductor Current VI = 12 V, VO = 15 V/1A Figure 3. Figure 4. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 9 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 OVER VOLTAGE PROTECTION SHORT-CIRCUIT POWER DOWN CYCLING Vsw Vout VI = 15 V, VO = shorted to GND, Peak current depends mainly on input power supply VI = 15 V, VO = 15 V/500 mA VOUT with 15 V Offset Vout Vsw Input Current Figure 5. Figure 6. LOAD TRANSIENT RESPONSE BOOST CONVERTER EFFICIENCY BUCK CONVERTER vs LOAD CURRENT 90 VI = 12 V, VO = 3.3 V 85 Vout VI = 12 V, VS = 15 V, 560 mA to 1.46 A Output Current Efficiency - % 80 75 70 65 60 55 50 0 1500 500 1000 IO - Output Current - mA Figure 7. 10 2000 Figure 8. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 PWM OPERATION AT NOMINAL LOAD CURRENT PWM OPERATION AT LIGHT LOAD CURRENT Vsw Vsw Vout Vout Inductor Current Inductor Current VI = 12 V, VO = 3.3 V/50 mA VI = 12 V, VO = 3.3 V/2.5 A Figure 9. Figure 10. SOFTSTART BUCK CONVERTER Vlogic LOAD TRANSIENT RESPONSE BUCK CONVERTER Vout Vsw Vout VI = 12 V, VS = 3.3 V, 3.3 V fixed output voltage 136 mA to 1.8 A VIN Input Current Output Current VI = 12 V, VO = 3.3 V fixed, IO = 500 mA Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 11 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 LOAD TRANSIENT RESPONSE LDO CONTROLLER VGL vs LOAD CURRENT -4.3 VGL = -5 V, VIN = 7 V, VIN = 7.5 V, VIN = 8 V -4.4 Vaux -4.5 -4.6 Cout = 22 mF, 50 mA to 530 mA Increasing VIN -4.7 VGL - V VI = 12 V, VS = 1.6 V, Output Current -4.8 -4.9 -5 -5.1 -5.2 0.091 0.081 0.071 0.061 0.051 0.041 0.031 0.021 0.011 0.001 -5.3 IO - Output Current - A Figure 13. Figure 14. VGH vs LOAD CURRENT – DOUBLER STAGE Vtemp vs TEMPERATURE 2.4 24 VS = 15 V, VGH = 24 V 23.8 2.3 2.2 23.6 2 23.2 TA = 85°C 23 TA = 25°C 22.8 Vtemp - V VGH - V Itemp = 200 mA, All Outputs no Load 2.1 TA = -40°C 23.4 VI = 12 V, 1.9 1.8 1.7 1.6 22.6 1.5 22.4 1.4 22.2 1.3 22 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 IO - Output Current - A 1.2 -40 -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - °C Figure 15. 12 140 Figure 16. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 GATE VOLTAGE SHAPING VGH POWER-UP SEQUENCING CTRL Vlogic Vaux VI = 12 V, GDLY = 10 nF EN = REGOUT Vs VGH VGH VGL DRN = 10 kW to VS, VGH = 470 pF Capacitive Load to Represent Panel 1 ms/div 4 ms/div Figure 17. Figure 18. POWER-UP SEQUENCING VI = 12 V, GDLY = 10 nF, EN = 22 nF to GND Vlogic Vaux Vs VGH VGL 2 ms/div Figure 19. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 13 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 APPLICATION INFORMATION TEMP 200 mA AVIN Temperature Sensor Vref 1.213V UVLO Undervoltage lockout 5.35V typ Regulator 4.8V typ REGOUT Start Buck Converter GND Thermal Shutdown latch 155oC typ 30 mA Start LDO Controller REF Control Start negative charge pump EN Ichg Vref EN AVIN 3.5k Start Boost converter, and positive charge 5k EN VREF Power Good Buck Converter GD Idischg Control EN Ichg GDLY Vref FBB Control Power Good Boost Converter FB Enable Gate voltage shaping block 3.5k EN Figure 20. Control Block TPS65167 Regulator REGOUT and Reference REF The 4.8-V regulator REGOUT and reference REF is always on as long as the input voltage is above the device undervoltage lockout of typically 5.2 V. The output of the internal regulator REGOUT requires a 1-µF output capacitor for regulation. The REF pin provides a reference output which is used to regulate the negative charge pump. In order to have a stable reference voltage, a 220-nF bypass capacitor is required, which needs to be connected directly from REF to GND (pin 37). The reference output has a current capability of 30 µA which must not be exceeded. Therefore, the feedback resistor value from FBN to REF must not be smaller than 40 kΩ. Temperature Sensor Output TEMP The device provides a temperature sensor output measuring the actual chip temperature. This pin has an analog output capable of driving 200 µA. The TEMP pin requires a 1-nF output capacitor to provide a stable output voltage. At 85°C, the typical output voltage is 2.037 V with a temperature coefficient of 5.9 mV/°C. See Figure 16 for the output characteristic of the temperature output. Thermal Shutdown A thermal shutdown is implemented to prevent damages due to excessive die temperatures. Once the thermal shutdown is exceeded, the device enters shutdown. The device can be enabled again by cycling the EN pin or input voltage to ground. 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Undervoltage Lockout To avoid mis-operation of the device at low input voltages an undervoltage lockout is included which shuts down the device at voltages lower than 5.2 V. Start-Up Sequencing The device has an adjustable start-up sequencing to provide correct sequencing as required by LCD. When the input voltage exceeds the undervoltage lockout threshold, then the step-down converter and LDO controller start-up at the same time. As the enable signal (EN) goes high, the negative charge pump starts up followed by the boost converter Vs starting at the same time as the positive charge pump. See the typical curves shown in Figure 18, Figure 19, and Figure 21. AVIN =UVLOVhys AVIN = UVLO VIN VLOGIC Vaux td VGH EN with CTRL=high POUT Vs VGL GDLY GD Figure 21. Power Up Sequencing Enable EN The enable is a dual function pin. It can be used as a standard enable pin that enables the device once it is pulled high by a logic signal or connected to the REGOUT pin. The enable can not be connected directly to Vin due to its maximum voltage rating! If no logic control signal is available, it is also possible to connect a capacitor to this pin to set the delay time td as shown in Figure 21 and Figure 19. Delay GDLY The capacitor connected to GDLY sets the delay time from the point when the boost converter Vs reaches its nominal value to the enable of the gate voltage shaping block. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 15 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Setting the Delay Times GDLY, EN delay Connecting an external capacitor to the GDLY and EN pin sets the delay time. To set the delay time, the external capacitor is charged with a constant current source of typically 5 µA. The delay time is terminated when the capacitor voltage has reached the threshold voltage of Vth = 1.230 V. The external delay capacitor is calculated: 5 mA x td 5 mA x td Cdly = = Vref 1.23 V (1) with td = Desired delay time Example for setting a delay time of 2.3 mS 5 mA x 2.3 ms Cdly = = 9.3 nF Þ Cdly = 10 nF 1.23 V (2) Boost Converter The main boost converter operates in Pulse Width Modulation (PWM) and at a fixed switching frequency of 750 kHz The converter uses a unique fast response, voltage mode controller scheme with input voltage feedforward. This achieves excellent line and load regulation (0.2% A load regulation typical) and allows the use of small external components. To add higher flexibility to the selection of external component values the device uses external loop compensation. Although the boost converter looks like a non-synchronous boost converter topology operating in discontinuous conduction mode at light load, the device will maintain continuous conduction even at light load currents. This is achieved with a novel architecture using an external Schottky diode with an integrated MOSFET in parallel connected between SW and SUP. See the Functional Block Diagram. The intention of this MOSFET is to allow the current to go below ground that occurs at light load conditions. For this purpose, a small integrated P-Channel MOSFET with typically 10 Ω RDS(on) is sufficient. When the inductor current is positive, the external Schottky diode with the lower forward voltage will carry the current. This causes the converter to operate with a fixed frequency in continuous conduction mode over the entire load current range. This avoids the ringing on the switch pin as seen with standard non-synchronous boost converter, and allows a simpler compensation for the boost converter. 16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 AVIN GD 5 kW IDLY SW SW IDLY Softstart Vref M2 SS 750kHz Oszillator 70 W SUP Current limit and Soft Start EN Comparator Control Logic M1 COMP GM Amplifier PGND Sawtooth Generator FB VFB 1.154V GM Amplifier Low Gain Overvoltage Comparator OVP SUP PGND Vref VFB 1.154 RHVS HVS Figure 22. Block Diagram Boost Converter Softstart (Boost Converter) The main boost converter has an internal softstart to prevent high inrush current during start-up. The device incorporates a digital softstart increasing the current limit in digital current limit steps. See Figure 2 for the typical softstart timing. High Voltage Stress Test (Boost converter and positive charge pump) The TPS65167 and TPS65167A incorporates a high voltage stress test where the output voltage of the boost converter Vs and the positive charge pump POUT is set to a higher voltage compared to the nominal programmed output voltage. The High Voltage Stress test is enabled by pulling the HVS pin to high. With HVS = high, the voltage on POUT, respectively VGH, remains unchanged with the TPS65167A and the TPS65167 regulates to a fixed output voltage of 30 V. The boost converter Vs is programmed to a higher voltage determined by the resistor connected to RHVS. With HVS = high the RHVS pin is pulled to GND which sets the voltage for the boost converter during the High Voltage Stress Test. The output voltage for the boost converter during high voltage stress test is calculated as: R1 + R2//R3 R1 + R2//R3 VsHVS = VFB = 1.146V R2//R3 R2//R3 R3 = R1 x R2 æ VsHSV ö - 1÷ x R2 - R1 ç V è FB ø (3) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 17 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 With: VsHVS = Boost converter output voltage with HVS = high VFB = 1.146 V Overvoltage Protection The main boost converter has an overvoltage protection of the main switch M1 if the feedback pin (FB) is floating or shorted to GND causing the output voltage to rise. In such an event, the output voltage is monitored with the overvoltage protection comparator on the SUP pin. As soon as the comparator trips at typically at 20 V then the boost converter stops switching. The output voltage will fall below the overvoltage threshold and the converter continues to operate. See Figure 4. Note: During high voltage stress test the overvoltage protection is disabled. Input Capacitor Selection VINB, SUP, SUPN, AVIN, Inductor Input Terminal For good input voltage filtering, low ESR ceramic capacitors are recommended. The TPS65167 has an analog input AVIN as well as a power supply input SUP powering all the internal rails. A 1-µF bypass capacitor is required as close as possible from AVIN to GND as well as from SUP to GND. The SUPN pin needs to be bypassed with a 470-nF capacitor. Depending on the overall load current two or three 22-µF input capacitors are required. For better input voltage filtering, the input capacitor values can be increased. To reduce the power losses across the external isolation switch a filter capacitance at the input terminal of the inductor is required. To minimize possible audible noise problems, two 10-µF capacitors in parallel are recommended. More capacitance will further reduce the ripple current across the isolation switch. See Table 2 and the typical applications for input capacitor recommendations. Table 2. Input Capacitor Selection CAPACITOR COMPONENT SUPPLIER COMMENTS 22 µF/16 V Taiyo Yuden EMK316BJ226ML Pin VINB 2 ×10 µF/25 V Taiyo Yuden TMK316BJ106KL Pin VINB (alternative) 2 ×10 µF/25 V Taiyo Yuden TMK316BJ106KL Inductor input terminal 1 µF/35 V Taiyo Yuden GMK107BJ105KA Pin SUP 1 µF/25 V Taiyo Yuden TMK107BJ105KA Pin AVIN 470 nF/25 V Taiyo Yuden TMK107BJ474MA Pin SUPN x Boost Converter Design Procedure The first step in the design procedure is to verify whether the maximum possible output current of the boost converter supports the specific application requirements. To simplify the calculation, the fastest approach is to estimate the converter efficiency by taking the efficiency numbers from the provided efficiency curves or to use a worst case assumption for the expected efficiency, e.g., 80%. With the efficiency number it is possible to calculate the steady state values of the application. Vin h D +1* Vout 1. Converter Duty Cycle: ǒ Ǔ Iout + Isw * Vin D 2 ƒs L 2. Maximum output current: I I swpeak + Vin D ) out 2 ƒs L 1 *D 3. Peak switch current: (1 * D) With Isw = converter switch current (minimum switch current limit = 3.5 A) fs = converter switching frequency (typical 750 kHz) L = Selected inductor value η = Estimated converter efficiency (use the number from the efficiency curves or 0.8 as an estimation) 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 The peak switch current is the steady state peak switch current the integrated switch, inductor and external Schottky diode has to be able to handle. The calculation must be done for the minimum input voltage where the peak switch current is highest. Note that the maximum output power of the device is limited by the power dissipation of the package. Inductor Selection (Boost Converter) The TPS65167 typically operates with a 10-µH inductor. Main parameter for the inductor selection is the saturation current of the inductor which should be higher than the peak switch current as calculated above with additional margin to cover for heavy load transients. The alternative more conservative approach is to choose the inductor with saturation current at least as high as the minimum switch current limit of 3.5 A. The second important parameter is the inductor dc resistance. The lower the dc resistance the higher the efficiency of the converter. The converter efficiency can vary between 2% to 10% when choosing different inductors. Possible inductors are shown in Table 3. Table 3. Inductor Selection Boost Converter INDUCTOR VALUE COMPONENT SUPPLIER DIMENSIONS in mm Isat/DCR 10 µH Sumida CDRH8D43-100 8.3 × 8.3 × 4.5 4 A/29 mΩ 10 µH Wuerth 744066100 10 × 10 × 3.8 4 A/25 mΩ 10 µH Coilcraft DO3316P-103 12.95 × 9.4 × 5.5 3.9 A/38 mΩ Output Capacitor Selection (Boost Converter) For best output voltage filtering, a low ESR output capacitor is recommended. Ceramic capacitors have a low ESR value and work best with the TPS65167. Three 22-µF or six 10-µF ceramic output capacitors in parallel are sufficient for most applications. More capacitors can be added to improve the load transient regulation. See Table 4 for the selection of the output capacitor. Table 4. Output Capacitor Selection CAPACITOR COMPONENT SUPPLIER 6 × 10 µF/25 V Taiyo Yuden TMK316BJ106KL 3 × 22 µF/25 V TDK C4532X7R1E226M COMMENTS Alternative solution Rectifier Diode Selection (Boost Converter) To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the converter. The current rating for the Schottky diode is calculated as the off time of the converter times the peak switch current of the application. The minimum switch current of the converter can be used as a worst case calculation. Vin Iavg = (1 - D ) x Isw = x 3.5 A Vout with Isw=minimum switch current of the TPS65167 (3.5 A) Usually a Schottky diode with 2 A maximum average rectified forward current rating is sufficient for most of the applications. Secondly, the Schottky rectifier has to be able to dissipate the power. The dissipated power is the average rectified forward current times the diode forward voltage. P D + I avg VF + Isw (1 * D) VF + I sw + Vin VF Vout with Isw = minimum switch current of 3.5 A (worst case calculation) Table 5. Rectifier Diode Selection (Boost Converter) Avg. Or Vforward RθJA SIZE COMPONENT SUPPLIER 3A 20 V 0.36 at 3 A 46°C/W S.C. MBRS320, International Rectifier 2A 20 V 0.44 V at 2 A 75°C/W SMB SL22, Vishay Semiconductor 2A 20 V 0.5 at 2 A 75°C/W SMB SS22, Fairchild Semiconductor Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 19 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Setting the Output Voltage and Selecting the Feedforward Capacitor (Boost Converter) The output voltage is set by the external resistor divider and is calculated as: V out + 1.146 V ǒ1 ) R1 Ǔ R2 (4) Across the upper resistor a bypass capacitor is required to speed up the circuit during load transients. The capacitor is calculated as: 1 1 C8 + + 2 p ƒ z R1 2 p 10000 R1 (5) A value coming closest to the calculated value should be used. Compensation (COMP) The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The COMP pin is the output of the internal transconductance error amplifier. A single capacitor connected to this pin sets the low frequency gain. A 22-nF capacitor is sufficient for most of the applications. Adding a series resistor sets an additional zero and increases the high frequency gain. The formula below calculates at what frequency the resistor will increase the high frequency gain. 1 ƒz + 2 p C12 R6 (6) Lower input voltages require a higher gain and; therefore, a lower compensation capacitor value. See the typical applications for the appropriate component selection. Gate Drive Pin (GD) and Isolation Switch Selection The external isolation switch disconnects the output of the boost converter once the device is turned off. The external isolation switch also provides a short-circuit protection of Vs by turning off the switch in case of a short-circuit. The Gate Drive (GD) allows control of an external isolation MOSFET switch. GD pin is pulled low when the input voltage is above the undervoltage lockout threshold (UVLO) and when enable (EN) is high. The gate drive has an internal pull up resistor to AVIN of typically 5 kΩ. In order to minimize inrush current during start-up, the gate drive pin is pulled low by an internal 10µA current sink. To further reduce this inrush current, typically a 1-nF capacitor can be connected from pin GD to the boost converter inductor. A standard P-Channel MOSFET with a current rating close to the minimum boost converter switch current limit of 3.5 A is sufficient. Table 6 shows two examples coming in a small SOT23 package. The worst case power dissipation of the isolation switch is calculated as the minimum switch current limit × RDS(on) of the MOSFET. A standard SOT23 package or similar is able to provide sufficient power dissipation. Table 6. Isolation Switch Selection COMPONENT SUPPLIER CURRENT RATING International Rectifier IRLML5203 3A Siliconix SI2343 3.1 A Step-Down Converter The non-synchronous step-down converter operates at a fixed switching frequency using a fast response voltage mode topology with input voltage feedforward. This topology allows simple internal compensation and it is designed to operate with ceramic output capacitors. The converter drives an internal 2.8-A N-Channel MOSFET switch. The MOSFET driver is referenced to the switch pin SWB. The N-Channel MOSFET requires a gate drive voltage higher than the switch pin to turn the N-Channel MOSFET on. This is accomplished by a boost strap gate drive circuit running of the step-down converter switch pin. When the switch pin SWB is at ground, the boot strap capacitor is charged to 8 V. This way the N-Channel Gate drive voltage is typically around 8 V. 20 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Regulator 8V VINB BOOT Q3 VINB SWB Control Logic SWB Current limit Vref Error Amplifier Vref FBB Vref Compensation and Softstart Vlogic select Fixed 3.3V/adj Sawtooth Generator Fixed 3.3V Clock /2 Logic 0.9V Clock /4 Clock 0.6V Clock 750 kHz Clock select for short circuit and softstart Figure 23. Block Diagram Buck Converter Soft-start (Step-Down Converter) To avoid high inrush current during start-up, an internal soft-start is implemented. When the step-down converter is enabled, its reference voltage slowly rises from zero to its power good threshold of typically 90% of Vref. When the reference voltage reaches this power good threshold, the error amplifier is released to its normal operation with its normal duty cycle. To further limit the inrush current during soft-start, the converter frequency is set to 1/4th of the switching frequency fs and of fs determined by the comparator that monitors the feedback voltage. See the internal block diagram. The softstart is typically completed within 1 ms. Setting the Output Voltage, Adjustable or Fixed 3.3V (step-down converter) The device supports a fixed 3.3-V output voltage when the feedback FBB is connected to GND. When using the external voltage divider any other output voltage can be programmed. To set the adjustable output voltage of the step-down converter, use an external voltage divider to set the output voltage. The output voltage is calculated as: V out + 1.213 V R9 Ǔ ǒ1 ) R10 (7) with R10 ≈ 1.2 kΩ and internal reference voltage V(ref)typ = 1.213 V At load currents < 1 mA, the device operates in discontinuous conduction mode. When the load current is reduced to zero, the output voltage rises slightly above the nominal output voltage. At zero load current, the device skips clock cycles but does not completely stops switching thus the output voltage sits slightly above the nominal output voltage. Therefore, the lower feedback resistor is selected to be around 1.2 kΩ to have always around 1 mA minimum load current. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 21 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Selecting the Feedforward Capacitor (step-down converter) The feedforward capacitor across the upper feedback resistor divider form a zero around 170 kHz and is calculated as: 1 1 C17 = = = 468 pF = 470 pF 2 x p x 170kHz x R9 2 x p x 170kHz x 2k (8) The capacitor value closest to the calculated value is selected. Inductor Selection (step-down converter) The TPS65167 operates typically with a 10-µH inductor value. For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. This needs to be considered when selecting the appropriate inductor. To avoid saturation of the inductor, the inductor should be rated at least for the maximum output current of the converter plus the inductor ripple current that will be calculated as: 1 * Vout DI Vin DI L + Vout I Lmax + I outmax ) L 2 L ƒ (9) With: f = Switching Frequency (750 kHz) L = Inductor Value (typically 10 µH) ΔIL= Peak to Peak inductor ripple current ILax = Maximum Inductor current The highest inductor current occurs at maximum Vin. A more conservative approach is to select the inductor current rating just for the minimum switch current limit of 2.8 A. Table 7. Inductor Selection (Step down converter) INDUCTOR VALUE COMPONENT SUPPLIER DIMENSIONS in mm Sat/DCR 10 µH Sumida CDRH8D43-100 8.3 × 8.3 × 4.5 4 A/29 mΩ 10 µH Wuerth 744066100 10 × 10 × 3.8 4 A/25 mΩ 10 µH Coilcraft DO3316P-103 12.95 × 9.4 × 5.51 3.9 A/38 mΩ Rectifier Diode Selection (step-down converter) To achieve high efficiency, a Schottky diode should be used. The reverse voltage rating should be higher than the maximum output voltage of the step-down converter. The averaged rectified forward current that the Schottky diode must be rated is calculated as the off time of the step-down converter times the minimum switch current of the TPS65167: D + Vout Vin (10) I avg + (1 * D) Isw + 1 * Vout Vin 2.8 A with Isw = minimum switch current of the TPS65167 (2.8 A) A Schottky diode with 2 A maximum average rectified forward current rating is sufficient for most of the applications. The Schottky rectifier has to be able to dissipate the power. The dissipated power is the average rectified forward current times the diode forward voltage. P D + I avg VF + Isw (1 * D) VF with Isw = minimum switch current of the TPS65167 (2.8 A) Table 8. Rectifier Diode Selection step-down Converter 22 CURRENT RATING Avg. Or Vforward RθJA SIZE COMPONENT SUPPLIER 3A 20V 0.36 at 3A 46°C/W S.C. MBRS320, International Rectifier 2A 20V 0.44V at 2A 75°C/W SMB SL22, Vishay Semiconductor 2A 20V 0.5 at 2A 75°C/W SMB SS22, Fairchild Semiconductor Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Output Capacitor Selection (step-down converter) The device is designed to work with ceramic output capacitors. Two 22-µF output capacitors are sufficient for most of the applications. Larger output capacitance improves the load transient response. Table 9. Output Capacitor Selection step-down Converter CAPACITOR VOLTAGE RATING COMPONENT SUPPLIER 2 × 22 µF/6.3 V 6.3 V Taiyo Yuden JMK212BJ226MG Positive Charge Pump The positive charge pump is a fully integrated charge pump switching automatically its gain between doubler and tripler mode. As shown in Figure 24, the input voltage of the positive charge pump is the SUP pin, that is connected to the output of the main boost converter Vs. FBP OSC 750kHz SUP IDRVP Control Logic Automatic Gain select (doubler or tripler mode) Vref 1.213 V C1N Q4 C1P Softstart Q6 SUP = Vs POUT D3 Q3 D0 D1 C2P D2 Q5 C2N PGND Figure 24. Positive Charge Pump Block Diagram The charge pump requires two 330-nF flying capacitors and a 1µF output capacitance for stable operation. The positive charge pump also supports a high voltage stress test by pulling the HVS pin high. This programs the output voltage to a fixed output voltage of 30 V by using the internal voltage divider as shown in the block diagram. During normal operation the HVS pin is pulled low and the output voltage is programmed with the external voltage divider. V out + 1.213 V R4 + R5 ǒ ǒ1 ) R4 Ǔ R5 Ǔ Vout * 1 + R5 V FB (11) ǒ Ǔ Vout *1 1.213 (12) To minimize noise and leakage current sensitivity, keeping the lower feedback divider resistor R5 in the 20 kΩ range is recommended. A 100-pF feedforward capacitor across the upper feedback resistor R4 is typically required. For the capacitor selection, see Table 10. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 23 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Table 10. Output Capacitor Selection Positive Charge Pump CAPACITOR COMPONENT SUPPLIER COMMENT 330 nF/35 V Taiyo Yuden GMK212BJ334KG Flying capacitor C9, C20 1 µF/35 V Taiyo Yuden GMK107BJ105KA Output capacitor on POUT High Voltage Switch Control (Gate Voltage Shaping) The output voltage of the TPS65167A remains unchanged with HVS=high. The TPS65167 has a high voltage switch integrated to provide gate voltage modulation of VGH. If this feature is not required, then the CTRL pin has to be pulled high or connected to VIN. When the device is disabled or the input voltage is below the undervoltage lockout (UVLO), then both switches Q4 and Q5 are off, and VGH is discharge by a 1-kΩ resistor over Q8, as shown in Figure 25. FB Power Good FBP Power Good FBN Power Good UVLO EN POUT CTRL Vref GDLY 3.5kW Q4 I DLY EN VGH Control Voltage clamp 5.8V max CTRL = high Q4 on Q5 off CTRL = low Q4 off Q5 on EN = low Q4 and Q5 off, Q8 on 1kW Q5 AVIN Q8 DRN Vs Vs R13 10kW R11 10kW R10 1 kW Option 1 R12 10kW Option 2 Option 3 Figure 25. High Voltage Switch (Gate Voltage Shaping) Block TPS65167 To implement gate voltage shaping, the control signal from the LCD timing controller (TCON) is connected to CTRL. The CTRL pin is activated once the device is enabled, the input voltage is above the under voltage lockout, all the output voltages (Vs, VGL, VGH) are in regulation and the delay time set by the GDLY pin passed by. As soon as one of the outputs is pulled below its Power Good level, Q4 and Q5 are turned off, and VGH is discharged via a 1-kΩ resistor over Q8. 24 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 With CTRL=high, Q4 is turned on, and the charge pump output voltage is present at VGH. When the CTRL pin is pulled low, then Q4 is turned off, and Q5 is turned on discharging VGH. The slope and time for discharging VGH is determined by the LC Display capacitance and the termination on DRN. It is not required or recommended to connect an additional output capacitor on VGH. There are three options available to terminate the DRN pin. The chosen solution depends mainly on the LC Display capacitance and required overall converter efficiency. td VH VGH VL CTRL T Timing: 1. td is set by the capacitor CE 2.The slope is set by the resistor RE 3. VL is set by the voltage applied to VD Figure 26. High Voltage Switch (Gate Voltage Shaping) Timing Diagram Option 1 in Figure 25 discharges VGH to Vs. The lower the resistor the faster the discharge. Option 3 in Figure 25 constantly draws current from Vs due to the voltage divider connected to Vs. The advantage of this solution is that the low level voltage VL is given by the voltage divider assuming the feedback resistor values are small and allow to discharge the LC Display capacitance during the time, toff. Therefore, the solution is not recommended for large display panels since the feedback divider resistors needs to be selected too low which draws too much current from Vs. Option 2 does not draw any current from Vs and; therefore, is better in terms of converter efficiency. The voltage level VL where VGH is discharge to is determined by the LC Display capacitance, the resistor connected to DRN and the off time, toff. The lower the resistor value connected to DRN the lower the discharge voltage level VL. Adding any additional output capacitance to VGH is not recommend. If more capacitance is required, it needs to be added to POUT instead. High Voltage Stress Test (positive charge pump) The TPS65167 incorporates a high voltage stress test where the output voltage of the boost converter Vs and the positive charge pump POUT are set to a higher output voltage compared to the nominal programmed output voltage. The High Voltage Stress test is enabled by pulling HVS pin to high. This sets POUT, respectively VGH to 30 V, and the output voltage of the boost converter Vs is programmed to a higher voltage determined by the resistor connected to RHVS. With HVS = high, the RHVS pin is pulled to GND which sets the voltage for the boost converter during High Voltage Stress. Negative Charge Pump Driver The negative charge pump provides a regulated output voltage set by the external resistor divider. The negative charge pump inverts the input voltage applied to the SUPN pin and regulates it to the programmed voltage. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 25 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 SUPN OSC 750kHz Control Logic Softstart Q7 DRVN IDRVN PGND FBN Vref 0V Figure 27. Negative Charge Pump Block TPS65167 The output voltage is VGL = (–Vin) + Vdrop. Vdrop is the voltage drop across the external diodes and internal charge pump MOSFETs. Setting the output voltage: V out + *VREF R7 + *1.213 V R8 |Vout| |V out| R7 + R8 + R8 1.213 V REF R7 R8 (13) (14) Since the reference output driver current should typically not exceed 30 µA, the lower feedback resistor value R8 should be in a range of 40 kΩ to 120 kΩ. The negative charge pump requires two external Schottky diodes. The peak current rating of the Schottky diode has to be twice the load current of the output. For the external component selection refer to Table 11. For a 20-mA output current, the dual Schottky diode BAV99 or BAT54 is recommended. Table 11. Capacitor Selection CAPACITOR COMPONENT SUPPLIER COMMENT 330 nF/35 V Taiyo Yuden GMK212BJ334KG Flying capacitor C15 2.2 µF/10 V Taiyo Yuden LMK107BJ225KA Output capacitor on VGL BAV99/BAT54 Any Dual Schottky diode LDO Controller Generating Vaux The TPS65167 has a LDO controller using an external pass transistor. The input of the LDO controller can be the 12-V power supply input or the output of the 3.3-V logic rail, as generated by the step-down converter. The LDO controller is connected to the 3.3-V rail in order to minimize power losses across the external pass transistor. 26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 FBLDO PGND 5 39 BASE 40 Q2 PZT2907A Vlogic 3.3V R14* 100 W C22 1m F Vaux 1.5V/500mA R11 1.6kW C23 22mF R13 1kW R12 6.8kW *Optional Figure 28. LDO Controller Block TPS65167 Setting the output voltage, LDO controller The output voltage is set by the external resistor divider and is calculated as: V out + 1.213 V ǒ1 ) R11 Ǔ R12 (15) Input Capacitor and Output Capacitor Selection, LDO Controller For input voltage filtering, a 1-µF input capacitor is sufficient. The output requires a least one 10-µF output capacitor for stability for load currents up to 300-mA. For load currents larger 300 mA, one 22-µF output capacitor is required. See Table 12 for the capacitor selection. Table 12. Output Capacitor Selection CAPACITOR Iout 1 µF/10 V COMPONENT SUPPLIER COMMENT Taiyo Yuden LMK107BJ105KK Input capacitor 10 µF/10 V ≤300 mA Taiyo Yuden LMK212BJ106KG Output capacitor 22 µF/10 V >300 mA Taiyo Yuden LMK212BJ226MG Output capacitor Base and Emitter Base Resistor Selection A 1-kΩ resistor (R13) is required across the emitter base of the external transistor. To limit the current into the base during a short-circuit event, a 100-Ω base resistor (R4) is required when the input is connected to the 3.3-V rail. If the input is connected to the 12-V rail, then a 1-kΩ (R4) resistor is required. R4 is optional and protects the TPS65167 in case of a short-circuit event at the output of the LDO controller. External Transistor Selection The external transistor is selected based on the required output current and collector saturation voltage. The maximum collector saturation voltage is only important as the output voltage is close to the input voltage. This is the case for a 3.3 V to 2.5 V conversion where the collector saturation voltage of the external transistor is lower than 800 mV. To use low cost external transistors, the TPS65167 provides a minimum base drive current of 25 mA. The other important parameter is the maximum power dissipation the external transistor must be able to handle. The power dissipation is the output current times the input to output voltage difference. See Table 13 for the transistor selection Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 27 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Table 13. Transistor Selection CAPACITOR Iout COMPONENT SUPPLIER COMMENT PZT2907A 500 mA Any 3.3 V to ≤2.5 V conversion at 150 mA 3.3 V to ≤1.6 V conversion at 500 mA BCP52 1A Any 3.3 V to ≤2.5 V conversion BCP69 1A Any 3.3 V to ≤2.5 V conversion PCB Layout Design Guidelines Temperature Output C2 1nF 31 1 38 5 D4 11 C20 0.33mF 15 16 VGH TPS65167 GDLY DRN HVS Vlogic CTRL BOOT DRVN SWB FBN SWB C1P FBB C1N 10 14 37 6 32 33 BASE R8 39kW 13 COMP PGND R7 160kW C15 0.33mF C2N REGOUT PGND 24 D3 C2P PGND 25 27 CTRL Signal POUT GND 9 C13 10nF FBP EN C12 22nF 30 R6 0W AVIN PGND 26 C11 1mF RHVS GND C1 22mF FB VINB REF C2 1mF C6 10mF C7 10mF R1 365kW 19 S UP SW GD 34 SUPN Vin 6 V to 14V C16 2.2mF 35 36 12 TEMP C28 470nF C5 1mF C4 10mF C24 10mF C3 10mF Vs 15 V/1.5 A SW C24 1nF VGL -5 V/150mA D1 SL22 L1 10mH Q1 SI2343 FBLDO R2 30kW 29 28 C8 47pF C25 C26 C27 10mF 10mF 10mF R3 82kW 20 R4 300kW 21 C9 0.33mF 17 C10 1mF 18 R5 16kW C25 100pF VGH 24 V/50 mA 22 R14 1kW 23 7 C14 100nF 2 L2 10mH 4 3 D2 SL22 8 Vlogic 3.3V/2.5A C18 22mF C19 22mF 39 40 C21 220nF Q2 PZT2907A R16 100kW C22 1mF Vaux 1.5V/500mA R11 1.6kW R13 1kW C23 22mF R12 6.8kW Figure 29. PCB Layout 1. 2. 3. 4. 5. 6. 7. 8. 28 Place the power components outlined in bold first on the PCB. Route the traces outlined in bold with wide PCB traces. Place a 1-µF bypass capacitor directly from the SUP pin to GND and from AVIN to GND. Use a short and wide trace to connect the SUP pin to the output of the boost converter Vs. Place a 470-nF bypass capacitor directly from the SUPN pin to GND. Place the 220-nF reference capacitor directly from REF to GND close to the IC pins. The feedback resistor for the negative charge pump between FBN and REF needs to be >40 kΩ. Use short traces for the charge pump drive pin (DRVN) of VGL because the traces carry switching waveforms. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 9. Place the feedback resistors of the negative charge pump away from the DRVN trace to minimize coupling 10. Place the flying capacitors as close as possible to the C1P, C1N and C2P, C2N pin. 11. Solder the PowerPad™ of the QFN package to GND and use thermal vias to lower the thermal resistance. 12. A solid PCB ground structure is essential for good device performance. The power pad is the analog ground connected to the internal reference Pin 32, 33 are the power grounds for the boost converter Vs Pin 5 is the power ground for the step-down converter Vlogic and internal digital circuit Pin 6 is the power ground for the negative charge pump VGL Pin 14 is the power ground for the positive charge pump POUT Pin 37 is the analog ground for the internal reference 13. For more layout recommendations, see the TPS65167 evaluation module (EVM) TYPICAL APPLICATION Temperature Output 1 C2 1uF 38 5 26 C11 1uF 9 C12 22nF 30 C13 10nF 25 27 CTRL Signal 24 C15 0.33uF D4 SUP TEMP POUT EN C2P C2N REGOUT VGH TPS65167 GDLY DRN HVS Vlogic CTRL BOOT DRVN SWB FBN SWB C1P FBB 11 15 16 C1N 10 14 37 6 32 33 BASE C20 0.33uF PGND R8 39kW PGND PGND R7 160kW FBP PGND C16 2.2uF 13 AVIN GND D3 VGL -5V/150mA FB RHVS COMP C6 22uF C8 47pF R1 365kW C7 22uF 19 31 VINB GND R6 0W 34 SUPN REF C1 22uF 35 SW 12 Vin 6V to 14V GD 36 C25 470nF Vs 15V/1.7A C5 1uF C4 22uF C24 10uF SW C3 10uF C24 1nF C2 1nF D1 SL22 L1 10uH Q1 SI2343 FBLDO R2 30kW 29 R3 82kW 28 20 R4 300kW 21 C9 0.33uF 17 C10 1uF 18 C25 100pF R5 16kW VGH 24V/50mA 22 R14 1kW 23 7 C14 100nF 2 L2 10uH 4 D2 SL22 3 8 R9 2kW Vlogic 3.3V/ 2.5A C17 470nF C18 22uF C19 22uF R10 1.2kW 39 40 C21 220nF Q2 PZT2907A C22 1uF Vaux 1.5V/500mA R11 1.6kW R13 1kW C23 22uF R12 6.8kW Figure 30. Typical Application with adjustable step down converter Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 29 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Temperature Output 1 C2 1uF 38 5 26 C11 1uF 9 C12 22nF 30 C13 10nF 25 27 CTRL Signal 24 C15 0.33uF D4 TEMP POUT EN C2P C2N REGOUT VGH TPS65167 GDLY DRN HVS Vlogic CTRL BOOT DRVN SWB FBN SWB C1P FBB 11 15 C1N 10 14 37 6 32 33 BASE 16 PGND C20 0.33uF PGND R8 39kW PGND PGND R7 160kW 13 FBP GND D3 FB AVIN COMP C6 10uF R1 365kW C7 10uF 19 RHVS GND R6 0W 31 VINB REF C1 22uF C16 2.2uF SW GD SUPN Vin 6V to 14V 34 35 36 12 VGL –5V/150mA C4 10uF C24 10uF SW C28 470nF C5 1uF SUP C3 10uF C24 1nF C2 1nF D1 SL22 L1 10uH Q1 SI2343 FBLDO Vs 15V/1.7A C8 47pF C25 10uF C26 10uF C27 10uF R2 30kW 29 R3 82kW 28 20 R4 300kW 21 C9 0.33uF 17 C10 1uF 18 R5 16kW C25 100pF VGH 24V/50mA 22 R14 1kW 23 7 C14 100nF 2 L2 10uH 4 3 D2 SL22 8 Vlogic 3.3V/2.5A C18 22uF C19 22uF 39 40 C21 220nF Q2 PZT2907A R16 100W C22 1uF Vaux 1.5V/500mA R11 1.6kW R13 1kW C23 22uF R12 6.8kW Figure 31. Typical Application With 3.3V Fixed Output Voltage Step Down Converter 30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Temperature Output 1 C2 1uF 38 5 26 C11 1uF 9 C12 22nF 30 C13 10nF 25 27 CTRL Signal 24 C15 0.33uF 13 D4 TEMP POUT EN C2P C2N REGOUT VGH TPS65167 GDLY DRN HVS Vlogic CTRL BOOT DRVN SWB FBN SWB C1P FBB 11 15 C1N 10 14 37 6 32 33 BASE 16 PGND C20 0.33uF PGND R8 39kW PGND PGND R7 160kW FBP GND D3 FB AVIN COMP C6 10uF R1 365kW C7 10uF 19 RHVS GND R6 0W 31 VINB REF C1 22uF C16 2.2uF SW GD SUPN Vin 6V to 14V 34 35 36 12 VGL –5V/150mA C4 10uF C24 10uF SW C28 470nF C5 1uF SUP C3 10uF C24 1nF C2 1nF D1 SL22 L1 10uH Q1 SI2343 FBLDO Vs 15V/1.7A C8 47pF C25 10uF C26 10uF C27 10uF R2 30kW 29 R3 82kW 28 20 R4 300kW 21 C9 0.33uF 17 C10 1uF 18 R5 16kW C25 100pF VGH 24V/50mA 22 R14 1kW 23 7 C14 100nF 2 L2 10uH 4 3 D2 SL22 8 Vlogic 3.3V/2.5A C18 22uF C19 22uF 39 40 C21 220nF Q2 PZT2907A R16 100W C22 1uF Vaux 1.5V/500mA R11 1.6kW R13 1kW C23 22uF R12 6.8kW Figure 32. Typical Application With 1.2V LDO Controller Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A 31 TPS65167 TPS65167A www.ti.com SLVS760B – APRIL 2007 – REVISED OCTOBER 2007 Temperature Output 1 C2 1uF 38 5 26 C11 1uF 9 C12 22nF 30 C13 10nF 25 27 CTRL Signal C15 0.33uF D4 SW VGH COMP DRN GDLY HVS Vlogic CTRL BOOT DRVN SWB 11 FBN SWB C1P FBB 15 16 C1N 10 14 37 6 32 33 BASE C20 0.33uF 28 FBLDO C28 10uF R2 30kW R3 82kW R15 200kW 20 R4 300kW C9 0.33uF 17 C10 1uF 18 C25 100pF R5 16kW 22 VGH 24V/50mA R14 1kW TPS65167 PGND R8 39kW C2N REGOUT PGND R7 160kW 13 C2P C25 C26 C27 10uF 10uF 10uF 29 POUT EN C8 47pF R1 365kW C7 10uF 21 PGND D3 FB FBP AVIN PGND GND C16 2.2uF 24 C6 10uF Vs 15V/1.5A C29 100nF RHVS GND VGL -5V/150mA Q1 SI2304 19 VINB REF R6 0W SUPN 31 34 TEMP Vin 6V to 14V 35 GD 36 12 C1 22uF C24 10uF SW C28 470nF C5 1uF C4 10uF SUP C3 10uF C2 1nF D1 SL22 L1 10uH 23 7 2 C14 100nF L2 10uH 4 3 Vlogic 3.3V/2.5A D2 SL22 C18 22uF 8 C19 22uF 39 40 C21 220nF Q2 PZT2907A R16 100W C22 1uF Vaux 1.5V/500mA R11 1.6kW R13 1kW C23 22uF R12 6.8kW Figure 33. Typical Application Using Isolation Switch at the Output of the Boost Converter 32 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS65167 TPS65167A PACKAGE OPTION ADDENDUM www.ti.com 19-Nov-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS65167ARHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65167ARHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65167RHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65167RHARG4 ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65167RHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65167RHATG4 ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65167ARHAR RHA 40 SITE 41 330 16 6.3 6.3 1.5 12 16 Q2 TPS65167RHAT RHA 40 SITE 28 330 16 6.3 6.3 1.5 12 16 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2007 Device Package Pins Site Length (mm) Width (mm) TPS65167ARHAR RHA 40 SITE 41 346.0 346.0 33.0 TPS65167RHAT RHA 40 SITE 28 342.9 336.6 28.58 Pack Materials-Page 2 Height (mm) IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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