EMIF06-SD03F3 6-line IPAD™, EMI filter and ESD protection for SD card Features ■ ESD protection (IEC standard) ■ EMI Filtering ■ Level translator ■ Signal conditionning ■ Integrated power supply with: – Thermal shutdown (TSD) – Under voltage lockout (UVLO) – Short-circuit current limitation (ISC) – Power on/off feature with Enable pin Flip Chip (24 bumps) Benefits Figure 1. Pin configuration (bump side) ■ EMI Low-pass-filter and ESD protection (up to 15 kV on external pins) ■ Integrated pull up resistors prevent bus floating A ■ 50 MHz clock frequency compatible with Cline< 40 pF B ■ Lead-free package in 400 µm pitch C ■ Low power consumption ■ Very low PCB space consumption ■ High reliability offered by monolithic integration ■ Reduction of parasitic elements thanks to CSP integration 5 4 3 2 1 D E Complies with the following standards: Applications ■ IEC 61000-4-2, Level 4: External pins – 15 kV (air discharge) – 8 kV (contact discharge) ■ Removable memory cards in mobile phones, communication systems, and portable applications ■ HBM IEC 61340-3-1: All pins – 2 kV (air discharge) – 2 kV (contact discharge) ■ Memory cards compliant with: SD (standard and high speed), MiniSD, µSD and MMC/Trans-flash standards Description TM: IPAD is a trademark of STMicroelectronics. February 2010 The EMIF06-SD03F3 is a highly integrated device, based on IPAD technology, combining the 5 functions described under Features. Doc ID 15194 Rev 2 1/23 www.st.com 23 Contents EMIF06-SD03F3 Contents 1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Passive integration and low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 4.1 Test circuit from host to SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 Test circuit from SD to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Measurement of tskew (host to SD) from rising edge CLK.h . . . . . . . . . . . 12 4.4 Measurement of tskew.f (read mode) from rising edge CLK.h . . . . . . . . . . 13 Low drop out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Line regulation and transient line regulation . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 Load regulation and transient load regulation . . . . . . . . . . . . . . . . . . . . . 18 5.3 Dropout definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 Doc ID 15194 Rev 2 EMIF06-SD03F3 1 Functional description Functional description A SIDE (Host-CPU) pin list: VccA, Enable, Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, Vbat B SIDE (SD-Card) pin list: WP, CD, VccB, CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B Table 1. Pin name Note: Pin definition Bump Type Side Description VccA B3 Power input A Power supply (1.8v) VccB B4 Power output B Power supply (internally generated, 2.9 V) Vbat A4 Power input A Battery power supply GND C4 Ground - Ground GND C3 Ground - Ground Enable C2 Input A Internal power supply enable CMD.dir A2 Input A Command direction CMD.h D2 IO A A side command CLK.h C1 Input A Clock input CLK-f E2 Output A Clock feedback Dat0.dir A3 Input A Data direction Dat0.h D1 IO A Data host Dat123.dir E3 Input A Data direction Dat1.h E1 IO A Data host Dat2.h A1 IO A Data host Dat3.h B1 IO A Data host WP E4 Input to CPU A Write protect CD D3 Input to CPU A Card detect CMD-B D4 IO B Command direction CLK-B C5 Output B Clock output Dat0-B D5 IO B Data SD Dat1-B E5 IO B Data SD Dat2-B A5 IO B Data SD Dat3-B B5 IO B Data SD In Table 5, 6, 7, and 10, collective names are used for groups of pins. The names used are: *.dir = CMD.dir, Dat0.dir, Dat123.dir *.h = CMD.h, CLK.h, Dat0.h, Dat1.h, Dat2.h, Dat3.h *-B = CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B ViA = All A side input pins ViB = All B side input pins. Doc ID 15194 Rev 2 3/23 Functional description Table 2. EMIF06-SD03F3 Function table Command signals A side signals direction B side signal direction Dat1.h Enable CMD. dir Dat0.dir Dat123.dir CMD.h CLK.h CLK-f Dat0.h Dat2.h Dat1-B CMD-B CLK-B Dat0-B Dat3.h Dat2-B Dat3-B H H X X IN IN OUT X X OUT OUT X X H L X X OUT IN OUT X X IN OUT X X H X H X X IN OUT IN X X OUT OUT X H X L X X IN OUT OUT X X OUT IN X H X X H X IN OUT X IN X OUT X OUT H X X L X IN OUT X OUT X OUT X IN L X X X X X Z X X L* Z L* L* Note: 1 When A side signals direction is INPUT, SD-CARD is WRITTEN by CPU-Host (i.e B side signals direction is OUTPUT) When A side signals direction is OUTPUT, SD-CARD is READ by CPU-Host (i.e B side signals direction is INPUT) 2 For B side signals when Enable = L: * Defined by internal pull-down (see Figure 3 for pins CMD.B and data bus Dat[0…3].B) Figure 2. Configuration VccA 1.8 V Vbat IPAD Feedback Clk Low drop out voltage regulator CMD VccB CMD Dir ESD 2 kV CPU Dir0 Dir1-3 Clk CMD Data 0 - 3 WP, CD 4/23 Clk Doc ID 15194 Rev 2 CMD ESD (15 kV) and EMI Data 0 - 3 Mini SD EMIF06-SD03F3 Functional description Figure 3. Block diagram Vbat VccA VccA VCCA 15KV 2 kV LDO V REF VREF 2KV 2 kV A Enable 2KV 2 kV VccB VCCB R,C 500 500KW kΩ VccA VCCA CMD.dir 15 kV 15KV REN REF VccB VCCB VccB OTP UVLO VccB VCCB 2KV 2 kV R9 15KW 15 kΩ CMD.h CMD-B 2KV 2 kV 15 kV 15KV CLK-B CLK.h 2KV 2 kV 15 kV 15KV CLK-f 2KV 2 kV Dat0.dir VccB VCCB 2KV 2 kV R10 EMI Filters 70KW 70 kΩ Dat0.h Dat0-B 2KV 2 kV 15 kV 15KV Dat123.dir VccB VCCB 2KV 2 kV R11 70KW 70 kΩ Dat1.h Dat1-B 2KV 2 kV VccB VCCB R12 15 kV 15KV 70KW 70 kΩ Dat2.h Dat2-B 2KV 2 kV 15 kV 15KV Dat3.h Dat3-B 2KV 2kV R7 VccA VCCA R14 470KW 470k Ω 15KV 15 kV VccA VCCA Level-Shifters Level-shifters - 100KW 100k Ω R13 100KW 100 kΩ WP CD 15KV 15kV 15KV 15 kV EMIF06 -SD02F3 EMIF06-SD03F3 GND Doc ID 15194 Rev 2 5/23 Characteristics EMIF06-SD03F3 2 Characteristics Table 3. Absolute maximum ratings Symbol Parameter A SIDE (Host-CPU) All pins: HBM IEC61340-3-1 VccA, Enable, Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, Vbat Value Air discharge Contact discharge 2 2 ESD kV B SIDE (SD-Card) External pins : IEC 61000-4-2, level 4 VccB, CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B, WP, CD Tjmax Rth (j-a) (1) Pdmax Tstg Air discharge Contact discharge 15 8 Maximum junction temperature 150 °C Thermal resistance from junction to ambient Board: Epoxy FR4, copper thickness = 40 µm, 4 layers 64 °C/ W Maximum power dissipation: Pdmax= (Tjmax - Taopmax)/ Rth (j-a) 1 W Storage temperature range -55 to +150 °C Vbat, VccB, Enable -0.3 to 5.5V CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B Voltage Unit -0.3 to VccB + 0.3 -0.3 to 3.3 VccA Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, WP, CD V -0.3 to VccA+0.3 1. VccB is an internally generated power supply, no external voltage should be applied on this pin other than a current clamp. The thermal resistance depends on printed circuit board layout. To dissipate the heat efficiently away from Flip Chip bumps, it is better to make copper planes the largest possible as well as considering thermal vias usage. 6/23 Doc ID 15194 Rev 2 EMIF06-SD03F3 Table 4. Symbol Characteristics Recommended operating conditions Parameter Conditions Min. Typ. Max. Unit VccA Power supply 1.62 1.8 1.92 V Vbat Battery power supply 3.1 - 5 V Iout VccB output current 0.10 100 200 mA Cbat External battery capacitance Ceramic capacitor - 2.20 - µF Cout(1) External output capacitance Ta = -40 °C to +85 °C, Vbias = 0 V to 3.3 V Multi-layer ceramic capacitor type like: C20RX7R1C225K 1.4 (-35%) 2.20 3.0 (+35%) µF ESR(2) Equivalent series resistance for Cout F = 1 Hz to 10 MHz Multi-layer ceramic capacitor type like: C2012X7R1C225KT - 3 200 mΩ Taop Ambient operating temperature -30 25 85 °C Tjop Juntion operating temperature -30 25 125 °C Pdop Maximum power dissipation - - 625 mW Enable Enable input voltage 0 - VccA V External pins (without CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B WP and CD) 0 - VccB V Internal pins (except WP, CD, Dat123.dir, CMD.dir, CMD.h, CLK.h, Enable, with CLK-f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h WP and CD) 0 - VccA V Pdop = (Tjop - Taop)/Rth (j-a) 1. Cout = 2.2 µF is minimum allowable capacitance value to guarantee LDO stability 2. Values for ESR include the VccB - Cout resistance path and Cout - GND resistance path. These resistance paths need to be minimized in PCB design. Doc ID 15194 Rev 2 7/23 Passive integration and low pass filter Table 5. LDO - current levels in recommended operating conditions Symbol Test conditions(1) Parameter Min. Typ. Max. Unit Quiescent current consumption IccA_OFF VEN = 0.4 V, Vbat = 3.4 V, VccA = 1.92 V *.dir, *.h, *-B = GND, WP = CD = VccA All other pins floating - - 1 µA Quiescent current consumption Ibat_OFF VEN = 0.4 V, Vbat = 5 V, VccA = 1.92 V *.dir, *.h, *-B = GND All other pins floating - - 1 µA - 160 220 µA Quiescent current consumption (Ground pin current) Ibat + IccA Iout = 100 µA Level shifter disactivated Iout = 50 mA *.dir = 0 V, Vbat = 3.4 V VEN = VccA = VCLK.h = 1.8 V I = 100 mA out All other pins floating Iout = 200 mA - 320 375 µA - 470 550 µA - 750 900 µA IQ_OFF IQ_ON EMIF06-SD03F3 1. See Note: on page 3 for definition of collective names of pins, for example *.dir Table 6. Level shifter - current levels in recommended operating conditions Symbol Test conditions(1) Parameter Min. Typ. Max. Unit IccA_ON Quiescent current on VccA VEN = VccA = 1.92 V, Vbat = 3.4 V *.dir = VccA, ViA = *.h = VccA - 3 10 µA IccB_ON Quiescent current on VccB VEN = VccA = 1.92 V, Vbat = 3.4 V *.dir = 0 V, VccB = 3.05 V, ViB = VccB - 15 30 µA 1. See Note: on page 3 for definition of collective names of pins, for example *.dir 3 Passive integration and low pass filter Figure 4. Circuit diagram of EMIF06-SD03F3 (without LDO) R14 R13 VccA CLK.h CMD.h Data0.h Data1.h Data2.h Data3.h Enable R12 R11 R9 level Shifter Host side R10 VccB Card side ESD 2 kV R3 R4 R5 R6 15 kV R7 ESD 15 kV REN ESD 15 kV WP CD 15 kV 15 kV G ND GND Note: 8/23 CLK B CMD B Data0 B Data1 B Data2 B Data3 B R1 R2 G ND GND VBR in 14 V technology for pins: CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B, WP, CD VBR in 8 V technology for pins: Vcc-B, CLK.h, CLK-f, CMD.h, Dat0.h, Dat1.h, Dat2.h, Dat3.h Doc ID 15194 Rev 2 15 kV EMIF06-SD03F3 Table 7. Passive integration and low pass filter Components Symbol Test conditions(1) Parameter Min. Typ. Max. Unit Cin-A Input capacitance for A Vbat = 3.4 V, *.dir = VEN = VccA side F = 1 MHz, Vdc = 0 V, ±30 mV, VAC = 30mV - 5 10 pF Cin-B Input capacitance for B Vbat = 3.4 V, *.dir = GND, VEN = VccA side F = 1 MHz, Vdc = 0 V, ±30 mV, VAC = 30mV - 25 35 pF CEMIF Capacitance seen on B side from EMIF filter - 15 - pF Tj = 25 °C - 40 - Ω at 20 mA 40 50 60 Ω R1, R2, R3, R4, EMIF resistors(3) R5, R6(2) Rline Line resistance (4) Tj = 25 °C 49 70 91 kΩ EMIF resistor (4) Tj = 25 °C 10.5 15 19.5 kΩ R7 EMIF resistor (4) Tj = 25 °C 329 470 611 kΩ R13 EMIF resistor(4) Tj = 25 °C 70 100 130 kΩ R14 (4) EMIF resistor Tj = 25 °C 70 100 130 kΩ REN resistor(4) Tj = 25 °C - 500 - kΩ R10, R11, R12 EMIF resistors R9 1. See Note: on page 3 for definition of collective names of pins, for example *.dir 2. These values are guaranteed by design and statistical process control. 3. 20% tolerance in resistance value 4. 30% tolerance in resistance value Figure 5. Frequency response with level shifters internally bypassed(1) Figure 6. Crosstalk response with level shifters internally bypassed(1) dB dB 0.00 0.00 - 5.00 - 20.00 - 10.00 - 40.00 - 15.00 - 60.00 - 20.00 - 80.00 - 25.00 - 100.00 F (Hz) F (Hz) - 30.00 100.0k 1.0M 10.0M 100.0M f/Hz a1- a5 c1 - c5 e1- e5 1.0G - 120.00 100.0k b1- b5 d1- d5 1.0M a1- b5 d1- e5 10.0M 100.0M 1.0G c1 - d5 1. Measurement in 50 Ω environment Doc ID 15194 Rev 2 9/23 Data transmission 4 EMIF06-SD03F3 Data transmission All values in the tables below are guaranteed across the operating temperature and voltage range unless otherwise specified. Table 8. DC voltage levels on host side Symbol Parameter VIHA Test conditions Min. Typ. Max. Unit High level input voltage 0.65 x VccA VccA - V VILA Low level input voltage 0 0 0.35 x VccA V VOHA High level output voltage Ioh = -6 mA VccA - 0.45 - - V VOLA Low level output voltage Iol = 7 mA - 0 0.45 V Min. Typ. Max. 0.7 x VccB(1) VccB - Table 9. Symbol VIHB DC voltage levels on SD side Test conditions Parameter High level input voltage VILB Low level input voltage VOHB High level output voltage Ioh = -8 mA VOLB Low voltage output voltage Iol = 8 mA 0.3 x VccB Unit V (1) - 0 V VccB(1) - 0.7 2.9 - V - 0 0.7 V 1. VccB is defined in power supply block. Table 10. Symbol DC current levels Parameter Test conditions(1) ILH Leakage current on host pin VEN = *.dir = VccA = 1.92 V, ViA = VccA or GND, Vbat = 3.4 V - - 5 µA ILSD Leakage current on SD pin Vbat = 3.4 V, VCLK.h = VccA, VCMD = VDat0 = VDat1 = VDat2 = VccB VDat3 = *.dir = GND - - 5 µA ISCH Short circuit current on host side SD input = H, host= 0 V SD input = 0 V, host = VccA = 1.8 V *.dir = 0 V, Vbat = 3.4 V, Tj = 25 °C - 25 - mA ISCSD Short circuit current on SD side Host input = H, SD = 0 V Host input= L, SD = VccB, Tj = 25 °C *.dir = VccA = 1.8 V, Vbat = 3.4 V - 60 - mA 1. See Note: on page 3 for definition of collective names of pins, for example *.dir 10/23 Min. Typ. Max. Unit Doc ID 15194 Rev 2 EMIF06-SD03F3 Data transmission Figure 7. Symbol definitions of tplh, tphl, tr and tf for AC characteristics in Table 11 VccA or VccB INPUT 50% 50% 0V tphl tplh 70% VccA or VccB 70% 50% OUTPUT 20% 50% 20% 0V tr Table 11. tf AC characteristics(1) Symbol Parameter tphl Propagation delay hl from host to SD tplh Propagation delay lh from host to SD tphl Propagation delay hl from SD to host tplh Propagation delay lh from SD to host Test conditions Min. Typ. Max. Unit - 3.5 6 - 3.5 6 - 3 6 - 3 6 Section 4.1 ns Section 4.2 ns Rise time from host to SD Section 4.1 - 1.5 3 Rise time from SD to host Section 4.2 - 0.5 2 Fall time from host to SD Section 4.1 - 1.9 3 Fall time from SD to host Section 4.2 - 0.5 2 tskew Delay differences from host to SD Section 4.1,Section 4.3 -1.0 0 1.0 ns tskew.f tskew delay from SD to host Section 4.2, Section 4.4 -1.5 0 1.5 ns tp_clkf Propagation delay for CLK feedback - 6.5 12 ns tr_clkf Rise time for CLK feedback Section 4.2 - 0.5 2 ns tf_clkf Fall time for CLK feedback Section 4.2 - 0.5 2 ns tr tf ns ns 1. Taop -30 to 85 °C, Iout = 1 mA, Cbat = 2.2 µF, Cout = 2.2 µF 4.1 Test circuit from host to SD Test circuit from host to SD is shown in Figure 8. Timings are measured for the whole line cell (shifter + EMI + ESD) on an external load Csd = 15 pF (board capacitance 5 pF + SD card capacitance 10 pF). Figure 8. Test circuit from host to SD HOST SD Csd =15 pF Doc ID 15194 Rev 2 11/23 Data transmission 4.2 EMIF06-SD03F3 Test circuit from SD to host Test circuit from SD to host is shown in Figure 9. Timings are measured for the whole line cell (shifter + EMI + ESD) on an external load Chost = 5 pF (board capacitance + host capacitance). Figure 9. Test circuit from SD to host HOST SD Chost = 5 pF 4.3 Measurement of tskew (host to SD) from rising edge CLK.h Figure 10. Example of measurement of tskew (host to SD) from rising edge of CLK.h CLK.h CLK-B 15pF CLK.f DAT.dir = « 1 » Dat-B DAT.h 15pF CPU EMIF06-SD02F3 EMIF06-SD03F3 MiniSD card tskew= Tp(CLK.h CLK -B) - Tp(Datx.h Datx-B) VccA Dat.h 50% 0V Tp(Datx.h Datx -B) VccB 50% Dat x- B 0V VccA CLK.h 50% 0V Tp(CLK.h CLK -B) VccB CLK -B 50% 0V 12/23 Doc ID 15194 Rev 2 EMIF06-SD03F3 4.4 Data transmission Measurement of tskew.f (read mode) from rising edge CLK.h Figure 11. Example of measurement of tskew.f for read mode from rising edge of CLK.h CLK.h CLK-B delay CLK.f 15pF DAT.dir = « 0 » 5pF Dat-B DAT.h 5pF CPU EMIF06-SD03F3 CLK.f ) – [ Tp(CLK.h tskew.f = Tp (CLK.h MiniSD card CLK -B) + Tp(Datx-B Datx.h)] VccA CLK.h 50% 0V Tp(CLK.h CLK -B) VccB CLK -B 50% 0V VccB 50% Datx-B 0V Tp(Datx-B Datx .h) VccA Datx .h 50% 0V Tp ( CLK.h CLK. f ) VccA 50% CLK. f 0V Datx.h = Dat0.h, Dat1.h, Dat2.h, Dat3.h, CMD.h Datx-B = Dat0-B, Dat1-B, Dat2-B, Dat3-B, CMD.B Doc ID 15194 Rev 2 13/23 Low drop out voltage regulator 5 EMIF06-SD03F3 Low drop out voltage regulator Figure 12. Low drop out voltage regulator Power Management ASIC Vbat VBAT VCCA V ccA CBAT C bat BAT CVCCA C VccA VCCA V ccA VBAT V bat 2kV 2 kV vref V ref UVLO + A TSD Base Band ASIC VEN VEN V VCCA ccA EN LOGIC VccB VCCB Vbat VBAT Level LS Shifter R,C 15kV 15 kV VCCB VccB COUT C out 2kV 2 kV REN Req = 135 Ω 500 kΩ EMIF06-SD02F3 (LDO part only) EMIF06-SD03F3 Gnd GND 14/23 Doc ID 15194 Rev 2 GND Gnd Mini-SD Card EMIF06-SD03F3 Table 12. Symbol Vout Low drop out voltage regulator Static parameters, VEN = VccA unless otherwise specified(1) Parameter Regulated output voltage (VccB) Test conditions Min. Typ. Max. Unit Vbat = 3.4 V, Iout = 100 mA, Tj = 25 °C 2.81 (-3%) 2.90 2.99 (+3%) V Vbat = 3.4 V, Iout = 100 mA, Tj = -30 to 125 °C 2.81 (-3%) - 2.99 (+3%) V Vbat = 3.1 to 5 V, Iout = 0.1 to 200 mA, Tj = -30 to 125 °C 2.75 (-5%) - 3.05 (+5%) V LiR Line regulation Vbat = 3.4 to 5 V (Section 5.1), Iout = 100 mA, Tj = 25 °C - 3 20 mV LdR Load regulation Vbat = 3.4 V, Iout = 1 to 200 mA (Section 5.2), Tj = 25 °C - 50 100 mV Iout = 50 mA - 25 37 mV Dropout voltage Vout(nom) - 100 mV (Section 5.3), Tj = -30 to 85 °C Iout = 100 mA - 50 75 mV Iout = 200 mA - 100 150 mV - 500 - mA Shutdown (Temp ↑) - 150 - °C Reset (Temp ↓) - 130 - °C Hysteresis - 20 - °C Shutdown (Vbat ↓) 2.3 2.5 2.7 V Reset (Vbat ↑) 2.35 2.55 2.75 V - 50 - mV VDO ISC TSD UVLO Short circuit current limitation Thermal shutdown temperature Under voltage lockout Vbat = 5 V, Vout = 0 V, Tj = 25 °C Vbat = 3.4 V Tj = -30 to 125 °C Hysteresis 1. Level shifter disactivated, *.dir = 0, CLK.h = VccA , all other pins floating. Doc ID 15194 Rev 2 15/23 Low drop out voltage regulator Table 13. Symbol EMIF06-SD03F3 Dynamic parameters (VEN = VccA unless otherwise specified) Parameter Test conditions Min. Typ. Max. Unit LiTr Line transient peak voltage Vbat = 3.4 V ↑↓ 4 V, ttr = 30 µs, Iout = 200 mA Tj = 25 °C (Section 5.1) Cout = 2.2 µF, ESR = 5 mΩ LdTr Load transient peak voltage Iout = 1 mA ↑↓ 200 mA, ttr = 10 µs, Vbat = 3.4 V Tj = 25 °C (Section 5.2) Cout = 2.2 µF, ESR = 5 mΩ PSRR Power supply rejection ratio Vbat = 3.4 V, Iout = 100 mA, Tj = 25 °C, Cout = 2.2 µF, ESR = 5 mΩ - 4.2 - mV - 9 - mV F = 1 kHz - 45 - dB F = 10 kHz - 35 - dB tstart Settling time Vout ↑ 95% Nom, Vbat = 5 V, Iout = 200 mA Tj = -30 °C to 125 °C, Cout = 2.2 µF, Enable L → H - 30 200 µs tstop Discharge time Vout ↓ 10% Nom, Vbat = 3.4 V, Iout = 1 mA Tj = 25 °C, Cout = 2.2 µF, Enable H → L - 600 - µs 16/23 Doc ID 15194 Rev 2 EMIF06-SD03F3 5.1 Low drop out voltage regulator Line regulation and transient line regulation The line regulation (LiR) is a static variable that indicates the change in the output voltage of the voltage controller ΔVout (at constant load) when there is a change ΔVbat at the input voltage. By contrast the line transient response (LiTr) represents dynamic peak value to be observed during the change in input voltage Thermal effects due to changes in the junction temperature are circumvented with pulsed voltage during the test and are to be taken into account separately. The figure shows the boundary conditions for trise, tfall, and ΔVbat to be taken as the basis of the measurement of the line transient response without additional decoupling of the supply voltage by a buffer capacity Cbat. The values defined in the specification apply, however, only in the case of decoupling of the supply voltage with such a capacity Cbat, as a result of which the values for trise and tfall are influenced to some extent. Figure 13. Line regulation and transient line regulation Vbat Static and dynamic line regulation VbatH VbatL trise = ttr tfall = ttr Time Vout Vrise LiR Vfall Time Line Regulation: LiR=f(VbatH,VbatL) Line Transient: LiTr = MAX( Vrise, Vfall) –LiR(VbatH,VbatL) Transient line regulation measurement Typcial values at 25° C Vbat 4V X: 0.2 ms/div Y: 100 mV/div 3.4 V Vout X: 0.2 ms/div Y: 4 mV/div 5 Line regulation (LiR) and Line transient (LiTr) versus temperature (typical values 4 3 LiR (mV) LiTr (mV) 2 1 0 -10 25 Doc ID 15194 Rev 2 85 Temperature ( °c) 17/23 Low drop out voltage regulator 5.2 EMIF06-SD03F3 Load regulation and transient load regulation The load regulation (LdR) is a static variable that indicates the change in output voltage of the voltage controllor ΔVout (at constant input voltage) in the event of a change in the load current ΔIout. By contrast the load transient response (LdTr) represents the dynamic peak value to be observed during load variation. Thermal effects due to changes in the junction temperature are circumvented by testing with pulsed load and are to be taken into account separately. The figure shows the boundary conditions for trise, tfall, and ΔIout to be taken as the basis for the measurement of the load transient response. Figure 14. Load regulation and transient load regulation Iout Static and dynamic load regulation IoutH IoutL tfall = ttr trise = ttr Time Vout Vrise LdR Vfall Load Regulation: LdR=f(IoutH,IoutL) Load Transient: LdTr = MAX( Vrise, Vfall) –LdR(IoutH,IoutL) Time Transient load regulation measurement (typical values at 25° C) X: 50µs/div Y: 50mA/div Iout Vccb X: 50µs/div Y: 10mV/div Load regulation (LdR) and Load transient (LdTr) versus temperature (typical values 60 50 40 LdR (mV) LdTr (mV) 30 20 10 0 -10 18/23 25 Doc ID 15194 Rev 2 85 Temperature ( °c) EMIF06-SD03F3 5.3 Application schematic Dropout definition The dropout voltage (VDO) is measured by decreasing the input voltage till the output voltage will drop by 100 mV compared to the output voltage measured at the specified minimum supply voltage (3.1 V). Worst case for dropout is maximum die temperature and maximum current load. This is done statically. Figure 15. Dropout definition V(Vbat) V(Vout) 3.100e+00 2.888e+00 2.873e+00 VDO 100 mV 2.772e+00 2.888e+00 -2.122e-01 6 3.100e+00 Base Application schematic Figure 16. Application schematic 1.8 V Vbat B3 A4 VccA Vbat CVccA Enable C2 Enable Cbat VccB B4 Cout EMIF06-SD03F3 A3 E3 D1 E1 A1 B1 DATA 0 -3 CMD.dir CMD.h CLK.h CLK.f CD WP DAT0.dir DAT123.dir CMD-B CLK-B DAT0.h DAT1.h DAT2.h DAT3.h DAT0 -B DAT1 -B DAT2 -B DAT3 -B C3 GND DATA dir A2 D2 C1 C1 GND CMD dir CMD CLK CLK feedback 3.0 V D3 E4 26 36 3 12 12 10 C4 Doc ID 15194 Rev 2 9 1 2 3 4 5 6 7 8 DAT2 DAT3/CD/CS CMD VSS1 VDD CLK VSS2 DAT0 DAT1 19/23 Ordering information scheme 7 EMIF06-SD03F3 Ordering information scheme Figure 17. Ordering information scheme EMIF yy - xx zz F3 EMI filter Number of lines Information x = resistance value (ohm) z = capacitance value / 10 (pF) or 2 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 µm 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 18. Flip Chip dimensions 255 µm± 40 2.1 mm ± 30 µm 400 µm ± 40 400 µm ± 40 2.1 mm ± 30 µm 20/23 Doc ID 15194 Rev 2 605 µm ± 55 EMIF06-SD03F3 Ordering information Figure 19. Footprint recommendations Figure 20. Marking Dot, ST logo ECOPACK status xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum x x z y ww Solder stencil opening : 220 µm recommended Dot identifying Pin A1 location Ø 1.55 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 ST ST ST xxz yww xxz yww xxz yww 2.25 3.5 ± 0.1 8.0 ± 0.3 2.25 0.20 ± 0.02 1.75 ± 0.1 Figure 21. Flip Chip tape and reel specifications 4.0 ± 0.1 0.69 ± 0.05 User direction of unreeling All dimensions in mm 9 Ordering information Table 14. Note: Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF06-SD03F3 HY Flip Chip 5.46 mg 5000 Tape and reel (7”) More information is available in the application notes: AN2348 :"Flip Chip : Package description and recommendations for use" AN1751 : EMI Filters: Recommendations and measurements Doc ID 15194 Rev 2 21/23 Revision history 10 EMIF06-SD03F3 Revision history Table 15. 22/23 Document revision history Date Revision Changes 21-Nov-2008 1 First issue 11-Feb-2010 2 AC timing characteristics updated in Table 11. Doc ID 15194 Rev 2 EMIF06-SD03F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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