LFTVS10-1F3 Transil™, transient voltage suppressor Features ■ Transient voltage suppressor ■ Electrostatic discharge protection ■ Electrical overstress protection ■ Unidirectional device ■ Low clamping factor VCL/VBR ■ Fast response time ■ Very thin package: 0.605 mm ■ RoHS compliant Flip Chip (4 bumps) Figure 1. A Complies with the following standards: ■ Pin configuration (bump side) B IEC 61000-4-2 level 4 – ± 15 kV (air discharge) – ± 8 kV (contact discharge) 1 2 Description The LFTVS10-1F3 is a single line diode designed specifically for the protection of integrated circuits in portable equipment and miniaturized electronic devices subject to ESD and EOS transient overvoltages. Figure 2. Device configuration A1 and A2 B1 and B2 TM: Transil is a trademark of STMicroelectronics November 2008 Rev 1 1/7 www.st.com Characteristics 1 LFTVS10-1F3 Characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Test condition Value Peak pulse power dissipation (10/1000 µs pulse) PPP Peak pulse power dissipation (8/20 µs pulse) IFSM Non repetitive surge peak forward current Tstg Storage temperature range Tj Table 2. 44 Tj initial = Tamb tp = 10 ms Tj initial = Tamb 11 A -55 to +150 °C 125 °C Electrical characteristics (Tamb = 25 °C) Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current αT Voltage temperature coefficient VF Forward voltage drop I IF Symbol Test conditions VBR IR = 15 mA IRM VRM = 8 V VCL (1) V IRM Slope = 1/Rd Min. Typ. IPP Max. 10 (2) 0.5 µA 13 V 1.05 8 VR = 0 V, VOSC = 30 mV, F = 1 MHz Unit V IPP = 1 A IF = 850 mA VF VCL VBR VRM αT Cline W 350 Maximum operating junction temperature Symbol VF Unit 200 V 10-4 / °C pF 1. 8 / 20 µs pulse waveform 2. DC current not recommended for more than 5 s. Even if diode failure mode is short circuit the bumps could exceed melting temperature and the component disassembled from the board. 2/7 LFTVS10-1F3 Figure 3. Characteristics Relative variation of peak pulse power versus initial junction temperature Figure 4. PPP[Tj initial] / PPP[Tj initial=25°C] 10000 1.1 Peak pulse power versus exponential pulse duration (typical value) PPP(W) Tj initial = 25 °C 1.0 0.9 0.8 1000 0.7 0.6 0.5 0.4 100 0.3 0.2 0.1 tp(µs) Tj(°C) 10 0.0 0 25 Figure 5. 10.0 50 75 100 125 1 150 Clamping voltage versus peak pulse current (typical values) 10 Figure 6. IPP(A) 100 1000 Relative variation of leakage current versus junction temperature (typical values) IR[Tj] / IR[Tj=25°C] 1000 Pulse 8 / 20 µs VR =8V 100 1.0 25 °C 10 85 °C -30 °C Tj(°C) VCL(V) 1 0.1 5 6 7 Figure 7. 8 9 10 11 12 13 14 15 16 Forward voltage drop versus peak forward current (typical values) 0.1 Tj initial = 25 °C Tj initial = 85 °C Tj initial = -30 °C 0.001 VFM(V) 0.0001 0.0 50 Figure 8. 75 100 125 Junction capacitance versus line voltage (typical values) Capacitance(pF) IFM(A) 1 0.01 25 17 0.2 0.4 0.6 0.8 1.0 1.2 1.4 250 240 230 220 210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 F=1 MHz VOSC=30mVRMS TJ=25°C Vr=0 to 8V Voltage(V) 0 1 2 3 4 5 6 7 8 3/7 Ordering information scheme Figure 9. LFTVS10-1F3 Breakdown voltage versus initial junction temperature (typical value) 13.0 VBR(V) 12.0 11.0 10.0 9.0 Tj(° C) 8.0 -40 2 -15 10 35 60 85 110 135 Ordering information scheme Figure 10. Ordering information scheme LF Low forward voltage Transient voltage suppressor Breakdown voltage 10 = 10 VMAX Number of lines 1 = single line Package F = Flip Chip 3 = Lead-free, pitch = 400 µm 4/7 TVS 10 - 1 F3 LFTVS10-1F3 3 Package information Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. 400 µm ± 40 Figure 11. Flip Chip dimensions 605 µm ± 55 0.77 mm ± 30 µm 185 µm ± 10 400 µm ± 40 205 µm ± 40 185 µm ± 10 0.77 mm ± 30 µm Figure 12. Footprint recommendations Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum Solder stencil opening: 220 µm recommended 255 µm ± 40 Figure 13. Marking Dot xx = marking z = manufacturing location yww = datecode (y = year ww = week) x x z y ww 5/7 Ordering information LFTVS10-1F3 Figure 14. Flip Chip tape and reel specifications Ø 1.55 ± 0.05 4.0 ± 0.1 3.5 ±- 0.05 8.0 ± 0.3 0.87 xxz yww xxz yww 0.87 xxz yww xxz yww xxz yww xxz yww xxz yww 2.0 ± 0.1 0.69 ± 0.05 User direction of unreeling All dimensions in mm Note: 1.75 ± 0.1 2.0 ± 0.05 0.20 ± 0.05 More information is available in the application notes: AN2348: “400 µm flip chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" 4 Ordering information Table 3. 5 Order code Marking Package Weight Base qty Delivery mode LFTVS10-1F3 EN Flip Chip 0.86 mg 10 000 Tape and reel (7”) Revision history Table 4. 6/7 Ordering information Document revision history Date Revision 21-Nov-2008 1 Changes Initial release. LFTVS10-1F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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