FREESCALE MC9RS08KA4CWG

深圳市南天星电子科技有限公司
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Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MC9RS08KA8
Rev. 1 , 1/2008
MC9RS08KA8
TBD
MC9RS08KA8 Series
Covers: MC9RS08KA8
Features:
• 8-Bit RS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 1.8 V to 5.5 V across temperature
range of –40°C to 85°C
– Subset of HC08 instruction set with added BGND
instruction
• On-Chip Memory
– 8 KB flash read/program/erase over full operating
voltage and temperature; KA4 has 4 KB flash
– 254 byte random-access memory (RAM); KA4 has 126
byte RAM
– Security circuitry to prevent unauthorized access to
RAM and flash contents
• Power-Saving Modes
– Wait and stop
– Wakeup from power-saving modes using real-time
interrupt (RTI), KBI, or ACMP
• Clock Source Options
– Oscillator (XOSC) — Loop-Control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
39.0625 kHz or 1 MHz to 5 MHz
– Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2% resolution
and 2% deviation over temperature and voltage;
supports bus frequencies up to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-Voltage detection with reset or interrupt
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
TBD
20-Pin W-SOIC
Case 751D
20-Pin PDIP
Case 738C
Preliminary—Subject to Change Without Notice
TBD
16-Pin PDIP
Case 648
– Single-Wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
– ADC — 12-channel, 10-bit resolution; 2.5 μs
conversion time; automatic compare function; operation
in stop; fully functional from 2.7 V to 5.5 V (8-channels
available on 16-pin package)
– TPM — One 2-channel; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on
each channel
– IIC — Inter-Integrated circuit bus module capable of
operation up to 100 kbps with maximum bus loading;
capable of higher baudrates with reduced loading
– MTIM1 and MTIM2 — Two 8-bit modulo timers
– KBI — Keyboard interrupts with rising or falling edge
detect; eight KBI ports in 16-pin and 20-pin packages
– ACMP — Analog comparator: full rail-to-rail supply
operation; option to compare to fixed internal bandgap
reference voltage; can operate in stop mode
• Input/Output
– 14/18 GPIOs including one output only pin and one
input only pin
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins
• Package Options
– 16-pin, 20-pin SOIC or PDIP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
TBD
16-Pin W-SOIC
Case 751G
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .5
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .5
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .6
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .7
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18
3.9 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4
5
3.9.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . .
3.10 Analog Comparator (ACMP) Electrical . . . . . . . . . . . .
3.11 Internal Clock Source Characteristics . . . . . . . . . . . . .
3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . .
3.14.2 Conducted Transient Susceptibility . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
20
21
21
23
26
26
26
28
28
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
1
Date
1/22/2008
Description of Changes
Initial public release
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9RS08KA8RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9RS08KA8 Series, Rev. 1
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of the MC9RS08KA8 MCU.
RS08 CORE
BDC
ANALOG COMPARATOR
(ACMP)
RS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
RTI
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
WAKEUP
LVD
KEYBOARD INTERRUPT
PTB6/SDA/XTAL
16-BIT TIMER/PWM
MODULE (TPM)
USER FLASH
VPP
PTA5/TCLK/RESET/VPP
PTA4/ACMPO/BKGD/MS
PTA3/KBIP3/SCL/ADP3
PTA2/KBIP2/SDA/ADP2
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTB7/SCL/EXTAL
(MC9RS08KA8 = 8192 BYTES)
(MC9RS08KA4 = 4096 BYTES)
PTB5/TPMCH1
PORT B
CPU
PORT A
IIC MODULE(IIC)
PTB3/KBIP7/ADP7
PTB2/KBIP6/ADP6
PTB1/KBIP5/ADP5
8-BIT TIMER
(MTIM1 and MTIM2)
USER RAM
(MC9RS08KA8 = 254 BYTES)
PTB4/TPMCH0
PTB0/KBIP4/ADP4
PORT C
PTC3/ADP11
(MC9RS08KA4 = 126 BYTES)
PTC2/ADP10
PTC1/ADP9
PTC0/ADP8
20-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
31.25 kHz to 39.0625 kHz
1 MHz to 5 MHz
(XOSC)
VSS
VDD
VOLTAGE REGULATOR
Figure 1. MC9RS08KA8 Series Block Diagram
2
Pin Assignments
This section shows the pin assignments in the packages available for the MC9RS08KA8 series.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
Pin Assignments
Table 1. Pin Availability by Package Pin-Count
Pin
Number
20
16
1
1
PTA5
2
2
PTA4
3
3
4
4
5
5
6
Alt 1
ACMPO
--> Highest
Alt 2
Alt 3
TCLK
RESET
BKGD
MS
SCL1
PTB6
1
EXTAL
SDA
XTAL
2
TPMCH1
8
8
PTB4
TPMCH02
9
—
PTC3
ADP11
10
—
PTC2
ADP10
11
—
PTC1
ADP9
12
—
PTC0
13
9
PTB3
KBIP7
ADP7
14
10
PTB2
KBIP6
ADP6
15
11
PTB1
KBIP5
ADP5
ADP8
16
12
PTB0
KBIP4
17
13
PTA3
KBIP3
SCL1
18
14
PTA2
KBIP2
SDA1
16
VPP
VSS
PTB7
PTB5
15
Alt 4
VDD
7
20
2
6
Port Pin
Priority
7
19
1
<-- Lowest
PTA1
PTA0
KBIP1
KBIP0
ADP4
ADP3
ADP2
TPMCH1
2
ADP1
ACMP–
TPMCH0
2
ADP0
ACMP+
IIC pins can be remapped to PTA3 and PTA2
TPM pins can be remapped to PTA0 and PTA1
PTA5/TCLK/RESET/VPP
1
20
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA4/ACMPO/BKGD/MS
2
19
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
VDD
3
18
PTA2/KBIP2/SDA/ADP2
VSS
4
17
PTA3/KBIP3/SCL/ADP3
PTB7/SCL/EXTAL
5
16
PTB0/KBIP4/ADP4
PTB6/SDA/XTAL
6
15
PTB1/KBIP5/ADP5
PTB5/TPMCH1
7
14
PTB2/KBIP6/ADP6
PTB4/TPMCH0
8
13
PTB3/KBIP7/ADP7
PTC3/ADP11
9
12
PTC0/ADP8
PTC2/ADP10
10
11
PTC1/ADP9
Figure 2. MC9RS08KA8 Series in 20-Pin PDIP/SOIC Package
MC9RS08KA8 Series, Rev. 1
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
PTA5/TCLK/RESET/VPP
1
16
PTA0/KBIP0/TPMCH0/ADP0/ACMP+
PTA4/ACMPO/BKGD/MS
2
15
PTA1/KBIP1/TPMCH1/ADP1/ACMP–
VDD
3
14
PTA2/KBIP2/SDA/ADP2
VSS
4
13
PTA3/KBIP3/SCL/ADP3
PTB7/SCL/EXTAL
5
12
PTB0/KBIP4/ADP4
PTB6/SDA/XTAL
6
11
PTB1/KBIP5/ADP5
PTB5/TPMCH1
7
10
PTB2/KBIP6/ADP6
PTB4/TPMCH0
8
9
PTB3/KBIP7/ADP7
Figure 3. MC9RS08KA8 Series in 16-Pin PDIP/SOIC Package
3
Electrical Characteristics
3.1
Introduction
This chapter contains electrical and timing specifications for the MC9RS08KA8 series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this chapter.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
Electrical Characteristics
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 5.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
±25
mA
Tstg
–55 to 150
°C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two
resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD except the RESET/VPP pin which is internally
clamped to VSS only.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum
current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are:
if no system clock is present, or if the clock rate is very low which would reduce overall power consumption.
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits and it
is user-determined rather than being controlled by the MCU design. In order to take PI/O into account in power calculations,
determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except
in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 4. Thermal Characteristics
Rating
Symbol
Value
Unit
Operating temperature range (packaged)
TA
TL to TH
–40 to 85
°C
Maximum junction temperature
TJMAX
105
°C
Thermal resistance 16-pin PDIP
θJA
80
°C/W
Thermal resistance 16-pin SOIC
θJA
112
°C/W
Thermal resistance 20-pin PDIP
θJA
75
°C/W
Thermal resistance 20-pin SOIC
θJA
96
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
MC9RS08KA8 Series, Rev. 1
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
θJA = Package thermal resistance, junction-to-ambient, °C /W
PD = Pint + PI/O
Pint = IDD × VDD, Watts chip internal power
PI/O = Power dissipation on input and output pins user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA× (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations 1 and 2 iteratively for any
value of TA.
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be used to avoid exposure to static discharge. Qualification tests are performed to ensure that
these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Description
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
—
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Latch-up
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
Rating1
No.
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
—
V
2
Machine model (MM)
VMM
±200
—
V
3
Charge device model (CDM)
VCDM
±500
—
V
ILAT
±1002
—
mA
4
Latch-up current at TA = 85°C
(applies to all pins except pin 9
PTC3/ADP11)
Latch-up current at TA = 85°C
(applies to pin 9 PTC3/ADP11)
ILAT
±753
—
mA
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
2 These pins meet JESD78A Class II (section 1.2) Level A (section 1.3) requirement of ±100mA.
3 This pin meets JESD78A Class II (section 1.2) Level B (section 1.3) characterization to ±75mA.
This pin is only present on 20 pin package types.
3.6
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 7. DC Characteristics
(Temperature Range = –40 to 85°C Ambient)
Parameter
Symbol
Min
Typical
Max
Unit
VDD
1.8
—
5.5
V
Minimum RAM retention supply voltage applied to VDD
VRAM
0.81
—
—
V
Low-voltage Detection threshold
(VDD falling)
(VDD rising)
VLVD
1.80
1.88
1.86
1.94
1.95
2.03
V
Power on RESET (POR) voltage
VPOR1
0.9
—
1.7
V
Supply voltage (run, wait and stop modes.)
0 < fBus <10MHz
Input high voltage (VDD > 2.3V) (all digital inputs)
VIH
0.70 × VDD
—
—
V
Input high voltage (1.8 V ≤ VDD ≤ 2.3 V) (all digital inputs)
VIH
0.85 × VDD
—
—
V
Input low voltage (VDD > 2.3 V) (all digital inputs)
VIL
—
—
0.30 × VDD
V
Input low voltage (1.8 V ≤ VDD ≤ 2.3 V)
(all digital inputs)
VIL
—
—
0.30 × VDD
V
Vhys1
0.06 × VDD
—
—
V
Input leakage current (per pin)
VIn = VDD or VSS, all input only pins
|IIn|
—
0.025
1.0
μA
High impedance (off-state) leakage current (per pin)
VIn = VDD or VSS, all input/output
|IOZ|
—
0.025
1.0
μA
Internal pullup resistors2(all port pins)
RPU
20
45
65
kΩ
Internal pulldown resistors2(all port pins except PTA5)
RPD
20
45
65
kΩ
—
45
—
95
kΩ
Input hysteresis (all digital inputs)
PTA5 Internal pulldown resistor
MC9RS08KA8 Series, Rev. 1
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics
(Temperature Range = –40 to 85°C Ambient)
Parameter
Symbol
Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
1.8 V, ILoad = 0.5 mA
Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 5 mA
3 V, ILoad = 3 mA
1.8 V, ILoad = 2 mA
Min
Typical
Max
VDD – 0.8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
40
—
—
—
—
—
—
0.8
—
—
—
—
—
—
0.8
—
—
40
mA
—
—
—
—
0.2
0.8
mA
mA
—
—
7
pF
VOH
VDD – 0.8
|IOHT|
Maximum total IOH for all port pins
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 1 mA
1.8 V, ILoad = 0.5 mA
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 5 mA
3 V, ILoad = 3 mA
1.8 V, ILoad = 2 mA
VOL
IOLT
Maximum total IOL for all port pins
Unit
V
mA
V
current3, 4, 5 ,6
DC injection
VIn < VSS, VIn > VDD
Single pin limit
Total MCU limit, includes sum of all stressed pins
Input capacitance (all non-supply pins)
1
2
3
4
5
6
CIn
This parameter is characterized and not tested on each device.
Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
All functional non-supply pins are internally clamped to VSS and VDD except the RESET/VPP which is internally clamped
to VSS only.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
This parameter is characterized and not tested on each device.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 5.5 V
-50
IOH (mA)
-40
85C
25C
-40C
-30
-20
-10
0
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD-VOH (V)
Figure 4. Typical IOH vs. VDD–VOH
VDD = 5.5 V (High Drive)
IOH vs VDD-VOH (Low Drive) at VDD = 5.5 V
-12
IOH (mA)
-10
85C
25C
-40C
-8
-6
-4
-2
0
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VDD-VOH (V)
Figure 5. Typical IOH vs. VDD–VOH
VDD = 5.5 V (Low Drive)
MC9RS08KA8 Series, Rev. 1
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
IOH vs VDD-VOH (High Drive) at VDD = 3 V
IOH (mA)
-20
-15
85C
25C
-40C
-10
-5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VDD-VOH (V)
Figure 6. Typical IOH vs. VDD–VOH
VDD = 3 V (High Drive)
IOH vs VDD-VOH (Low Drive) at VDD = 3 V
-5
IOH (mA)
-4
85C
25C
-40C
-3
-2
-1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VDD-VOH (V)
Figure 7. Typical IOH vs. VDD–VOH
VDD = 3 V (Low Drive)
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
Electrical Characteristics
IOH (mA)
IOH vs VDD-VOH (High Drive) at VDD = 1.8 V
-7
-6
-5
-4
-3
-2
-1
0
85C
25C
-40C
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VDD-VOH (V)
Figure 8. Typical IOH vs. VDD–VOH
VDD = 1.8 V (High Drive)
IOH (mA)
IOH vs VDD-VOH (Low Drive) at VDD = 1.8 V
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
85C
25C
-40C
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VDD-VOH (V)
Figure 9. Typical IOH vs. VDD–VOH
VDD = 1.8 V (Low Drive)
MC9RS08KA8 Series, Rev. 1
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 5.5 V
50
IOL (mA)
40
30
85C
25C
-40C
c
20
10
0
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VOL (V)
Figure 10. Typical IOL vs. VDD–VOL
VDD = 5.5 V (High Drive)
IOL vs VOL (Low Drive) at VDD = 5.5 V
IOL(mA)
15
85C
25C
-40C
10
5
0
0.1
0.2
0.4
0.6
0.8
1.0 1.2
1.4
1.6
1.8
2.0
VOL (V)
Figure 11. Typical IOL vs. VDD–VOL
VDD = 5.5 V (Low Drive)
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 3 V
IOL (mA)
20
15
85C
25C
-40C
10
5
0
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOL (V)
Figure 12. Typical IOL vs. VDD–VOL
VDD = 3 V (High Drive)
IOL vs VOL (Low Drive) at VDD = 3 V
5
IOL (mA)
4
85C
25C
-40C
3
2
1
0
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VOL (V)
Figure 13. Typical IOL vs. VDD–VOL
VDD = 3 V (Low Drive)
MC9RS08KA8 Series, Rev. 1
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
IOL vs VOL (High Drive) at VDD = 1.8 V
5
IOL (mA)
4
85C
25C
-40C
3
2
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOL (V)
Figure 14. Typical IOL vs. VDD–VOL
VDD = 1.8 V (High Drive)
IOL(mA)
IOL vs VOL (Low Drive) at VDD = 1.8 V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
85C
25C
-40C
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOL(V)
Figure 15. Typical IOL vs. VDD–VOL
VDD = 1.8 V (Low Drive)
3.7
Supply Current Characteristics
Table 8. Supply Current Characteristics
Parameter
Run supply current3 measured at
(fBus = 10 MHz)
Symbol
VDD (V)
Typical1
Max2
Temp. (°C)
5
2.4 mA
5 mA
25
85
3
2.4 mA
—
25
85
1.80
1.7 mA
—
25
85
RIDD10
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Electrical Characteristics
Table 8. Supply Current Characteristics (continued)
Parameter
Symbol
Run supply current3 measured at
(fBus = 1.25 MHz)
VDD (V)
Typical1
Max2
Temp. (°C)
5
0.42 mA
2 mA
25
85
3
0.42 mA
—
25
85
1.80
0.3 mA
—
25
85
5
2.4 μA
5 μA
8 μA
25
85
3
2 μA
—
25
85
1.80
1.5 μA
—
25
85
5
128 μA
150 μA
165 μA
25
85
3
121 μA
—
25
85
1.80
79 μA
—
25
85
5
21 μA
22 μA
25
85
3
18.5 μA
—
25
85
1.80
17.5 μA
—
25
85
5
2.4 μA
2 μA
25
85
3
1.9 μA
—
25
85
1.80
1.5 μA
—
25
85
5
2.1 μA
2 μA
25
85
3
1.6 μA
—
25
85
1.80
1.2 μA
—
25
85
5
70 μA
80 μA
25
85
3
65 μA
—
25
85
1.80
60 μA
—
25
85
RIDD1
Stop mode supply current
SIDD
ADC adder from stop4
ACMP adder from stop
(ACME = 1)
RTI adder from stop
with 1 kHz clock source enabled5
RTI adder from stop
with 1 MHz external clock source reference
enabled
LVI adder from stop
(LVDE=1 and LVDSE=1)
1
Typicals are measured at 25°C.
Maximum value is measured at the nominal VDD voltage times 10% tolerance. Values given here are preliminary estimates
prior to completing characterization.
3
Not include any DC loads on port pins.
4 Required asynchronous ADC clock and LVD to be enabled.
2
MC9RS08KA8 Series, Rev. 1
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
5
Most customers are expected to find that auto-wakeup from stop can be used instead of the higher current wait mode. Wait
mode typical is 1.3 mA at 3 V and 1 mA at 2 V with fBus = 1 MHz.
Run IDD vs VDD at FEI mode
3.00
2.50
VDD (V)
2.00
10 MHz
1.50
4 MHz
1.25 MHz
1.00
0.50
0.00
5.5
5.0
3.3
3.0
2.7
2.0
1.8
1.7
Run IDD (A)
Figure 16. Typical Run IDD vs. VDD for FEI Mode
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Electrical Characteristics
3.8
External Oscillator (XOSC) Characteristics
Table 9. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient)
Num
1
C
C
Rating
3
D
Feedback resistor
Low range (32 kHz to 100 kHz)
High range (1 MHz to 16 MHz)
D
Series resistor
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
6
D
32
1
1
1
C1, C2
Load capacitors
C
flo
fhi
fhi-hgo
fhi-lp
D
5
Min
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
High range (RANGE = 1) FEE or FBE mode 2
High range (RANGE = 1, HGO = 1) FBELP mode
High range (RANGE = 1, HGO = 0) FBELP mode
2
4
Symbol
RF
RS
Crystal start-up time 3
Low range, low gain (RANGE = 0, HGO = 0)
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO = 0)4
High range, high gain (RANGE = 1, HGO = 1)4
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE or FBE mode 2
FBELP mode
t
t
CSTL-LP
CSTL-HGO
t
CSTH-LP
t
CSTH-HGO
fextal
Typical1 Max
—
—
—
—
Unit
38.4 kHz
5
MHz
16 MHz
8
MHz
See crystal or resonator
manufacturer’s
recommendation.
—
—
10
1
—
—
—
—
—
0
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
200
400
5
—
—
—
—
—
0.03125
0
—
—
5
40
MΩ
kΩ
ms
MHz
1
Typical data was characterized at 5.0 V, 25°C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
3 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to
achieve specifications.
4 4 MHz crystal.
2
MCU
EXTAL
XTAL
RF
C1
3.9
Crystal or Resonator
RS
C2
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
MC9RS08KA8 Series, Rev. 1
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.9.1
Control Timing
Table 10. Control Timing
Num
C
1
D
Bus frequency (tcyc = 1/fBus)
2
D
Real time interrupt internal oscillator period
3
4
5
D
D
D
Parameter
1
External RESET pulse width
2
KBI pulse width
KBI pulse width in
stop1
Symbol
Min
Typical
Max
Unit
fBus
0
—
10
MHz
tRTI
700
1000
1300
μs
textrst
150
—
—
ns
tKBIPW
1.5 tcyc
—
—
ns
tKBIPWS
100
—
—
ns
tRise, tFall
—
—
11
35
—
—
ns
3
6
D
Port rise and fall time (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
1
This is the shortest pulse guaranteed to pass through the pin input filter circuitry. Shorter pulses may or may not be recognized.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
3 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
2
textrst
RESET
Figure 17. Reset Timing
tKBIPWS
tKBIPW
KBI Pin
(rising or high level)
KBI Pin
(falling or low level)
tKBIPW
tKBIPWS
Figure 18. KBI Pulse Width
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Electrical Characteristics
3.9.2
TPM/MTIM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 11. TPM Input Timing
Num
C
Rating
Symbol
Min
Max
Unit
1
D
External clock frequency
fTPMext
DC
fBus/4
MHz
2
D
External clock period
tTPMext
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 19. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 20. Timer Input Capture Pulse
3.10
Analog Comparator (ACMP) Electrical
Table 12. Analog Comparator Electrical Specifications
1
Num
C
Characteristic
1
D
Supply voltage
2
P
Supply current (active)
3
D
4
Symbol
Min
Typical
Max
Unit
VDD
1.80
—
5.5
V
IDDAC
—
20
35
μA
Analog input voltage1
VAIN
VSS – 0.3
P
Analog input offset voltage1
VAIO
5
C
Analog Comparator hysteresis1
VH
6
C
Analog source impedance1
RAS
—
VDD
V
20
40
mV
3.0
9.0
15.0
mV
—
—
10
kΩ
7
P
Analog input leakage current
IALKG
—
—
1.0
μA
8
C
Analog Comparator initialization delay
tAINIT
—
—
1.0
μs
9
P
Analog Comparator bandgap reference
voltage
VBG
1.1
1.208
1.3
V
These data are characterized but not production tested.
MC9RS08KA8 Series, Rev. 1
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
3.11
Internal Clock Source Characteristics
Table 13. Internal Clock Source Specifications
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
1
C
Average internal reference frequency — untrimmed
fint_ut
25
31.25
41.66
kHz
2
P
Average internal reference frequency — trimmed
fint_t
31.25
39.06
39.0625
kHz
3
C
DCO output frequency range — untrimmed
fdco_ut
12.8
16
21.33
MHz
4
P
DCO output frequency range — trimmed
fdco_t
16
20
20
MHz
5
C
Resolution of trimmed DCO output frequency
at fixed voltage and temperature
Δfdco_res_t
—
—
0.2
%fdco
6
C
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δfdco_t
—
—
2
%fdco
7
C
FLL acquisition time2,3
tacquire
—
—
1
ms
8
C
t_wakeup
—
—
μs
Stop recovery time (FLL wakeup to previous acquired
frequency)
IREFSTEN=0
IREFSTEN=1
100
86
1
Data in typical column was characterized at 3.0 V and 5.0 V, 25°C or is typical recommended value.
This parameter is characterized and not tested on each device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBILP) to FLL enabled (FEI, FBI).
2
3.12
ADC Characteristics
Table 14. 5 Volt 10-bit ADC Operating Conditions
C
Characteristic
Conditions
Symb
Min.
Typical
Max.
Unit
VADIN
VSS
—
VDD
V
—
—
8 bit
—
—
D
Input voltage
C
Accuracy
C
Input capacitance
CADIN
—
4.5
5.5
pF
C
Input resistance
RADIN
—
3
5
kΩ
RAS
—
—
—
—
5
10
kΩ
—
—
10
0.4
—
8.0
0.4
—
8.0
C
Analog source resistance
external to MCU
VDD = 2 V
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
8 bit mode (all valid fADCK)
D
ADC conversion clock
frequency
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADCK
MHz
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 21. ADC Input Impedance Equivalency Diagram
Table 15. 10-bit ADC Characteristics
C
Symb
Min
Typical1
Max
Unit
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
T
IDDAD
—
133
—
μA
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
T
IDDAD
—
218
—
μA
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
T
IDDAD
—
327
—
μA
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
C
IDDAD
—
0.582
1
mA
T
IDDAD
—
0.011
1
μA
—
3.3
—
T
fADACK
—
2
—
Characteristic
Conditions
Supply current
Stop, reset, module off
ADC asynchronous clock
source
High speed (ADLPC = 0)
Low power (ADLPC = 1)
MHz
MC9RS08KA8 Series, Rev. 1
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 15. 10-bit ADC Characteristics (continued)
Characteristic
Conversion time (including
sample time)
Conditions
C
Symb
P
tADC
Short sample (ADLSMP=0)
Long sample (ADLSMP=1)
Short sample (ADLSMP=0)
Sample time
P
Long sample (ADLSMP=1)
tADS
10 bit mode
Total unadjusted error
C
8 bit mode
10 bit mode
ETUE
P
Min
Typical1
Max
Unit
—
20
—
—
40
—
ADCK
cycles
—
3.5
—
—
23.5
—
—
±1
±2.5
—
±0.5
±1.0
—
±0.5
±1.0
—
±0.3
±0.5
DNL
Differential non-linearity
8 bit mode
T
ADCK
cycles
LSB2
LSB2
Monotonicity and No-Missing-Codes guaranteed
10 bit mode
Integral non-linearity
C
8 bit mode
10 bit mode
P
Zero-scale error
Full-Scale error
VADIN = VDDA
8 bit mode
T
10 bit mode
P
8 bit mode
T
EZS
EFS
10 bit mode
Quantization error
D
8 bit mode
EQ
10 bit mode
Input leakage error
pad leakage3 * RAS
D
8 bit mode
—
±0.5
±1.0
—
±0.3
±0.5
—
±0.5
±1.5
—
±0.5
±0.5
—
±0.5
±1.5
—
±0.5
±0.5
—
—
±0.5
—
—
±0.5
—
±0.2
±2.5
—
±0.1
±1
INL
EIL
LSB2
LSB2
LSB2
LSB2
LSB2
Typical values assume Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are
not tested in production.
2 1 LSB = (V
N
REFH – VREFL)/2
3 Based on input pad leakage current. Refer to pad electrical.
1
3.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. For detailed
information about program/erase operations, see the reference manual.
Table 16. Flash Characteristics
Symbol
Min
Typical1
Max
Unit
Supply voltage for program/erase
VDD
2.7
—
5.5
V
Program/Erase voltage
VPP
11.8
12
12.2
V
IVPP_prog
IVPP_erase
—
—
—
—
200
100
μA
μA
Characteristic
VPP current
Program
Mass erase
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Electrical Characteristics
Table 16. Flash Characteristics (continued)
Symbol
Min
Typical1
Max
Unit
VRead
1.8
—
5.5
V
Byte program time
tprog
20
—
40
μs
Mass erase time
tme
500
—
—
ms
Cumulative program HV time2
thv
—
—
8
ms
thv_total
—
—
2
hours
HVEN to program setup time
tpgs
10
—
—
μs
PGM/MASS to HVEN setup time
tnvs
5
—
—
μs
Characteristic
Supply voltage for read operation
0 < fBus < 10 MHz
Total cumulative HV time
(total of tme & thv applied to device)
HVEN hold time for PGM
tnvh
5
—
—
μs
HVEN hold time for MASS
tnvh1
100
—
—
μs
VPP to PGM/MASS setup time
tvps
20
—
—
ns
HVEN to VPP hold time
tvph
20
—
—
ns
time3
tvrs
200
—
—
ns
Recovery time
trcv
1
—
—
μs
1000
—
15
—
VPP rise
Program/erase endurance
TL to TH = –40°C to 85°C
tD_ret
Data retention
cycles
—
years
1
Typicals are measured at 25°C.
thv is the cumulative high voltage programming time to the same row before next erase. Same address can not be
programmed more than twice before next erase.
3 Fast V
PP rise time may potentially trigger the ESD protection structure, which may result in over current flowing into the pad
and cause permanent damage to the pad. External filtering for the VPP power source is recommended. An example VPP
filter is shown in Figure 22.
2
100 Ω
VPP
12 V
1 nF
Figure 22. Example VPP Filtering
MC9RS08KA8 Series, Rev. 1
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
tprog
WRITE DATA1
Data
Next
Data
tpgs
PGM
tnvs
tnvh
trcv
HVEN
trs
VPP2
tvps
tvph
thv
1 Next
2V
DD
Data applies if programming multiple bytes in a single row, refer to MC9RS08KA8 Series Reference Manua
must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 23. Flash Program Timing
tme
trcv
MASS
tnvs
tnvh1
HVEN
trs
VPP1
1
tvps
tvph
VDD must be at a valid operating voltage before voltage is applied or removed from the VPP pin.
Figure 24. Flash Mass Erase Timing
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Electrical Characteristics
3.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 17. Radiated Emissions, Electric Field
Parameter
Radiated emissions,
electric field
1
Symbol
VRE_TEM
Conditions
VDD = TBD
TA = 25oC
package type
TBD
Frequency
fOSC/fBUS
Level1
(Max)
0.15 – 50 MHz
TBD
50 – 150 MHz
TBD
150 – 500 MHz
500 – 1000 MHz
TBD crystal
TBD bus
Unit
dBμV
TBD
TBD
IEC Level
TBD
—
SAE Level
TBD
—
Data based on qualification test results.
3.14.2
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 18.
MC9RS08KA8 Series, Rev. 1
26
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Freescale Semiconductor
Electrical Characteristics
Table 18. Conducted Susceptibility, EFT/B
Parameter
Symbol
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
1
VCS_EFT
Conditions
VDD = TBD
TA = 25°C
package type
TBD
fOSC/fBUS
TBD crystal
TBD bus
Result
Amplitude1
(Min)
A
TBD
B
TBD
C
TBD
D
TBD
Unit
kV
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 19.
Table 19. Susceptibility Performance Classification
Result
Performance Criteria
A
No failure
The MCU performs as designed during and after exposure.
B
Self-recovering
failure
C
Soft failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
D
Hard failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
E
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.
MC9RS08KA8 Series, Rev. 1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Ordering Information
4
Ordering Information
This section contains ordering numbers for MC9RS08KA8 series devices. See below for an example of the device numbering
system.
Table 20. Device Numbering System
Memory
Package
Device Number
MC9RS08KA8
MC9RS08KA4
Flash
RAM
8K bytes
4K bytes
254 bytes
126 bytes
Type
Designator
Document No.
16 PDIP
PG
98ASB42431B
16 W-SOIC
WG
98ASB42567B
20 PDIP
PJ
98ASB42899B
20 W-SOIC
WJ
98ASB42343B
MC 9 RS08 KA 8 C XX
Status
(MC = Fully qualified)
Memory
(9 = Flash-Based)
Core
Package designator (See Table 20)
Temperature range
(C = –40°C to 85°C)
Approximate memory size (in KB)
Family
5
Mechanical Drawings
This following pages contain mechanical specifications for MC9RS08KA8 Series package options.
•
•
•
•
16-pin PDIP (plastic dual in-line pin)
16-pin W-SOIC (wide body small outline integrated circuit)
20-pin PDIP (plastic dual in-line pin)
20-pin W-SOIC (wide body small outline integrated circuit)
MC9RS08KA8 Series, Rev. 1
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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Document Number: MC9RS08KA8
Rev. 1
1/2008
Preliminary—Subject to Change Without Notice
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