FREESCALE MC9S08FL16CLC

深圳市南天星电子科技有限公司
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Freescale Semiconductor
Data Sheet: Product Preview
MC9S08FL16 Series
Covers: MC9S08FL16 and
MC9S08FL8
Features:
8-Bit S08 Central Processor Unit (CPU)
• Up to 20 MHz CPU at 4.5 V to 5.5 V across
temperature range of 0 °C to 85 °C
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
On-Chip Memory
• Up to 16 KB flash read/program/erase over full
operating voltage and temperature
• Up to 1024-byte random-access memory (RAM)
• Security circuitry to prevent unauthorized access
to RAM and flash contents
Power-Saving Modes
• Two low power stop modes; reduced power wait
mode
• Allows clocks to remain enabled to specific
peripherals in stop3 mode
Clock Source Options
• Oscillator (XOSC) — Loop-control Pierce
oscillator; Crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 16 MHz to 20 MHz
• Internal Clock Source (ICS) — Internal clock
source module containing a
frequency-locked-loop (FLL) controlled by internal
or external reference; precision trimming of
internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports
bus frequencies up to 10 MHz
System Protection
• Watchdog computer operating properly (COP)
reset with option to run from dedicated 1 kHz
internal clock source or bus clock
• Low-voltage detection with reset or interrupt;
selectable trip points
• Illegal opcode detection with reset
Document Number: MC9S08FL16
Rev. 0 Draft B, 10/2008
MC9S08FL16
32-Pin LQFP
• Illegal address detection with reset
• Flash block protection
Development Support
• Single-wire background debug interface
• Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints). On-chip in-circuit emulator (ICE)
debug module containing two comparators and
nine trigger modes.
Peripherals
• IPC — Interrupt Priority Controller to provide
hardware based nested interrupt mechanism
• ADC — 12-channel, 8-bit resolution; 2.5 μs
conversion time; automatic compare function;
1.7 mV/°C temperature sensor; internal bandgap
reference channel; operation in stop; optional
hardware trigger; fully functional from 4.5V to
5.5 V
• TPM — One 4-channel and one 2-channel
timer/pulse-width modulators (TPM) modules;
selectable input capture, output compare, or
buffered edge- or center-aligned PWM on each
channel
• MTIM16 — One 16-bit modulo timer with optional
prescaler
• SCI — One serial communications interface
module with optional 13-bit break; LIN extensions
Input/Output
• 30 GPIOs including 1 output only pin and 1 input
only pin
Package Options
• 32-pin SDIP
• 32-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
32-Pin SDIP
Table of Contents
1
2
3
4
5
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
System Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Parameter Classification . . . . . . . . . . . . . . . . . . 10
5.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 10
5.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . 11
5.5 ESD Protection and Latch-Up Immunity . . . . . . 12
5.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Supply Current Characteristics . . . . . . . . . . . . . 16
5.8 External Oscillator (XOSC) Characteristics . . . . 17
5.9 Internal Clock Source (ICS) Characteristics. . . . 18
5.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 19
6
7
5.10.1Control Timing . . . . . . . . . . . . . . . . . . . . .
5.10.2TPM Module Timing . . . . . . . . . . . . . . . .
5.11 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .
5.12 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .
5.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .
5.13.1Conducted Transient Susceptibility . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . .
20
21
22
24
25
25
26
27
27
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
0
Sep 11, 2008
Initial created by Kenny and edited by Ping.
1
Oct 17, 2008
Added information of MTIM16, IPC, and 4 ADC channels
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9S08FL16RM)
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
2
Freescale Semiconductor
MCU Block Diagram
1
MCU Block Diagram
The block diagram, Figure 1, shows the structure of MC9S08FL16 series MCU.
PTA0/ADP0
16-bit Modulo Timer
HCS08 CORE
TCLK
PTA1/ADP1
(MTIM16)
2-CH TIMER/PWM
TPM2CH[1:0]
MODULE (TPM2)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
PORT A
PTA2/ADP2
BDC
CPU
PTA4/BKGD/MS
PTA5/IRQ/TCLK/RESET
PTA6/TPM2CH0
RESET
PTA7/TPM2CH1
IRQ
COP
PTA3/ADP3
IRQ
Interrupt Priority Controller
LVD
PTB0/RxD/ADP4
(IPC)
PTB1/TxD/ADP5
Serial Communications
Interface (SCI)
TxD
RxD
USER FLASH
MC9S08FL16 — 16,384 BYTES
MC9S08FL8 — 8,192 BYTES
4-CH TIMER/PWM
USER RAM
MC9S08FL16 — 1,024 BYTES
MC9S08FL8 — 768 BYTES
PTB2/ADP6
PORT B
ON-CHIP ICE AND
DEBUG MODUE (DBG)
PTB3/ADP7
PTB4/TPM1CH0
PTB5/TPM1CH1
TPM2CH[3:0]
MODULE (TPM1)
PTB6/XTAL
PTB7/EXTAL
PTC0/ADC8
20-MHz INTERNAL CLOCK
SOURCE (ICS)
PTC1/ADP9
PORT C
PTC2/ADP10
EXTAL
XTAL
External Oscillator Source
(XOSC)
VDD
VSS
PTC3/ADP11
PTC4
PTC5
VOLTAGE REGULATOR
PTC6
PTC7
VREFH
VREFL
VDDAD
VSSAD
12-CH 8-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
ADP[11:0]
PTD0
PORT D
PTD1
NOTE
1. PTA4 is output only when used as port pin.
2. PTA5 is input only when used as port pin.
PTD2/TPM1CH2
PTD3/TPM1CH3
PTD4
PTD5
Figure 1. MC9S08FL16 Series Block Diagram
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
3
System Clock Distribution
2
System Clock Distribution
MC9S08FL16 series use ICS module as clock sources. The ICS module can use internal or external clock
source as reference to provide up to 20 MHz CPU clock. The output of ICS module includes,
• ICSERCLK — ICS external clock reference provides EXTAL signal to ADC as external reference
clock.
• ICSFFCLK — ICS fixed frequency clock reference (around 32.768 kHz) provides fixed lock
signal to TPMs.
• ICSOUT — ICS CPU clock provides double of bus clock which is basic clock reference of
peripherals.
• ICSLCLK — Alternate BDC clock provides debug signal to BDC module.
The TCLK pin is an extra external clock source. When TCLK is enabled, it can provide alternate clock
source to TPMs and MTIM16. The on-chip 1 kHz clock can provide clock source of COP module.
TCLK
1-kHz
COP
TPM1
TPM2
MTIM16
ADC
ICSERCLK
ICSFFCLK
FIXED CLOCK (XCLK)
ICS
ICSOUT
BUS CLOCK
÷2
ICSLCLK
XOSC
CPU
SCI
BDC
FLASH
RAM
IPC
EXTAL XTAL
Figure 2. System Clock Distribution Diagram
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
4
Freescale Semiconductor
Pin Assignments
3
Pin Assignments
This section shows the pin assignments for the MC9S08FL16 series devices.
PTC5
PTC4
PTA5/IRQ/TCLK/RESET
PTD2/TPM1CH2
PTA4/BKGD/MS
PTD0
PTD1
VDD
VSS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPM2CH1
PTD3/TPM1CH3
PTB4/TPM1CH0
PTC3/ADP11
PTC2/ADP10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PTC6
PTC7
PTA0/ADP0
PTD5
PTA1/ADP1
PTA2/ADP2
PTA3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/RxD/ADP4
PTB1/TxD/ADP5
PTB2/ADP6
PTD4
PTB3/ADP7
PTC0/ADP8
PTC1/ADP9
Figure 3. MC9S08FL16 Series 32-Pin SDIP Package
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
5
PTA0/ADP0
25 PTD5/TPM1CH5
PTC7
PTC6
PTC5
PTC4
PTA5/IRQ/TCLK/RESET
32
31
30
29
28
27
26
PTD2/TPM1CH2
Pin Assignments
PTA4/BKGD/MS 1
PTA2/ADP2
PTA3/ADP3
PTA6/TPM2CH0
PTA7/TPM2CH1
PTB0/RxD/ADP4
PTB1/TxD/ADP5
17 PTB2/ADP6
PTD4
PTB3/ADP7
PTD3/TPM1CH3 9
PTB5/TPM1CH1
PTC0/ADP8
PTB6/XTAL
PTC1/ADP9
PTB7/EXTAL
PTC2/ADP10
VSS
PTC3/ADP11
VDD
2
3
4
5
6
7
8
10
11
12
13
14
15
16
PTD1
PTA1/ADP1
24
23
22
21
20
19
18
PTB4/TPM1CH0
PTD0
Figure 4. MC9S08FL16 Series 32-Pin LQFP Package
Table 3-1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest
Alt 1
Priority
32-SDIP
32-LQFP
Port Pin
I/O
Alt 2
I/O
Alt 3
I/O
1
29
PTC5
I/O
I/O
2
30
PTC4
I/O
I/O
3
31
PTA5
I/O
TCLK
I
RESET
I
4
32
PTD2
I/O
5
1
PTA4
O
O
I
MS
I
6
2
PTD0
I/O
I/O
7
3
PTD1
I/O
I/O
8
9
4
VDD
I
5
VSS
I
10
6
PTB7
I/O
EXTAL
I
11
7
PTB6
I/O
XTAL
O
12
8
PTB5
I/O
IRQ
I/O
--> Highest
I
TPM1CH2
BKGD
TPM1CH1 I/O
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
6
Freescale Semiconductor
Pin Assignments
Table 3-1. Pin Availability by Package Pin-Count
Pin Number
<-- Lowest
Alt 1
Priority
I/O
--> Highest
32-SDIP
32-LQFP
Port Pin
I/O
Alt 2
I/O
13
9
PTD3
I/O
TPM1CH3 I/O
14
10
PTB4
I/O
TPM1CH0 I/O
Alt 3
I/O
15
11
PTC3
I/O
ADP11
I
ACMP–
I
16
12
PTC2
I/O
ADP10
I
ACMP+
I
17
13
PTC1
I/O
ADP9
I
18
14
PTC0
I/O
ADP8
I
19
15
PTB3
I/O
20
16
PTD4
I/O
I
ADP7
I
21
17
PTB2
I/O
I
ADP6
I
22
18
PTB1
I/O
I
TxD
O
ADP5
I
23
19
PTB0
I/O
I
RxD
I
ADP4
I
24
20
PTA7
I/O
TPM2CH1 I/O
25
21
PTA6
I/O
TPM2CH0 I/O
26
22
PTA3
I/O
I
ADP3
I
27
23
PTA2
I/O
I
ADP2
I
28
24
PTA1
I/O
I
ADP1
I
29
25
PTD5
I/O
30
26
PTA0
I/O
31
27
PTC7
I/O
32
28
PTC6
I/O
I/O
I/O
I
ADP0
I
NOTE
When an alternative function is first enabled, it is possible to get a spurious
edge to the module. User software should clear out any associated flags
before interrupts are enabled. Table 3-1 illustrates the priority if multiple
modules are enabled. The highest priority module will have control over the
pin. Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module.
Disable all modules that share a pin before enabling another module.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
7
Memory Map
4
Memory Map
Figure 5 shows the memory map for the MC9S08FL16 series. On-chip memory in the MC9S08FL16
series of MCUs consist of RAM, flash program memory for nonvolatile data storage, plus I/O and
control/status registers. The registers are divided into two groups:
• Direct-page registers (0x0000 through 0x003F)
• High-page registers (0x1800 through 0x187F)
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
8
Freescale Semiconductor
Memory Map
$0000
$0000
DIRECT PAGE REGISTERS
$003F
$0040
RAM 768 BYTES
$033F
$0340
DIRECT PAGE REGISTERS
$003F
$0040
RAM 1024 BYTES
$043F
$0440
UNIMPLEMENTED
$17FF
$1800
HIGH PAGE REGISTERS
$187F
$1880
UNIMPLEMENTED
$17FF
$1800
HIGH PAGE REGISTERS
$187F
$1880
UNIMPLEMENTED
UNIMPLEMENTED
$BFFF
$C000
FLASH
16384 BYTES
$DFFF
$E000
FLASH
8192 BYTES
$FFFF
$FFFF
MC9S08FL8
MC9S08FL16
Figure 5. MC9S08FL16 Series Memory Map
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
9
Electrical Characteristics
5
Electrical Characteristics
5.1
Introduction
This section contains electrical and timing specifications for the MC9S08FL16 series of microcontrollers available at the time
of publication.
5.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 2. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
5.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled.
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 5.5
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
±25
mA
Tstg
–55 to 150
°C
Storage temperature range
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
10
Freescale Semiconductor
Electrical Characteristics
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
5.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 4. Thermal Characteristics
Rating
Operating temperature range
(packaged)
Maximum junction temperature
Symbol
Value
Unit
TA
TL to TH
0 to 85
°C
TJM
TBD
°C
Thermal resistance
Single-layer board
32-pin SDIP
32-pin LQFP
θJA
TBD
66
°C/W
Thermal resistance
Four-layer board
32-pin LQFP
32-pin LQFP
θJA
TBD
47
°C/W
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
11
Electrical Characteristics
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
5.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions must be taken to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless instructed otherwise in the device specification.
Table 5. ESD and Latch-up Test Conditions
Model
Human
Body
Machine
Description
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
—
Series resistance
R1
0
Ω
Storage capacitance
C
200
pF
Number of pulses per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Latch-up
Table 6. ESD and Latch-Up Protection Characteristics
No.
1
5.6
Rating1
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
±2000
—
V
2
Machine model (MM)
VMM
±200
—
V
3
Charge device model (CDM)
VCDM
±500
—
V
4
Latch-up current at TA = 85°C
ILAT
±100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
12
Freescale Semiconductor
Electrical Characteristics
Table 7. DC Characteristics
Num C
1
Symbol
Condition
Min.
P Operating Voltage
C
2
P
3
Characteristic
D
C
4
P
4.5
All I/O pins,
low-drive strength
Output high
voltage
All I/O pins,
high-drive strength
Output high
current
Max total IOH for all ports
All I/O pins,
low-drive strength
Output low
voltage
5
D
Output low
current
6
P
7
Typical1
All I/O pins,
high-drive strength
Max.
Unit
5.5
V
V
ILoad = –2 mA
VDD – 1.5
—
—
ILoad = –10 mA
VDD – 1.5
—
—
—
—
—
100
ILoad = 2 mA
—
—
1.5
ILoad = 10 mA
—
—
1.5
—
—
—
100
mA
V
VOH
IOHT
VOL
mA
V
Max total IOL for all ports
IOLT
Input high
voltage
all digital inputs
VIH
0.65 x VDD
—
—
P
Input low
voltage
all digital inputs
VIL
—
—
0.35 x VDD
8
C
Input
hysteresis
all digital inputs
Vhys
—
0.06 x VDD
—
—
mV
9
Input
P leakage
current
all input only pins
(Per pin)
|IIn|
VIn = VDD or VSS
—
0.1
1
μA
10
Hi-Z
(off-state)
P
leakage
current
all input/output
(per pin)
|IOZ|
VIn = VDD or VSS
—
0.1
1
μA
11a
Pullup,
P Pulldown
resistors
all digital inputs, when
enabled (all I/O pins other
than
PTA5/IRQ/TCLK/RESET
RPU,
RPD
—
17.5
—
52.5
kΩ
11b
Pullup,
C Pulldown
resistors
17.5
—
52.5
kΩ
–0.2
—
0.2
mA
–5
—
5
mA
12
(PTA5/IRQ/TCLK/RESET)
DC injection
C current 3, 4,
5
RPU,
RPD
2
—
(Note )
Single pin limit
Total MCU limit, includes
sum of all stressed pins
13
C Input Capacitance, all pins
14
C RAM retention voltage
6
IIC
VIN < VSS, VIN > VDD
CIn
—
—
—
8
pF
VRAM
—
—
0.6
1.0
V
—
0.9
1.4
2.0
V
15
C POR re-arm voltage
VPOR
16
D POR re-arm time
tPOR
—
10
—
—
μs
—
TBD
—
V
—
TBD
—
V
17
C Low-voltage detection threshold
VLVD
VDD falling
VDD rising
18
C Low-voltage warning threshold
VLVW
VDD falling
VDD rising
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
13
Electrical Characteristics
Table 7. DC Characteristics (continued)
Num C
Characteristic
Low-voltage inhibit reset/recover
hysteresis
19
C
20
C Bandgap Voltage Reference7
1
2
3
4
5
6
7
Symbol
Condition
Min.
Typical1
Max.
Unit
Vhys
—
—
80
—
mV
VBG
—
—
TBD
—
V
Typical values are measured at 25°C. Characterized, not tested
The specified resistor value is the actual value internal to the device. The pullup or pulldown value may appear higher when
measured externally on the pin.
All functional non-supply pins, except for PTA5 are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum
injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is
present, or if clock rate is very low (which would reduce overall power consumption).
Maximum is highest voltage that POR is guaranteed.
Factory trimmed at VDD = 5.0 V, Temp = 25 °C
TBD
Figure 6. Pullup and Pulldown Typical Resistor Values (VDD = 5.0 V)
TBD
Figure 7. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
14
Freescale Semiconductor
Electrical Characteristics
TBD
Figure 8. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
TBD
Figure 9. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
TBD
Figure 10. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
15
Electrical Characteristics
5.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Table 8. Supply Current Characteristics
Num
P
Parameter
Symbol
Bus
Freq
10 MHz
VDD
(V)
Typical1
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
Temp
(°C)
mA
0 to 85°C
mA
0 to 85°C
μA
0 to 85°C
Run supply current
FEI mode, all modules on
RIDD
Run supply current
FEI mode, all modules off
RIDD
C
Wait mode supply current
FEI mode, all modules off
WIDD
4
C
Stop2 mode supply current
S2IDD
—
5
TBD
—
μA
0 to 85°C
5
C
Stop3 mode supply current
no clocks active
S3IDD
—
5
TBD
—
nA
0 to 85°C
6
C
ADC adder to stop3
—
5
TBD
—
μA
25°C
7
C
ICS adder to stop3
EREFSTEN = 1
—
5
TBD
—
μA
25°C
8
C
LVD adder to stop3
—
5
TBD
—
μA
25°C
1
2
3
1
C
P
P
P
C
1 MHz
10 MHz
1 MHz
20 MHz
1 MHz
5
5
5
Data in Typical column was characterized at 5.0 V, 25°C or is typical recommended value.
TBD
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
16
Freescale Semiconductor
Electrical Characteristics
Figure 11. Typical Run IDD for FBE and FEI, IDD vs. VDD
(ADC off, All Other Modules Enabled)
5.8
External Oscillator (XOSC) Characteristics
Refer to Figure 12 and Figure 13 for crystal or resonator circuits.
Table 9. XOSC and ICS Specifications (Temperature Range = 0 to 85°C Ambient)
Num
C
Characteristic
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
2
D
3
Feedback resistor
Low range, low power (RANGE=0, HGO=0)2
D
Low range, high gain (RANGE=0, HGO=1)
High range (RANGE=1, HGO=X)
4
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
4 MHz
1 MHz
5
6
Load capacitors
Low range (RANGE=0), low power (HGO=0)
Other oscillator settings
Crystal start-up time 4
Low range, low power
Low range, high gain
C
High range, low power
High range, high gain
D
Symbol
Min.
flo
fhi
fhi
32
1
1
RS
t
t
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
CSTL
CSTH
fextal
FBE or FBELP mode
—
—
—
38.4
16
8
Unit
kHz
MHz
MHz
See Note 2
See Note 3
C1,C2
RF
Typical1 Max.
—
—
—
—
10
1
—
—
—
—
—
—
—
100
0
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
600
400
5
15
—
—
—
—
ms
0.03125
0
—
—
20
20
MHz
MHz
MΩ
kΩ
1
Data in Typical column was characterized at 5.0 V, 25°C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.
3
See crystal or resonator manufacturer’s recommendation.
4
Proper PC board layout procedures must be followed to achieve specifications.
2
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
17
Electrical Characteristics
XOSC
EXTAL
XTAL
RF
C1
RS
Crystal or Resonator
C2
Figure 12. Typical Crystal or Resonator Circuit
5.9
Internal Clock Source (ICS) Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = 0 to 85°C Ambient)
Symbol
Min.
Typical1
Max.
Unit
Average internal reference frequency — factory trimmed
at VDD = 3.6 V and temperature = 25°C
fint_ft
—
32.768
—
kHz
P
Internal reference frequency — user trimmed
fint_ut
31.25
—
39.06
kHz
3
T
Internal reference start-up time
tIRST
—
60
100
μs
4
P
DCO output frequency range — trimmed2
fdco_u
24
—
30
MHz
5
P
DCO output frequency2
Reference = 32768 Hz and DMX32 = 1
fdco_DMX32
—
TBD
—
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
Δfdco_res_t
—
±0.1
±0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
Δfdco_res_t
—
±0.2
±0.4
%fdco
8
C
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δfdco_t
—
+ 0.5
–1.0
±2
%fdco
9
C
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0°C to 70 °C
Δfdco_t
—
±0.5
±1
%fdco
10
C FLL acquisition time3
tAcquire
—
—
1
ms
11
C
CJitter
—
0.02
0.2
%fdco
Num
C
1
P
2
Characteristic
Long term jitter of DCO output clock (averaged over 2-ms
interval)4
1
Data in Typical column was characterized at 5.0 V, 25°C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
2
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
18
Freescale Semiconductor
Electrical Characteristics
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
1.00%
0.50%
Deviation (%)
0.00%
-60
-40
-20
0
20
40
60
80
100
120
-0.50%
-1.00%
TBD
-1.50%
-2.00%
Temperature
Figure 13. Deviation of DCO Output from Trimmed Frequency (20 MHz, 5.0 V)
5.10
AC Characteristics
This section describes timing characteristics for each peripheral system.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
19
Electrical Characteristics
5.10.1
Control Timing
Table 11. Control Timing
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
20
MHz
D
Internal low power oscillator period
tLPO
700
—
1300
μs
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive
trstdrv
34 x tcyc
—
—
ns
5
D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
—
ns
6
D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
tMSH
100
—
—
μs
7
D
IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
16
23
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
5
9
—
—
Num
C
1
D
2
9
Rating
ns
C
ns
1
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range 0°C to 85°C.
2
textrst
RESET PIN
Figure 14. Reset Timing
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
20
Freescale Semiconductor
Electrical Characteristics
tIHIL
KBIPx
IRQ/KBIPx
tILIH
Figure 15. IRQ/KBIPx Timing
5.10.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 12. TPM Input Timing
No.
C
1
D
2
Function
Symbol
Min
Max
Unit
External clock frequency
fTCLK
0
fBus/4
Hz
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 16. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 17. Timer Input Capture Pulse
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
21
Electrical Characteristics
5.11
ADC Characteristics
Table 13. 12-bit ADC Operating Conditions
Characteristic
Supply voltage
Ground voltage
Symb
Min
Typical1
Max
Unit
Comment
Absolute
VDDAD
4.5
—
5.5
V
—
Delta to VDD (VDD-VDDAD)2
ΔVDDAD
–100
0
+100
mV
—
Delta to VSS (VSS-VSSAD)2
ΔVSSAD
–100
0
+100
mV
—
VREFH
1.8
VDDAD
VDDAD
V
—
VADIN
VREFL
—
VREFH
V
—
CADIN
—
4.5
5.5
pF
—
RADIN
—
5
7
kΩ
—
RAS
—
—
10
kΩ
External to MCU
0.4
—
8.0
MHz
—
0.4
—
4.0
Conditions
Ref Voltage
High
—
Input Voltage
—
Input
Capacitance
—
Input
Resistance
—
Analog Source
Resistance
ADC
Conversion
Clock Freq.
8 bit mode (all valid fADCK)
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADCK
Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2 DC potential difference.
1
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
22
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
–
CAS
+
–
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 18. ADC Input Impedance Equivalency Diagram
Table 14. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Symbol
Min.
Typical1
Max.
Unit
Comment
—
IDDAD
—
120
—
μA
—
T
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
—
IDDAD
—
202
—
μA
—
T
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
—
IDDAD
—
288
—
μA
—
P
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
—
IDDAD
—
0.532
1
mA
—
2
3.3
5
MHz
tADACK =
1/fADACK
C
Characteristic
T
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
P
C
ADC
Asynchronous
Clock Source
Conditions
High Speed (ADLPC=0)
Low Power (ADLPC=1)
fADACK
1.25
2
3.3
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
23
Electrical Characteristics
Table 14. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
C
P
Characteristic
Conversion
Time (Including
sample time)
Conditions
Short Sample
(ADLSMP=0)
C
Long Sample
(ADLSMP=1)
P
Short Sample
(ADLSMP=0)
Sample Time
Long Sample
(ADLSMP=1)
C
Symbol
Min.
Typical1
Max.
—
20
—
Unit
ADCK
cycles
tADC
—
40
—
—
3.5
—
ADCK
cycles
tADS
—
23.5
—
Comment
See ADC
chapter in the
QE8
Reference
Manual for
conversion
time
variances
T
Total
Unadjusted
Error
8 bit mode
ETUE
—
±0.5
—
LSB2
Includes
quantization
T
Differential
Non-Linearity
8 bit mode3
DNL
—
±0.3
±0.5
LSB2
—
T
Integral
Non-Linearity
8 bit mode
INL
—
±0.3
±0.5
LSB2
—
T
Zero-Scale
Error
8 bit mode
EZS
—
±0.5
±1.0
LSB2
VADIN =
VSSAD
T
Full-Scale
Error
8 bit mode
EFS
—
±0.5
±1.0
LSB2
VADIN =
VDDAD
D
Quantization
Error
8 bit mode
EQ
—
±0.5
—
LSB2
—
D
Input Leakage
Error
8 bit mode
EIL
—
±0.1
—
LSB2
Pad leakage3
* RAS
Temp Sensor
Slope
—
1.646
—
D
—
1.769
—
—
701.2
—
D
Temp Sensor
Voltage
0°C to 25°C
m
25°C to 85°C
25°C
VTEMP25
mV/°C
mV
Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 1 LSB = (V
N
REFH – VREFL)/2
3 Based on input pad leakage current. Refer to pad electricals.
1
5.12
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
24
Freescale Semiconductor
Electrical Characteristics
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section.
Table 15. Flash Characteristics
C
Characteristic
Symbol
Min
Typical
Max
Unit
5.5
V
D
Supply voltage for program/erase
0°C to 85°C
Vprog/erase
4.5
D
Supply voltage for read operation
VRead
4.5
—
5.5
V
fFCLK
150
—
200
kHz
tFcyc
5
—
6.67
μs
1
D
Internal FCLK frequency
D
Internal FCLK period (1/FCLK)
P
P
P
P
Byte program time (random
location)2
tprog
9
tFcyc
2
Byte program time (burst mode)
tBurst
4
tFcyc
2
tPage
4000
tFcyc
time2
tMass
20,000
tFcyc
Page erase time
Mass erase
Byte program
Page erase
—
current3
current3
RIDDBP
—
4
—
mA
RIDDPE
—
6
—
mA
—
10,000
—
cycles
10
100
—
years
endurance4
C
Program/erase
TL to TH = 0°C to + 85°C
T = 25°C
C
Data retention5
tD_ret
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied
for calculating approximate time to program and erase.
3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures
DD
with VDD = 5.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile
Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention,
please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
5.13
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
5.13.1
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The
measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC
test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient
susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
25
Ordering Information
61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is
greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 16.
Table 16. Conducted Susceptibility, EFT/B
Parameter
Symbol
Conducted susceptibility, electrical
fast transient/burst (EFT/B)
1
fOSC/fBUS
Conditions
VDD = 5V
TA = +25oC
package type
32 LQFP
VCS_EFT
8 MHz
crystal
8 MHz bus
Result
Amplitude1
(Min)
A
2.3
B
4.0
C
>4.0
D
>4.0
Unit
kV
Data based on qualification test results. Not tested in production.
The susceptibility performance classification is described in Table 17.
Table 17. Susceptibility Performance Classification
Result
6
Performance Criteria
A
No failure
The MCU performs as designed during and after exposure.
B
Self-recovering
failure
C
Soft failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the RESET pin is asserted.
D
Hard failure
The MCU does not perform as designed during exposure. The MCU does not return to
normal operation until exposure is removed and the power to the MCU is cycled.
E
Damage
The MCU does not perform as designed during and after exposure. The MCU cannot
be returned to proper operation due to physical damage or other permanent
performance degradation.
The MCU does not perform as designed during exposure. The MCU returns
automatically to normal operation after exposure is removed.
Ordering Information
This section contains ordering information for MC9S08FL16 series devices. See below for an example of the device numbering
system.
Table 18. Device Numbering System
Memory
Device Number1
Available Packages2
FLASH
RAM
MC9S08FL16
16K
1024
32 SDIP
32 LQFP
MC9S08FL8
8K
768
32 SDIP
32 LQFP
1
See the reference manual, MC9S08FL16 Series Reference Manual, for a complete
description of modules included on each device.
2
See Table 19 for package information.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
26
Freescale Semiconductor
Package Information
Example of the device numbering system:
MC 9 S08 FL 16
C XX
Status
(MC = Fully Qualified)
Package designator (see Table 19)
Temperature range
(C = 0°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate flash size in Kbytes
Family
7
Package Information
Table 19. Package Descriptions
Pin Count
7.1
Package Type
Abbreviation
Designator
Case No.
Document No.
32
Low Quad Flat Package
LQFP
LC
873A-03
98ASH70029A
32
Shrink Dual In-line Package
SDIP
TBD
1376-02
98ASA99330D
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 19.
MC9S08FL16 Series Data Sheet, Rev. 0 Draft B
Freescale Semiconductor
27
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