MXED202 128-Channel OLED Row Driver Features Description • CMOS High Voltage Process: 9V-30V Display Panel Supply Compatible • 128 Output Channels, Cascadable; Configurable 120-Output Mode • 150mA Maximum Current Capability per channel (two channels maximum active simultaneously) • 20 Ohm Maximum Row Switch “On” Resistance • Token-Based Control: Bidirectional data transfer; Single and Dual-Token Mode • Current Source Magnitude User Control: 4 µA to 1 mA • 6-Bit Monochromatic/Color Gray-Scale User Control • Monochromatic Voltage Precharge Options • 3.3 V to 5 V logic supply • Up to 100kHz clock frequency • Gold-Bumped Die @ ~ 60 micron Output Pitch • TCP packaging • Companion to MXED102 240-Channel OLED Column Driver The MXED202 Row Driver supports up to 128-row OLED panel displays. The MXED202 has low "on" switch resistance, and support of voltage precharge options, ensures uniform luminance at rapid row scan rates. This is the first ASSP production row driver for OLED display OEM's, enabling the development and manufacture of this new standard in flat-panel display technology. For All Passive-Matrix Organic-Light-EmittingDiode Displays • Monochrome and Color • Small-Molecule and Polymer • Common-Cathode Row Switching Functional Block Diagram Preliminary DS-MXED202-R2 www.clare.com 1 MXED202 Preliminary PRELIMINARY ELECTRICAL DATA SHEET The MXED202 is a row-multiplexed display driver, for Passive Matrix Organic Light Emitting Diode (OLED) and Polymer Light Emitting Diode arrays (PLED, PolyLED, LEP, . . .), with anodes connected to current-sourcing column data drivers. The common cathode rows (channels) of the display matrix are activated by sequentially switching them to a low impedance voltage source (ground/0V, typically) in synchronism with the digital data column current drive. The MXED202 supports precharging options to improve luminance control. It is manufactured in a high voltage (30 V) CMOS process and provided in bumped die and TCP (Tape Carrier Package) form. Overview A row-scan token bit is passed along the length of MXED202 shift register to successively activate the row switches. The OLED cathodes of the active row(s) are switched to RTN, a low impedance return, ground or 0V typically, while the companion column drivers source data-driven currents through each OLED to be illuminated. Inactive rows are connected to a programmable "Off" (or Precharge) voltage to ensure the OLED's are not forward-biased. A programmable precharge interval and programmable precharge voltage are available to set initial conditions for the next active row(s). In normal, or single token mode, the token may be entered at either end of the MXED202 row shift register (SRIN or SLIN), depending on the shift direction selection Shift Right (SHR). The token is shifted one row (one channel) per clock cycle, CLK. One row maximum is active at a time. In dual mode (DUAL), the token is entered at one end and automatically in the center, and again the tokens may be selectively shifted left or right at the CLK rate; two rows maximum are active at a time. The MXED202 has options for 128- and 120-row display panels. When the Select 128 (S128) pin is tied low, the token is also automatically entered at the fifth cell from the entry direction end; only the 120 middle outputs, Rows 4 through 123, should be used. Note that a lesser number of rows may be used by resetting the MXED202 (RSTB) at any time, truncating the shift cycle. Overview of Operation A row-scan token bit is passed along the length of MXED202 shift register to successively activate the row switches. The OLED cathodes of the active row(s) are switched to RTN, a low impedance return, ground or 0V typically, while the companion column drivers source data-driven currents through each OLED to be illuminated. Three successive row activations, N-1, N, N+1, are depicted in the simplified timing diagram below. Inactive rows are connected to a programmable "Off" (or Precharge) voltage to ensure the OLED's are not forward-biased. A programmable precharge interval and programmable precharge voltage are available to set initial conditions for the next active row(s). Precharge is described on page 9. 2 www.clare.com Rev. 2 Preliminary MXED202 Simplified Timing Diagram Token: The row-scan token(s) activate row switches. Token entry positions, 0 to 127, are defined in the table below: S128 00 Rev. 2 DUAL • SHR 01 10 Outputs Used 11 0 127,123 0,4 127,123,63 0,4,64 Rows 4-123 (Rows 0-3, 124-127 N/C) 1 127 0 127,63 0,64 Rows 0-127 www.clare.com 3 MXED202 Preliminary PACKAGE AND PINOUT This drawing illustrates the pin ordering and relative locations of the bond pads, only. Semiconductor Die specification(2) for exact coordinates. See the MXED202 Top View: 4 www.clare.com Rev. 2 Preliminary MXED202 PIN LIST Name I/O/A RTN I ReTurN for all display current. (Low impedance ground connection, typically) GND I GrouND, the negative return for all chip current and the digital logic "zero" refer ence level. VCC I The logic voltage positive supply. MXED202 logic operates between VCC and VSS. Digital inputs should not exceed VCC, VSS VMAX I This Voltage MAXimum is the highest positive power supply voltage present on the chip, and supplies the display panel precharge current either directly or at derived voltage VOH. Inputs to the chip should not exceed VMAX to avoid for ward biasing substrate diodes. VOH [Page 12] I/O/A Row Voltage Output High supply. This pin is normally connected to an external power supply pin VMAX with bypass capacitor, and to pin DRV. Alternatively, an internal amplifier can generate VOH from an input voltage DRV. INV [Page 12] I INVerting input to Voltage Regulator Op Amp, to which an input Resistor RI and feedback Resistor RF may be connected to develop VOH from VDRV; see DRV pin. DRV [Page 12] I When not connected to VOH and VMAX, a Drive Reference Voltage >1V can be connected to the DRV pin.Note: If VDRV <0.3V, all row circuitry is powered down. SHR I Active high static SHift Right control input: When SHR=1, the token bit travels from R0 to R127, with SRIN being the token input, SLIN the token output. When SHR=0, the token bit travels from R127 to R0, with SLIN being the token input, SRIN the token output. SHR should always be driven to the desired logic level. SRIN I/O Shift Right INput. This bi-directional pin is the token input when SHR is high, and the token output (for synchronization or cascading) when SHR is low. When con figured as an input, this pin should always be driven. Normally low, SRIN should be driven high once per frame to enter the token into the shift register. SLIN I/O Shift Left INput. This bi-directional pin is the token input when SHR is low, and the token output (for synchron- ization or cascading) when SHR is high. When configured as an input, this pin should always be driven. Normally low, SLIN should be driven high once per frame to enter the token into the shift register. DUAL I DUAL tokens are seeded into the first and middle shift register cells from SRIN or SLIN when DUAL is static active high. When low, a single token is active. CLK I The rising edge of the CLocK input shifts the token along the internal shift regis ter to activate successive rows. The display Row Scan Rate is the CLK frequen cy times the number of tokens. PCB [Pages 9-11] I If the PreCharge Bar input is low on the rising edge of CLK, all row outputs will be switched to the same voltage (see MONO) to enable display panel precharg ing until PCB returns high. Holding PCB high disables MXED202 precharge. MONO [Pages 9-11] I Enables MXED202 row driver precharge of MONOchromatic displays, if PCB=0. The MONO input has no effect if PCB=1. MOD [Pages 9-11] I This input MODifies precharge timing S128 I Select 128 row driver output mode when static active high. When low, 120 row driver output mode is selected. Rev. 2 Description www.clare.com 5 Preliminary MXED202 Pin List (Continued) ROPT [Pages 10-11] I/O/A Resistor OPTion pin, normally N/C for digitally controlled precharge timing (PCB), or when precharge is disabled. When a resistor R is connected between ROPT and PCB, and a capacitor C is connected between PCB and VSS, the precharge time will be RC/1.65 when measured from the rising edge of CLK to the falling edge of ROPT. The timing components should be selected such that RC/1.65 not exceed 10% of the row active time. RSTB I ReSeT Bar, static, active low reset input, clears all the shift register cells, elimi nating token content. R(n) O Row driver outputs. R(0)-R(127) are used in 128 output mode, S128=1. Only R(4)-R(123) should be connected when S128=0. HREF O High voltage REFerence is an internally generated PFET switch drive voltage (approximately five-volts less than VOH), which should be bypassed to VOH with a 2200pF external capacitor. LREF O Low voltage REFerence is an internally generated NFET switch drive voltage (approximately five-volts above GND), which should be bypassed to GND with a 2200pF external capacitor. NRMH O Test Pin, N/C NRML O Test Pin, N/C ELECTRICAL SPECIFICATION Note: positive currents flow into the part, negative currents flow out of the part. Absolute Maximum Ratings: Parameter Operating Condition Min Typ Max Units Ambient temp - -65 155 Low voltage supply - -0.3 7.0 V High voltage supply - -0.3 35.0 V o C Operating Conditions: Unless otherwise stated, all parameters are specified for the following operating conditions. Parameter Ambient temp Low voltage supply High voltage supplies Clock Frequency 6 Sym Operating Condition TA - VCC Typ Max 0 - 70 - 3.0 - 5.5 V VMAX - 5.0 - 30 V CLK - - - 100 kHz www.clare.com Min Units o C Rev. 2 Preliminary MXED202 Chip Supply Currents - Exclusive of Load Parameter Sym Operating Condition Min Typ Max Units Logic Supply, Operating IVCC VDRV>1V, fCLK<100kHz 3V<VCC<5.5V - 140 210 µA Logic Supply, Powerdown IVCC VDRV<0.3V, 3V<VCC<5.5V - 15 25 µA High Voltage Supply, Operating IVMAX VDRV>1V, fCLK<100kHz 9V<MAX<30V - 445 700 µA High Voltage Supply, Powerdown IVMAX VDRV<0.3V, 9V<MAX<30V - - 20 µA Min Typ Max Units - 0.4 V - - V Digital Inputs: SHR, SRIN, SLIN, DUAL, CLK, PCB, MONO, S128, RSTB Parameter Sym Operating Condition Input low voltage VIL - Input high voltage VIH - II - -10 - 10 µA Clock Rise Time CLKRT - - - 5 nS Clock Fall Time CLKFT - - 5 nS Clock Duty Cycle CLK% - 20 - 80 % Input current VCC-0.4 Setup Time TSet Time in advance of 10% rising edge of CLK that inputs SHR, SRIN, SLIN, DUAL, PCB, MONO, S128, CLRB must be at valid input logic levels to take effect on next clock cycle. 50 - - nS Hold Time THold Time subsequent to 90% rising edge of CLK that inputs SHR, SRIN, SLIN, DUAL, PCB, MONO, S128, CLRB must be valid to take effect on next rising edge of the clock (CLK). 50 - - nS Digital Outputs: SRIN, SLIN, ROPT Parameter Sym Operating Condition Min Typ Max Units Output low voltage VOL Iout = 200 µA - - 0.4 V Output high voltage VOH Iout = -200 µA VCC-0.4 - - V Output rise/fall time TRF 10 to 90 %, Cload = 5 pF - - 5 nS Precharge Timing Resistor connected to pin ROPT RROPT Pages 9-11 50 - 200 kΩ Rev. 2 www.clare.com 7 Preliminary MXED202 Analog Inputs: DRV, INV Parameter Sym Operating Condition Min Typ Max Units DRV Pin Input Resistance DRVRin - 10 - - kΩ DRV Pin Input Capacitance DRVCin - - - 10 pF VDRV - 1.0 - VMAX-1.5 V Feedback Resistor from VOH to INV RF - 10 - 100 kΩ Input Resistor from INV to GND RI - 10 - 100 kΩ RF / RI - 0.1 - 10 - Min Typ Max Units Voltage Range of DRV Input Gain Ratio Analog Outputs: VOH, HREF, LREF, R(n) Bypass capacitors to GND: CVOH=10µF; CHREF, CLREF =2nF Parameter Sym Precharge Voltage VOH Iout avg= 100 µA, CLOAD=1000pF 5 - 30 V Precharge Ripple VOHac Voltage Regulator Active, Iout avg= 100 µA - - 100 mV p-p Row 0-127 Output RowON Pulldown Resistance VROW < 5V (to enable OLED turn-on) - - 20 Ω Row 0-127 Output Pullup Resistance VROW > (VOH-2V) (to disable OLED turn-on) - - 300 Ω Per output - - 20 pF Row 0-127 Chip Output Capacitance 8 RowOFF CRow Operating Condition www.clare.com Rev. 2 Preliminary MXED202 PRECHARGE: (Organic) Light-Emitting Diodes are current controlled devices, their photonic output (luminance) being proportional to the time-average charge passed through them. To pass charge, the forward voltage must first reach the diode “on” threshold. In passive-matrix panel displays, OLED’s are connected in n-row x m-column matrix fashion. In the row multiplex scheme, where a single row of OLED’s is activated at a time, the parasitic capacitance of the n-1 “off” rows of OLED’s appears connected to the columns - this capacitance must be charged to the “on” threshold before current flows through the selected “on” row diodes. If the column drive current alone were to charge this capacitance, much of the allotted row time would be consumed in just reaching the “on” threshold. Therefore, to improve the efficiency of the display, and to make luminance directly proportional to column current-magnitude and currentduty cycle, the MXED102 and MXED202 Display drivers support optional voltage precharge. In all precharge options, a predetermined voltage is impressed upon the diodes. For instance, the user may configure the precharge voltage to be near the OLED “on threshold,” to bias the diodes to the onset of conduction. The Timing Diagrams, Pages 10-11, illustrate the Prechage Options: Condition Precharge PCB=1 No Precharge MONO=1 A Monochromatic Precharge voltage may be applied via the MXED202 Row Driver, as a function of CLK, PCB, MOD. During the Discharge interval, all Row and Column driver outputs are grounded, discharging all pixels. At the beginning of the Active interval, a selected Precharge Voltage is applied to all but the next active row, and the column drivers source data-driven currents. MONO=0 Color/Monochrome Precharge by the MXED102 Column Driver, as function of CLK, PCB. Rev. 2 www.clare.com 9 MXED202 Preliminary TIMING DIAGRAMS 10 www.clare.com Rev. 2 Preliminary Rev. 2 www.clare.com MXED202 11 MXED202 Preliminary VOH OPTIONS 12 www.clare.com Rev. 2 Preliminary MXED202 SEMICONDUCTOR DIE DATA SHEET The MXED202 is a common cathode (row) driver for Passive Matrix Organic Light Emitting Diode (OLED) and Polymer Light Emitting Diode (PLED, PolyLED, LEP,…etc.) displays, with anodes connected to the columns. This document specificies the physical and mechanical properties of MXED202 semiconductor die, as provided in wafer form. DIMENSIONS Die Size “X Dimensions” Center Scribe to Center Scribe: 8270 µm “Y Dimensions” Scribe to Center Scribe: 2300 µm Die Thickness Unthinned (Non Back Lapped Wafer) Thickness: 25 mil Rev. 2 www.clare.com 13 MXED202 Preliminary BONDING PADS Locations and Sizes -Driver Outputs The information contained on this page is preliminary. Although the order of the bond pad will remain the same, the XY dimensions in the final document may vary slightly. Please take this possibility into consideration when doing any chip on board layouts. 14 www.clare.com Rev. 2 Preliminary MXED202 Interface Input/Output Rev. 2 www.clare.com 15 Worldwide Sales Offices CLARE LOCATIONS EUROPE ASIA PACIFIC Clare Headquarters 78 Cherry Hill Drive Beverly, MA 01915 Tel: 1-978-524-6700 Fax: 1-978-524-4900 Toll Free: 1-800-27-CLARE European Headquarters CP Clare nv Bampslaan 17 B-3500 Hasselt (Belgium) Tel: 32-11-300868 Fax: 32-11-300890 Clare Micronix Division 145 Columbia Aliso Viejo, CA 92656-1490 Tel: 1-949-831-4622 Fax: 1-949-831-4628 France Clare France Sales Lead Rep 99 route de Versailles 91160 Champlan France Tel: 33 1 69 79 93 50 Fax: 33 1 69 79 93 59 Asian Headquarters Clare Room N1016, Chia-Hsin, Bldg II, 10F, No. 96, Sec. 2 Chung Shan North Road Taipei, Taiwan R.O.C. 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Colombo 10/A I-20066 Melzo (Milano) Tel: 39-02-95737160 Fax: 39-02-95738829 Sweden Clare Sales Comptronic AB Box 167 S-16329 Spånga Tel: 46-862-10370 Fax: 46-862-10371 United Kingdom Clare UK Sales Marco Polo House Cook Way Bindon Road Taunton UK-Somerset TA2 6BG Tel: 44-1-823 352541 Fax: 44-1-823 352797 http://www.clare.com Clare cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in this Clare product. No circuit patent licenses nor indemnity are expressed or implied. Clare reserves the right to change the specification and circuitry, without notice at any time. The products described in this document are not intended for use in medical implantation or other direct life support applications where malfunction may result in direct physical harm, injury or death to a person. Specification: DS-MXED202-R2 ©Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 5/21/01 16 www.clare.com Rev. 2