TI SN74CBTLV16292

SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
D
D
D
D
D
D
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
4-Ω Switch Connection Between Two Ports
Isolation Under Power-Off Conditions
Make-Before-Break Feature
Internal 500-Ω Pulldown Resistors to
Ground
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
S
1A
NC
2A
NC
3A
NC
GND
4A
NC
5A
NC
6A
NC
7A
NC
VCC
8A
GND
NC
9A
NC
10A
NC
11A
NC
12A
NC
description
The SN74CBTLV16292 is a 12-bit 1-of-2
high-speed FET multiplexer/demultiplexer. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
When the select (S) input is low, port A is
connected to port B1 and RINT is connected to
port B2. When S is high, port A is connected to
port B2 and RINT is connected to port B1.
The SN74CBTLV16292 is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
S
FUNCTION
L
A port = B1 port
RINT = B2 port
H
A port = B2 port
RINT = B1 port
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
NC
NC
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
logic diagram (positive logic)
54
2
1A
1B1
SW
RINT
RINT
53
SW
1B2
30
27
12B1
SW
12A
RINT
RINT
29
12B2
SW
1
S
simplified schematic, each FET switch
A
B
(OE)
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High level control input voltage
High-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low level control input voltage
Low-level
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
MIN
MAX
2.3
3.6
1.7
UNIT
V
V
2
0.7
0.8
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
II
VCC = 3 V,
VCC = 3.6 V,
II = –18 mA
VI = VCC or GND
Ioff
ICC
VCC = 0,
VCC = 3.6 V,
VI or VO = 0 to 3.6 V
IO = 0,
VI = VCC or GND
One input at 3 V,
∆ICC§
Ci
Control input
Control input
VCC = 3.6 V,
VI = 3.3 V or 0
Cio
A or B port
VO = 3.3 V or 0
VCC = 3 V
TYP‡
Other inputs at VCC or GND
MAX
UNIT
–1.2
V
±1
µA
10
µA
10
µA
300
µA
3.5
pF
22.5
VCC = 2.3
23V
V,
TYP at VCC = 2.5 V
ron¶
MIN
pF
VI = 0
II = 64 mA
II = 24 mA
5
8
5
8
VI = 1.7 V,
II = 15 mA
11
40
VI = 0
II = 64 mA
II = 24 mA
3
7
3
7
Ω
VI = 2.4 V,
II = 15 mA
7
15
‡ All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
§ This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd†
tpd‡
A or B
B or A
S
A
2.5
7.1
ten
tdis
S
B
1
5.6
PARAMETER
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.15
ns
2.5
6.7
ns
1
5
ns
S
B
1
5
1
4.5
ns
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
‡ This propagation delay was measured by observing the change of voltage on the A output introduced by static levels equal to 3-V or 0 for
3.3 V ± 0.3 V or VCC or 0 for 2.5 V ± 0.2 V on B1 and B2 to achieve the desired transition.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
DESCRIPTION
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
tmbb§
Make-before-break time
0
2
0
2
§ The make-before-break time is the time interval between make and break, during the transition from one selected port to the other.
4
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UNIT
MAX
ns
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
500 Ω
From Output
Under Test
S1
Open
GND
CL = 30 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
VCC
Output
Control
LOAD CIRCUIT
VCC/2
0V
tPLZ
tPZL
VCC
VCC/2
Input
VCC/2
0V
tPLH
VCC/2
2 × VCC/3
VCC/3
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
Output
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/3
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74CBTLV16292
LOW-VOLTAGE 12-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER
WITH INTERNAL PULLDOWN RESISTORS
SCDS055G – MARCH 1998 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
Open
500 Ω
Output
Control
(low-level
enabling)
LOAD CIRCUIT
3V
1.5 V
0V
tPZL
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
VOL
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
tPLZ
2V
1V
tPZH
VOL + 0.3 V
VOL
tPHZ
1V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
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Copyright  1999, Texas Instruments Incorporated