EMC EM19100

EM19100
EM19100
8-BIT 20
8-BITVIDEO
20 MSPS A/D
VIDEO
A/D CONVERTER
(CMOS)
MSPS
CONVERTER
(CMOS)
GENERAL DESCRIPTION
EM19100 is an 8-bit CMOS A/D converter for video use. The adoption of a 2-step parallel system achieves low
consumption at a maximum conversion speed of 20 MSPS typical.
FEATURES
•
•
•
•
•
•
•
20MSPS maximum conversion speed
Build-in sampling and hold circuit
Internal self-bias reference voltage
90mW power dissipation at 20MSPS
+5V single power supply
Available in 24 pin SOP
Series
EM19100M for 300 mil SOP
EM19100S for 209 mil SOP
APPLICATION
TV,VCR digital systems and a wide range of fields where high speed A/D conversion is required.
PIN ASSIGNMENT
EM19100
OE
DVSS
D0
D1
D2
D3
D4
D5
D6
D7
DVDD
CLK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DVSS
VRB
VRBS
AVSS
AVSS
VIN
AVDD
VRT
VRTS
AVDD
AVDD
DVDD
FUNCTIONAL BLOCK DIAGRAM
/O E
1
24
DV S S
DVS S
2
23
VRB
D0
3
22
V RBS
D1
4
21
AVSS
Reference voltage
Lower data
latches
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
Lower encoder
(4bit)
Lower
Comparators with
S/ H (4bit)
Lower encoder
(4bit)
Lower
Comparators with
S/ H (4bit)
20
AVSS
19
VI N
18
AV DD
17
V RT
16
V RT S
15
AV DD
14
AV DD
13
DV DD
Upper data
latches
Upper encoder
(4bit)
DV DD 1 1
CL K 1 2
Clock generator
* This specification are subject to be changed without notice.
Upper
Comparators with
S/ H (4bit)
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EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
OUTPUT CODING
Step
Analog Input (V)
Digital Output Code
Conditions
0
1
2
....
124
125
....
254
255
0.607815
0.607815~0.6156250
0.6156250~0.6234375
....
1.6000000~1.6078125
1.6078125~1.6156250
....
2.5843750~2.5921875
2.5921875~
00000000
00000001
00000010
....
10000000
10000001
....
11111110
11111111
VRB=0.6V
VRT=2.6V
1LSB=7.8125mV
Clock
N
Analog input
N+ 4
N+1
N+2
N-3
Data output
N- 2
N- 1
N+ 3
N
N+ 1
ABSOLUTE MAXIMUM RATINGS (TA=25°C)
Items
Supply voltage
Operating temperature
Input voltage
Ref, Input voltage
Sym.
VDD
TOPR
VIN
VRT,VRB
Rating
7
-20 to +65
VSS to VDD
VSS to VDD
(FC=20MPS,VDD=5V,VRB=0.5V,VRT=2.5V,Ta=25 deg.)
Parameter
Sym.
Conditions
Maximum Conversion Speed
FC
Vin=0.6V to 2.6V fin=1kHz ramp
Supply current
IDD
FC=20MSPS NTSC ramp wave input
Reference pin current
IREF
Analog input bandwidth
BW
VIN=1.5V+0.07Vrms
Analog input capacitance
CIN
Reference resistance
RREF
Internal bias
VRB
Short VRB and VRBS
VRT-VRB Short VRT and VRTS
Offset Voltage
EOT
EOB
Digital input voltage
VIH
VIL
Digital input current
IIH
VDD=max.
VIH=VDD
IIL
VIL=0V
* This specification are subject to be changed without notice.
Unit
V
°C
V
V
Min. Typ. Max.
20
12
17
5.7
8.0 9.1
10
11
220 250 350
0.55 0.6 0.65
1.9
2.0 2.1
-10
-35 -60
0
15
45
4.0
1.0
5
5
Unit
MSPS
mA
mA
MHz
pF
Ω
V
mV
V
uA
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EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Parameter
Digital output current
Digital output current
Sym.
IOH
IOL
IOZH
Output data delay
Integral nonlinearity
Differential nonlinearity
Differential gain error
TDL
EL
ED
DG
Differential phase error
Aperture jitter
Sampling delay
Conditions
OE=VSS,VOH=VDD-0.5V
VDD=min.
VOL=0.4V
OE=VDD,
VOH=VDD
VOL=0V
Min. Typ. Max. Unit
-1.1
mA
3.7
16
uA
16
18
30
ns
0.5 1.3 LSB
±0.3 ±0.5 LSB
FC=20MSPS VIN=0.6V to 2.6V
FC=20MSPS VIN=0.6V to 2.6V
NTSC 40 IRE mod ramp,
FC=14.3MSPS
1.0
0.5
30
4
DP
tAJ
tDS
%
deg
ps
ns
Timing
Vi(2)
Vi(1)
Vi(3)
Vi(4)
Analog input
External clock
Upper comparators
block
S(1)
S(2)
C( 1)
S(3)
C( 2)
C( 3)
S(4)
C( 4)
Upper data
MD(0)
MD(1)
MD (2 )
MD(3)
Lower reference
voltage
RV( 0)
RV(1)
RV(2)
RV( 3)
Lower comparators
A block
S(1)
H( 1)
LD (-1)
Lower data A
Lower comparators
B block
Lower data B
Digital output
H(3)
S(3)
C(1)
C (0 )
H( 0)
L D(1 )
S (2 )
LD(-2)
OUT( -2)
* This specification are subject to be changed without notice.
C( 3)
H (2 )
C (2 )
H (4 )
LD(2)
LD( 0)
OUT( -1)
S (4 )
OU T (0 )
OUT( 1)
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EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Timing explanation
EM19100 is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower
comparators groups of 4-bit each. The reference voltage that is equal to the voltage between VRT-VRB/16 is
constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through
the reference supply to the lower data. VRTS and VRBS pins serve for the self generation of VRT (Reference
voltage top) and VRB(Reference voltage bottom).
This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the
following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is
input sampling (auto zero) mode, input hold mode and comparison mode.
The operation of respective parts is as indicated in the chart. For instance input voltage Vi(1) is sampled with the
falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The
upper comparators block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously
the reference supply generates the lower reference voltage RV(1) that corresponded to the upper results. The
lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and
LD(1) are combined and output as Out(1) with the rising edge the 3rd clock. Accordingly there is a 2.5 clock delay
from the analog input sampling point to the digital data output.
Application Note
VDD,VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND’s.
Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits
Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT
and VRTS, VRB and VRBS, the self bias function that generates VRT=2.6V and VRB=0.6V, is activated.
Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and
* This specification are subject to be changed without notice.
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EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.
OE pin
By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.
About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply. This is to avoid latch up
due to the voltage difference between AVDD and DVDD pins when power is ON.
* This specification are subject to be changed without notice.
1.26.1996
5
EM19100
8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)
Application Circuit
U2
U2
U3
* This specification are subject to be changed without notice.
1.26.1996
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