SONY CXD1172AM

CXD1172AM/AP
6-bit 20MSPS Video A/D Converter (CMOS)
Description
CXD1172AM/AP is a 6-bit CMOS A/D converter for
video use. The adoption of a 2-step parallel system
achieves low consumption at a maximum conversion
speed of 20MSPS minimum, 35MSPS typical.
Features
• Resolution: 6-bit ± 1/2LSB
• Max. sampling frequency: 20MSPS
• Low power consumption: 40mW (at 20MSPS typ.)
(Reference current excluded)
• Built-in sampling and hold circuit.
• 3-state TTL compatible output.
• Power supply: 5V single
• Low input capacitance: 4pF
• Reference impedance: 250Ω (typ.)
CXD1172AP
16 pin DIP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
7
V
• Supply voltage VDD
• Reference voltage
VRT, VRB VDD + 0.5 to VSS – 0.5 V
• Input voltage
VIN
VDD + 0.5 to VSS – 0.5 V
(Analog)
• Input voltage
VCLK
VDD + 0.5 to VSS – 0.5 V
Applications
TV, VCR digital systems and a wide range of fields
where high speed A/D conversion is required.
Structure
Silicon gate CMOS monolithic IC
CXD1172AM
16 pin SOP (Plastic)
(Digital)
• Output voltage VOH, VOL VDD + 0.5 to VSS – 0.5 V
(Digital)
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage AVDD, AVSS 4.75 to 5.25
V
DVDD, DVSS 4.75 to 5.25
V
• Reference input voltage
VRB
0 to 4.1
V
VRT
0.9 to 5.0
V
VRT – VRB
0.9 to AVDD
V
• Analog input voltage
VIN
VRB to VRT
V
• Clock pulse width
TPW1, TPW0 23ns (min.) to 1.1µs (max.)
• Operating temperature
Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89320C78-PS
CXD1172AM/AP
Block Diagram and Pin Configuration
Reference voltage
16 AVSS
D0 1
D1 2
D2 3
Lower data
latchs
15 DVDD
Lower
Sampling comparators
(3BIT)
Lower encoder
(3BIT)
14 AVDD
13 VRB
D3 4
D4 5
D5 6
Lower
Sampling comparators
(3BIT)
Lower encoder
(3BIT)
12 VIN
11 VRT
Upper data
latchs
CLK 7
10 AVDD
Upper
Sampling comparators
(3BIT)
Upper encoder
(3BIT)
9
DVDD
DVSS 8
Clook generator
Pln Description and Equivalent Circuits
No.
Symbol
Description
Equivalent Circuit
Di
1 to 6
D0 (LSB) to D5 (MSB) output
D0 to D5
DVDD
7
CLK
Clock input
7
DVSS
8
DVSS
Digital GND
9, 15
DVDD
Digital +5V
10, 14
AVDD
Analog +5V
11
VRT
AVDD
13
11
13
Reference voltage (Top)
VRB
Reference voltage (Bottom)
AVSS
AVDD
12
VIN
Analog input
12
AVSS
16
Analog GND
AVSS
–2–
CXD1172AM/AP
Input signal
voltage
Step
Digital output code
MSB
LSB
VRT
0
..............
1 1 1 1 1 1
...
...
31
32
1 0 0 0 0 0
0 1 1 1 1 1
...
...
Digital Output
Compatibility between Analog input voltage and the digital output code is indicated in the chart below.
VRB
63
0 0 0 0 0 0
TPW1
TPW0
Clock
Analog input
Data output
N
N+1
N–3
N+2
N–2
N–1
Td = 18ns
N+3
N
N+4
N+1
: Point for analog signal sampling.
Timing Chart 1
–3–
CXD1172AM/AP
Electrical Characteristics
(VDD = 5V, VRB = 1.0V, VRT = 2.0V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
20
MSPS
Conversion speed
Fc
VDD = 4.75 to 5.25V
Ta = –20 to +75°C
VIN = 1.0 to 2.0V
fIN = 1kHz ramp
Supply current
IDD
Fc = 20MSPS
NTSC ramp wave input
Reference pin current
IREF
Analog input band width
(–1dB)
BW
Envelope
18
MHz
Analog input capacitance
CIN
VIN = 1.5V + 0.07Vrms
4
pF
Reference resistance
(VRT to VRB)
RREF
Offset voltage∗1
Digital input voltage
Digital input current
Digital output current
0.5
7
12
4
5.7
mA
3
175
250
325
EOT
Potential difference to VRT
0
–20
–40
EOB
Potential difference to VRB
15
35
55
VIH
VDD = 4.75 to 5.25V
Ta = –20 to +75°C
4.0
VIL
IIH
IIL
VDD = max.
IOH
IOL
Output data delay
TDL
Integral non-linearity error
EL
VDD = min.
V
5
VIL = 0V
5
VOH = VDD + 0.5V
–1.1
VOL = 0.4V
3.7
ED
Differential gain error
DG
Differential phase error
DP
Aperture jitter
Sampling delay
µA
mA
18
30
±0.3
±0.5
End point
Differential non-linearity
error
mV
1.0
VIH = VDD
With TTL 1 gate and 10pF load
Ta = –20 to +75°C
VDD = 4.75 to 5.25V
Ω
ns
LSB
±0.3
±0.5
1.0
%
1.0
deg
Taj
40
ps
Tsd
4
ns
NTSC 40 IRE mod ramp
Fc = 14.3MSPS
∗1 The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
drops equivalent to 1/2 LSB of the voltage when the output data changes from "00000000" to "00000001".
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2 LSB of the voltage when the output data changes from "11111111" to "11111110".
–4–
CXD1172AM/AP
Electrical Characteristics Test Circuit
}
Integral non-linearity error
Differential non-linearity
Offset voltage
Test Circuit
+V
S2
S1 : ON IF A < B
S2 : ON IF B > A
S1
–V
VIN
CXD1172A
A<B
A>B
COMPARATOR
A6
B6
to
to
A1
B1
B0
A0
6
“0”
DVM
6
BUFFER
“1”
6
CLK (20MHz)
000 … 00
to
111 … 0
CONTROLLER
Maximum operational speed
Differential gain error
Differential phase error
}
Test Circuit
2.0V
ERROR RATE
FC – 1kHz
CX20202A-1
S. G.
H. P. F
1.0V
1
VIN
AMP
2
IAE
NTSC
SIGNAL
SOURCE
100
40 IRE
MODULATION
6
TTL
ECL
1
6
10bit
D/A
620
2
2.0V
VECTOR
SCOPE
CLK
–5.2V
BURST
0
–40
S. G.
(CW)
CXD
1172A
D. G
D. P
1.0V
SYNC
620
TTL
–5.2V
FC
ECL
Digital output current test circuit
2.0V
VRT
VIN
1.0V
VRB
VCC
CLK
IOL
VOL
2.0V
VRT
VIN
1.0V
VRB
VCC
CLK
+
–
IOH
VOH
+
–
GND
GND
–5–
COUNTER
CXD1172AM/AP
Timing Chart 2
Vi (2)
Vi (1)
Vi (3)
Vi (4)
Analog input
External clock
Upper comparators block
S (1)
Digital output
S (3)
H (1)
C (3)
C (1)
C (0)
RV (3)
S (3)
H (3)
C (3)
LD (1)
S (2)
LD (–2)
Out (–2)
C (4)
MD (3)
RV (2)
LD (–1)
H (0)
S (4)
MD (2)
RV (1)
S (1)
Lower data A
Lower data B
C (2)
MD (1)
RV (0)
Lower reference voltage
Lower comparators B block
S (2)
MD (0)
Upper data
Lower comparators A block
C (1)
H (2)
C (2)
–6–
H (4)
LD (2)
LD (0)
Out (–1)
S (4)
Out (0)
Out (1)
CXD1172AM/AP
Operation (See Block Diagram and Timing Chart)
1. CXD1172AM/AP is a 2-step parallel system A/D converter featuring a 3-bit upper comparators group and 2
Iower comparators groups of 3-bit each. The reference voltage that is equal to the voltage between VRTVRB/8 is constantly applied to the upper 3-bit comparator block. Voltage that corresponded to the upper
data is fed through the reference supply to the lower data.
2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features
the following operating modes which are respectively indicated on the timing chart with S, H, C symbols.
That is input sampling (auto zero) mode, input hold mode and comparison mode.
3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled with
the falling edge of the first clock by means of the upper comparator block and the Iower comparator A block.
The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.
Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to the
upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the
second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Operation Notes
1. VDD, Vss
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass to the
respective GND's.
2. Analog input
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.
However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.
When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be
prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals,
separate it from other circuits.
4. Reference input
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained.
5. Timing
Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and
with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.
6. About latch up
It is necessary that AVDD and DVDD pins be the common source of power supply.
This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.
See "For latch up prevention" of CXD1172P/CXA1106P PCB description. (Page 6, 7)
–7–
CXD1172AM/AP
Latch Up Prevention
The CXD1172A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pins 10 and 14) and DVDD (Pins 9 and 15), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
DVDD
AVDD
10
9
14
AVDD
+5V
+5V
15
DVDD
C14
C6
CXD1172A
AVSS
DIGITAL IC
DVSS
16
8
AVSS
DVSS
b. When analog and digital supplies are from a common source
(i)
DVDD
10
9
14
AVDD
15
DVDD
C14
+5V
CXD1172A
C6
AVSS
DIGITAL IC
DVSS
16
8
AVSS
DVSS
(ii)
DVDD
10
9
14
AVDD
15
DVDD
C14
+5V
DIGITAL IC
CXD1172A
C6
AVSS
DVSS
16
8
AVSS
DVSS
–8–
CXD1172AM/AP
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
DVDD
AVDD
10
9
14
AVDD
+5V
+5V
C6
15
DVDD
DIGITAL IC
CXD1172A
DVSS
AVSS
16
AVSS
8
DVSS
b. When analog and digital supplies are from common source
(i)
DVDD
AVDD
10
9
14
AVDD
15
DVDD
+5V
DIGITAL IC
CXD1172A
C6
AVSS
DVSS
16
AVSS
8
DVSS
(ii)
DVDD
AVDD
10
9
14
AVDD
15
DVDD
+5V
DIGITAL IC
CXD1172A
AVSS
DVSS
16
8
AVSS
DVSS
–9–
CXD1172AM/AP
6-bit, 20MSPS ADC and DAC Evaluation Board
Silk Side
Analog
VR5
C8
Q5
C5
VR1
C7
R5
VR2
R2
R7
D6 D7
CLK
C6
R1 C3
Q3
R8
C14
R6
Analog
A.GND
C11 C12
OSC
Q2
74HC04
C4
Q1
R3
74S174
CLK
AGND
R4
D1172P
Q4
C1
S IN
74S174
D6 D4 D2
R10
VR4
D0 D1 D2 D3 D4 D5
R9
C2
Logic
VR3
A1106P
C10
DA OUT
D7 D5 D3 D1 D0
C9
C13
SW
DVDD
AVDD
GND
+5V
–5V
R11
D.GND
Component Side
2
1
Soldering Side
3
– 10 –
CLK IN
CXD1172AM/AP
Package Outline
Unit: mm
CXD1172AM
16PIN SOP (PLASTIC) 300mil
+ 0.4
9.9 – 0.1
+ 0.4
1.85 – 0.15
16
9
6.9
8
+ 0.1
0.2 – 0.05
1.27
0.45 ± 0.1
0.5 ± 0.2
1
+ 0.2
0.1 – 0.05
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
± 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
∗SOP016-P-0300-A
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE WEIGHT
0.2g
JEDEC CODE
CXD1172AP
16
+ 0.3
6.4 – 0.1
+ 0.4
19.2 – 0.1
+ 0.1
0.05
0.25 –
16PIN DIP (PLASTIC)
7.62
9
1
0° to 15°
8
+ 0.4
3.7 – 0.1
3.0 MIN
0.5 MIN
2.54
0.5 ± 0.1
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
DIP-16P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
DIP016-P-0300
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
Similar to MO-001-AE
PACKAGE MASS
1.0 g
SONY CODE
– 11 –