SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 D D D D D Designed to be Used in Voltage-Limiting Applications 6.5-Ω On-State Connection Between Ports A and B Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing Direct Interface With GTL+ Levels Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DBQ), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) GND A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 description 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 GATE B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 The SN74TVC3010 provides 11 parallel NMOS pass transistors with a common gate. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device can be used as a 10-bit switch with the gates cascaded together to a reference transistor. The low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to protect components with inputs that are sensitive to high-state voltage-level overshoots. (See Application Information in this data sheet.) All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can be used as the reference transistor. Since, within the device, the characteristics from transistor-to-transistor are equal, the maximum output high-state voltage (VOH) will be approximately the reference voltage (VREF), with minimum deviation from one output to another. This is a large benefit of the TVC solution over discrete devices. Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the low-voltage side, and the I/O signals are bidirectional through each FET. The SN74TVC3010 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 simplified schematic GATE B1 B2 B3 B4 B11 24 23 22 21 20 13 1 2 3 4 5 12 GND A1 A2 A3 A4 A11 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input/output voltage range, VI/O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN TYP MAX UNIT VI/O VGATE Input/output voltage 0 5 V GATE voltage 0 5 V IPASS TA Pass-transistor current 64 mA 85 °C 20 Operating free-air temperature –40 application operating conditions (see Figure 2) 2 VBIAS VREF BIAS voltage VDPU IPASS Drain pullup voltage IREF TA Reference-transistor current Reference voltage MIN TYP 3 3.3 3.6 V 1.5 1.635 V 2.36 2.5 2.64 V 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 1.365 Pass-transistor current Operating free-air temperature MAX 14 mA 5 µA 85 °C SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VBIAS = 0, IREF = 5 mA, VDPU = 2.625 V, VOL Ci(GATE) Cio(OFF) Cio(ON) ron‡ II = –18 mA VREF = 1.365 V, RDPU = 150 Ω, MIN TYP† VS = 0.175 V, (see Figure 1) MAX UNIT –1.2 V 350 mV VI = 3 V or 0 VO = 3 V or 0 24 4 12 pF VO = 3 V or 0 IREF = 5 mA, VDPU = 2.625 V, 12 30 pF 12.5 Ω VREF = 1.365 V, RDPU = 150 Ω, VS = 0.175 V, (see Figure 1) pF † All typical values are at TA = 25°C. ‡ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, VDPU = 2.36 V to 2.64 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 0 4 0 4 UNIT ns 3 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VDPU 3.3 V Motherboard Interface 200 kΩ GATE 24 RDPU = 150 Ω RDPU = 150 Ω RDPU = 150 Ω RDPU = 150 Ω B1 (VBIAS) 23 B2 22 B3 21 B4 20 B11 13 2 A1 (VREF) 3 A2 (VS) 4 A3 (VS) 5 A4 (VS) 12 A11 (VS) TVC3010 1 Open-Drain Test Interface TESTER CALIBRATION SETUP (see Note D) 2.5 V Input GATETester 1.25 V 1.25 V 0V tPLHREF tPHLREF 2.5 V Output Reference 1.25 V 1.25 V VOL tPLHDUT tPHLDUT 2.5 V Output Device Under Test 1.25 V 1.25 V VOL tPLH (see Note E) tPHL (see Note F) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. B. C. D. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. The outputs are measured one at a time with one transition per measurement. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point. tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test. E. tPLH = tPLHDUT – tPLHREF F. tPHL = tPHLDUT – tPHLREF Figure 1. Tester Calibration Setup and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 APPLICATION INFORMATION TVC background information In personal computer (PC) architecture there are industry-accepted bus standards. These standards define, among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate with existing bus infrastructure. Providing an evolutionary upgrade path is important in the design of PC architecture, but the existing bus standards must be preserved. To achieve the ever-present needs for smaller, faster, lighter devices that draw less power, yet have faster performance, most new high-performance digital integrated circuits are being designed and produced with advanced submicron semiconductor process technologies. These devices have thin gate-oxide or short channel lengths and very low absolute-maximum voltages that can be tolerated at the inputs/outputs (I/Os) without causing damage. In many cases, the I/Os of these devices are not tolerant of the high-state voltage-levels on the pre-existing buses with which they must communicate. Therefore, the need arose for protection of the I/Os of devices by limiting the I/O voltages. The Texas Instruments (TI) Translation Voltage Clamp (TVC) family was designed for the specific application of protecting sensitive I/Os (see Figure 2). The information in this data sheet describes the I/O protection application of the TVC family and should enable the design engineer to successfully implement an I/O protection circuit utilizing the TI TVC solution. Low-Voltage I/O Device TVC Family Voltage-Clamp Device Standard-Voltage I/O Bus Figure 2. Thin Gate-Oxide Protection Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The VBIAS input is connected through a pullup resistor (typically, 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS is recommended. The opposite side of the reference transistor is used as the reference voltage (VREF) connection. The VREF input must be less than VDD – 1 V to bias the reference transistor into conduction. The reference transistor regulates the gate voltage (VG) of all the pass transistors. VG is determined by the characteristic gate-to-source voltage difference (VGS) because VG = VREF + VGS. The low-voltage side of the pass transistors has a high-level voltage limited to a maximum of VG – VGS, or VREF. 3.3 V Motherboard Interface 2.5 V 200 kΩ 150 Ω GATE† 48 B1 (VBIAS)† 47 150 Ω 150 Ω 150 Ω 46 45 44 25 3 4 5 24 TVC16222 1 2 A1 (VREF)† Open-Drain CPU Interface † VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS. Figure 3. Typical Application Circuit 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 APPLICATION INFORMATION electrical characteristics The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in Figures 5 and 6, show the current through a pass transistor, versus the voltage at the source for different reference voltages. The plots of the dc characteristics clearly reveal that the device clamps at the desired reference voltage for the varying device environments. Figure 5 shows the V-I characteristics, with low reference voltages and a reference-transistor drain-supply voltage of 3.3 V. To further investigate the spread of the V-I characteristic curves, VREF was held at 2.5 V and IREF was increased by raising VDDREF (see Figure 6). The result was a tighter grouping of the V-I curves. VDDREF GATE VDDPASS RDREF RDPASS VBIAS VDPASS VREF VSPASS Figure 4. TI SPICE Simulation Schematic and Voltage-Node Names POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 I PASS – Pass Current – mA APPLICATION INFORMATION VREF = 1 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS – Pass Current – mA VSPASS – Low Reference Voltage – V VREF = 1.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS – Pass Current – mA VSPASS – Low Reference Voltage – V VREF = 2 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 VSPASS – Low Reference Voltage – V Figure 5. Electrical Characteristics at Low VREF Voltages 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2.8 3.2 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 I PASS – Pass Current – mA APPLICATION INFORMATION VREF = 2.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS – Pass Current – mA VSPASS – Low Reference Voltage – V VREF = 2.5 V VDDREF = 4 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS – Pass Current – mA VSPASS – Low Reference Voltage – V VREF = 2.5 V VDDREF = 5 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V –2 –4 –6 –8 –10 –12 –14 –16 Weak Nominal Strong –18 –20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 VSPASS – Low Reference Voltage – V Figure 6. Electrical Characteristics at VREF = 2.5 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74TVC3010 10-BIT VOLTAGE CLAMP SCDS088A – APRIL 1999 – REVISED JUNE 1999 APPLICATION INFORMATION features and benefits The TVC family has several features that benefit a system designer when implementing a sensitive I/O protection solution. Table 1 lists these features and their associated benefits. Table 1. Features and Benefits FEATURES BENEFITS Any FET can be used as the reference transistor Ease of layout All FETs on one die, tight process control Very low spread of VO relative to VREF No active control logic (passive device) No logic power supply (VCC) required Flow-through pinout Ease of trace routing Devices offered in different bit-widths and packages Optimizes design and cost effectiveness Designer flexibility with VREF input Allows migration to lower-voltage I/Os without board redesign conclusion The TI TVC family provides the designer with a solution for protection of circuits with I/Os that are sensitive to high-state voltage-level overshoots. The flexibility of TVC enables a low-voltage migration path for advanced designs to align with industry standards. frequently asked questions (FAQ) 1. Q: Can any of the transistors in the array be used as the reference transistor? A: Yes, any transistor can be used as long as its VBIAS pin is connected to the GATE pin. 2. Q: In the recommended operating conditions table of the data sheet, the typical VBIAS is 3.3 V. Should VBIAS be equal to or greater than VREF on the reference transistor? A: VBIAS is a variable that is determined by VREF. VBIAS is connected to VDD through a resistor to allow the bias voltage to be controlled by VREF. VDD can be as high as 5.5 V. VREF needs to be at least 1 V less than VBIAS on the reference transistor. 3. Q: Do both A and B ports have 5-V I/O tolerance or is 5-V I/O tolerance provided only on the low-voltage side? A: Both ports are 5-V tolerant. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated