TI MSP58C20

MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
D
D
D
D
D
D
D
D
Analog Portion of ADC and DAC for
Audio-Band Signal-Processing
Applications
5-V Supply Voltage
Oversampling Second-Order Sigma-Delta
Modulator
1.024-MHz Master Clock Frequency
On-Chip Continuous-Time Antialiasing and
Smoothing Filters
High-Performance Fully Differential and
Symmetrical Analog Data Paths
Internal Reference Voltage and
Common-Mode Bias Voltage Generation
Very Low Power Consumption Mode
DW PACKAGE
(TOP VIEW)
VSUB
NC
VSS
AIP
AIM
PWAD
PWDA
ADOUT
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
NC
AOP
AOM
DIGS
DIGL
ADCLK
VDD
NC
NC
NC – No internal connection
description
The MSP58C20 is the analog portion of an audio-band sigma-delta analog-to-digital and digital-to-analog
converter and is a companion part to the MSP58C80. The MSP58C20 is designed to operate only with the
MSP58C80, which contains the digital portion of the audio-band converter. The circuit consists of three main
blocks: the analog-to-digital converter (ADC), the digital-to-analog converter (DAC), and internal reference and
bias voltages.
The analog-to-digital conversion chain consists of a continuous-time antialiasing stage, an analog oversampled
modulator, and the modulator bias voltage. The antialiasing stage is a second-order low-pass filter with a cutoff
frequency of typically 190 kHz. The modulator is a sigma-delta feedback loop, which oversamples the signal
at 1.024 MHz and provides second-order noise shaping. It performs the conversion of the differential analog
input signal to a pulse-density-modulated single-bit digital output (ADOUT). When a maximum positive
differential input voltage (i.e., a maximum positive voltage difference of AIP – AIM) is applied at the AIP and AIM
inputs, the resulting code at the ADOUT output is all ones.
The digital-to-analog conversion chain consists of a fast DAC, an analog low-pass filter, and the filter’s bias
voltage. The two input bits (DIGS and DIGL), sampled at 0.512 MHz from a digital modulator on the MSP58C80,
are the inputs of the DAC conversion chain. Based on the values for DIGS (the sign bit) and DIGL (the level bit),
the following table shows the DAC voltage steps that are produced.
DIGS
DIGL
DAC VOLTAGE STEPS
L
L
–1 × Vref
L
H
H
L
–2 × Vref
+1 × Vref
H
H
+2 × Vref
When DIGS = L, the AOM analog output has a more positive voltage than AOP. When DIGL = H, the absolute
value of the voltage difference between AOP and AOM is greater than when DIGL = L. A band-gap voltage
source is used to produce the DAC and ADC reference voltages. These two references are different to avoid
crosstalk between the two converters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
functional block diagram
ADCLK
AIP
AIM
Antialiasing
Filter
PWAD
1.024 MHz
Analog
Sigma-Delta 2
Modulator
1.024 MHz
ADOUT
ADC Band-Gap
Reference Voltage
Source
VSS
Bias
VDD
DAC Band-Gap
Reference
Voltage Source
AOP
AOM
Smoothing
Filter
Low-Pass
Filter
DIGS
512 kHz
DIGL
MSP58C20
VSUB
2
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PWDA
• DALLAS, TEXAS 75265
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
Terminal Functions
TERMINAL
NAME
NO.
A/D
I/O
DESCRIPTION
ADCLK
14
D
I
ADCLK is a 1.024-MHz clock input.
ADOUT
8
D
O
ADOUT is the 1-bit output of the ADC modulator and is sampled at 1.024 MHz.
AIM
5
A
I
AIM is a negative differential input for the ADC. AIP and AIM together form a balanced differential input.
The biasing of this terminal is fixed through resistors by the internal common-mode voltage source. This
terminal can be ac coupled or dc coupled. If the terminal is dc coupled, external common-mode bias
should satisfy recommended operating conditions.
AIP
4
A
I
AIP is a positive differential input for the ADC. AIP and AIM together form a balanced differential input.
The biasing of this terminal is fixed through resistors by the internal common-mode voltage source. This
terminal can be ac coupled or dc coupled. If the terminal is dc coupled, external common-mode bias
should satisfy recommended operating conditions.
AOM
17
A
O
AOM is a negative differential DAC output. AOP and AOM together form a balanced differential output.
The common-mode voltage at this terminal is fixed by the internal common-mode circuitry.
AOP
18
A
O
AOP is a positive differential DAC output. AOP and AOM together form a balanced differential output.
The common-mode voltage at this terminal is fixed by the internal common-mode circuitry.
DIGL
15
D
I
DIGL is the input level bit of the DAC and is sampled at 0.512 MHz.
DIGS
16
D
I
DIGS is the input sign bit of the DAC and is sampled at 0.512 MHz.
PWAD
6
D
I
When PWAD is high, it puts the ADC part of the circuit into a power-down mode. When both PWAD and
PWDA are high, the MSP58C20 is in a stable low-power-consumption state.
PWDA
7
D
I
When PWDA is high, it puts the DAC part of the circuit in a power-down mode. When both PWAD and
PWDA are high, the MSP58C20 is in a stable low-power-consumption state.
VSUB
1
n/a
n/a
VSUB and VSS must be connected together to minimize substrate currents during power up, power down,
and normal operation.
13
n/a
n/a
3
n/a
n/a
VDD is the 5-V power supply.
VSS is ground. The internal band-gap voltage and the common-mode bias voltages are referenced to
VSS.
VDD
VSS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6 V
Input voltage range, VI (any digital or analog input, see Note 1) . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V
VSUB, VSS voltage range, relative to each other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 mV to 30 mV
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS unless otherwise noted.
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3
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
recommended operating conditions
Supply voltage, VDD (see Note 1)
High-level input voltage, digital inputs, VIH (see Note 1)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
Low-level input voltage, digital inputs, VIL (see Note 1)
Maximum differential input voltage between AIP and AIM (ac or dc peak-to-peak voltage), VID
Common-mode input voltage at AIP and AIM, VIC (see Note 1)
0.8
V
–3
3
V
0.45 ×
VDD
0.5 × 0.55 ×
VDD
VDD
V
Input clock frequency, ADCLK
1.024
Resistive load between AOP and AOM
Capacitive load at AOP and AOM (at each output versus VSS)
Operating free-air temperature, TA
0
NOTE 1: All voltage values are with respect to VSS unless otherwise noted.
4
MHz
15
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kΩ
50
pF
70
°C
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode)
(unless otherwise noted)
supply current characteristics
PARAMETER
IDD
TEST CONDITIONS
MIN
TYP
PWAD =H,,
PWDA = H,,
Digital inputs = VDD or VSS,
Digital output = no load
Supply current
PWAD = L,
PWDA = L
MAX
UNIT
50
µA
µ
mA
6.5
9
16
MIN
TYP
MAX
UNIT
± 2.36
± 2.5
V
150
mV
0.4 ×
VDD
0.5 ×
VDD
0.6 ×
VDD
V
analog input characteristics
PARAMETER
VIO
VIC
zi
TEST CONDITIONS
Transmit dynamic range, maximum differential
input voltage (between AIP and AIM)
dc or ac voltage
± 2.22
Transmit differential input offset voltage
See Note 2
– 150
Internal common-mode voltage at AIP and AIM
AIP
Between AIP and internal common-mode
voltage source (AIM = VDD/2)
15
25
35
AIM
Between AIM and internal common-mode
voltage source (AIP = VDD/2)
15
25
35
AIP
Measured at 5 MHz between AIP and VSS
(AIM = VDD /2)
50
AIM
Measured at 5 MHz between AIM and VSS
(AIP = VDD /2)
50
Input impedance
Input capacitance
kΩ
pF
NOTE 2: Calculated by linear regression based on five dc measurements between –1 V and 1 V
digital output characteristics
PARAMETER
VOH
VOL
Digital high-level output voltage versus VSS
Digital low-level output voltage versus VSS
TEST CONDITIONS
MIN
IOH = 300 µA
IOL = 1 mA
2.4
TYP
MAX
UNIT
V
0.4
V
analog output characteristics
PARAMETER
TEST CONDITIONS
VOD
VOO
Differential output voltage, dynamic range, AOP to AOM
Balanced loads,
Differential output offset voltage
dc measurement
VOC
Common-mode output voltage at AOP and AOM
POST OFFICE BOX 655303
dc measurement
MIN
TYP
MAX
± 2.82
±3
± 3.18
– 150
0.4 ×
VDD
• DALLAS, TEXAS 75265
0.5 ×
VDD
UNIT
V
150
mV
0.6 ×
VDD
V
5
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode)
(unless otherwise noted) (continued)
ADC transmit characteristics†
PARAMETER
MIN
TYP
MAX
UNIT
± 0.5
dB
VDD = 5 V,
TA = 25°C,
Input = 1-kHz sine wave at – 13 dBrl
Input = 1-kHz sine wave,
G i reference
Gain
f
llevell = gain
i
measured at in
input
ut level of
–13 dBrl,
See Note 3
Input level = – 1 dBrl to – 43 dBrl
± 0.25
Transmit
T
it gain
i versus
in
ut level
input
Input level = – 43 dBrl to – 53 dBrl
± 0.5
Input level = – 53 dBrl to – 58 dBrl
±1
Transmit g
gain versus
supply voltage
VDD = 4
4.75
75 V to 5
5.25
25 V
V,
Input = 1 kHz at – 13 dBrl
Transmit idle channel
in-band noise
Psophometrically-weighted output noise,
Transmit channel idle
Transmit idle channel
single-frequency noise
spectrum (see Note 4)
Ilkg
lk
TEST CONDITIONS
Transmit absolute gain
tolerance
TA = 25
25°C,
C,
FFT rectangular window bandwidth = 125 Hz,
Transmit channel idle,
See Figure 5
± 0.15
0 15
– 76
f = 50 Hz
– 80
f = 300 Hz
– 82
f = 3.4 kHz
– 82
f = 4 kHz
– 80
f = 7 kHz
– 72
f = 12 kHz
– 65
f = 20 kHz
– 64
dB
dB
dBrlp
dBrl
Transmit singlefrequency distortion
Input = one frequency in 0.7-kHz to 1.1-kHz band at – 4 dBrl,
Measured first two harmonics
– 50
dB
Transmit intermodulation
distortion (see Note 4)
Input = two frequencies in 0.3-kHz to 3.4-kHz band,
Input levels = – 7 dBrl and – 24 dBrl,
Measured second and third intermodulation products
– 40
dBrl
Input level = – 70 dBrl
– 13
Transmit signal to total
Transmit-signal-to-totalnoise-plus-distortion ratio
(see Note 5)
VDD = 5.25 V,
TA = 25°C,,
Input = 1-kHz sine wave,
Measured psophometricallyy
weighted total noise plus
distortion,
See Figure 6
Input level = – 20 dBrl
50
Input level = –1 dBrl
50
Transmit gain variations
versus input frequency
(see Notes 4 and 6)
f = 0.1 kHz to 4 kHz,
Input level = – 13 dBrl
Transmit power supply
rejection
See Note 7
Leakage current
Voltage
g applied to terminal is between VSS and VDD,
PWDA = H (power-down mode)
Receive-to-transmit
crosstalk
Receive input = one frequency in 0.3-kHz to 3.4-kHz band at – 3 dBrl,
Crosstalk measured at transmit digital output,
Transmit channel idle
dB
± 0.6
30
dB
dB
AIP
– 10
10
AIM
–10
10
– 70
µA
dB
† This table contains specifications in which the power levels are expressed in dBrl; dBrl stands for dB above reference level. 0 dBrl is the ADC
theoretical overload point. This overload point corresponds to a sine wave at the input of the modulator with peak amplitude equal to 2.25 V dBrlp
is a psophometrically-weighted value being compared against a psophometrically-weighted reference.
NOTES: 3. Input satisfies CCITT G.714 15.3, Method 2.
4. This parameter is characterized but not tested.
5. Input satisfies CCITT G.714 14.3, Method 2.
6. Gain is relative to gain at 1 kHz.
7. The power-supply rejection measurement is made with a 50-mVrms, 0- to 20-kHz signal applied to VDD and with the transmit channel
idle.
6
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MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode)
(unless otherwise noted) (continued)
DAC receive characteristics†
PARAMETER
TEST CONDITIONS
Receive gain tolerance
VDD = 5 V,
TA = 25°C,
Input = 1-kHz sine wave at – 28 dBrl
Receive gain versus input level
Input = 1-kHz sine wave,
G i reference
Gain
f
llevell = gain
i
measured at input
in ut level of –28 dBrl,
See Note 8
MIN
TYP
MAX
UNIT
± 0.5
dB
Input level = – 1 dBrl to – 43 dBrl
± 0.25
Input level = – 43 dBrl to – 53 dBrl
± 0.5
Input level = – 53 dBrl to – 58 dBrl
±1
dB
Receive gain versus
supply voltage
VDD = 4.75 V to 5.25 V,
Digital input = 1-kHz sine wave at – 28 dBrl
Receive idle channel in-band
noise
Receive channel idle,
Psophometrically-weighted output noise
Receive idle channel
single-frequency
single frequency noise
sspectrum
ectrum (see Note 4)
TA = 25°C
25°C,
Receive channel idle,,
Measurement bandwidth = 125 Hz,
See
Figure 6
S Fi
Receive single-frequency
distortion
Input = one frequency in 0.7-kHz to 1.1-kHz band at – 6 dBrl,
Measured first two harmonics
– 50
dB
Receive intermodulation
distortion (see Note 4)
Input = two frequencies in 0.3-kHz to 3.4-kHz band,
Input levels = – 7 dBrl and – 24 dBrl,
Measured second and third intermodulation products
– 40
dBrl
Receive signal-to-total-noiseplus-distortion ratio
(see Note 9)
VDD = 5.25 V, TA = 25°C,
Input
In
ut = 1-kHz sine wave,
wave
Measured psophometricallyweighted total noise plus
distortion,
See Figure 7
– 82
f = 3 kHz
– 82
f = 10 kHz
– 64
f = 100 kHz
– 64
Input level = –70 dBrl
0
Input level = –20 dBrl
50
Input level = –1 dBrl
50
dBrl
dB
0.6
– 0.7
– 0.4
f = 6.25 kHz
– 1.75
– 1.4
f = 7.8125 kHz
– 3.35
– 2.9
f = 9.375 kHz
– 5.25
– 4.8
f = 10.9375 kHz
– 7.25
– 6.8
f = 12.5 kHz
f = 15.625 kHz
dB
dBrlp
– 0.6‡
f = 4.6875 kHz
VDD = 4.75 V, TA = 25°C,
In
ut level = –13 dBrl,
Input
dBrl
See Figure 9
– 75
f = 100 Hz
f = 156 Hz to 4 kHz
Receive gain variations versus
in
ut sine wave frequency
input
(see Note 6)
± 0.15
– 9.2
– 8.7
– 12.8
– 12.2
dB
Receive power supply rejection See Note 10
30
dB
† This table contains specifications in which the power levels are expressed in dBrl; dBrl stands for dB above reference level. 0 dBrl is the DAC
overload point. Overload levels of the digital modulator (see parameter measurement information) are 32767 and – 32767 peak values. The 0-dBrl
level is related to maximum differential output voltage, which is typically 2.25 V.
‡ The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for receive gain
variations versus input sine-wave frequency.
NOTES: 4. This parameter is characterized but not tested.
6. Gain is relative to gain at 1 kHz.
8. Input satisfies CCITT G.714 15.4 Method 2.
9. Input satisfies CCITT G.714 14.4 Method 2.
10. The power supply rejection measurement is made with a 50-mVrms, 0-kHz to 20-kHz signal applied to VDD and with the receive
channel idle.
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7
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, ADCLK input frequency = 1.024 MHz, PWDA = L and PWAD = L (power-up mode)
(unless otherwise noted) (continued)
DAC receive characteristics (continued)
PARAMETER
Ilkg
lk
TEST CONDITIONS
Leakage current
MIN
TYP
MAX
AOP
– 10
10
AOM
–10
10
Output impedance,
differential, between
AOP and AOM
(see Note 4)
30
µA
kΩ
Transmit input = one frequency in 0.3-kHz to 3.4-kHz band at – 3 dBrl,
Receive channel idle,
Crosstalk measured at receive analog output
Transmit-to-receive
crosstalk
UNIT
– 70
dB
NOTE 4. This parameter is characterized but not tested.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu1
Transmit setup time at power up
(PWAD transition from H to L)
ADCLK input frequency = 1.024 MHz,
See Note 11
20
µs
tsu2
Receive setup time at power up
(PWDA transition from H to L)
ADCLK input frequency = 1.024 MHz,
See Note 12
20
µs
tsu3
th
Receive setup time, DIGS or DIGL setup before ADCLK↑
See Figure 4
50
Receive hold time, DIGS or DIGL hold after ADCLK↑
See Figure 4
50
tc
tw1
Cycle time, ADCLK
Pulse duration, ADCLK high
470
tw2
tf
Pulse duration, ADCLK low
470
Fall time, ADCLK
20
ns
tr
Rise time, ADCLK
20
ns
ns
ns
µs
1
ns
ns
NOTES: 11. After the setup time, the transmit channel displays normal operating characteristics.
12. After the setup time, the receive channel displays normal operating characteristics.
switching characteristic over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ta
TEST CONDITION
Transmit access time, ADOUT after ADCLK↑ (see Note 4)
See Figure 3
NOTE 4. This parameter is characterized but not tested.
8
POST OFFICE BOX 655303
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MIN
TYP
MAX
UNIT
100
ns
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
The receive characteristics in the electrical characteristics table are measured by activating the MSP58C20 receive
path through a digital modulator. This modulator consists of two functional blocks (see Figure 1 and Figure 2)
connected in series. The output of the decoder (see Figure 2) is shown in Table 1.
3
/
Em
BITS (16 –1)
3 LSBs
+
/
16
3
/
Z –1
/
16
Di
/
13 MSBs
Figure 1. 16- to 13-Bit Modulator at 512-kHz Sampling Rate
512 kHz
Di
13
/
512 kHz
Ux
16
/
+
11
/
1/ 32
12
/
+
16
16
/
Z –1
12
/
16
/
+
4 MSBs
/
Dx
Decoder
12
Rx
Sx
Vx
+
Z –1
3
/
64
DIGS
DIGL
Dx
3
/
2048
Figure 2. Sigma-Delta-2 Modulator at 512-kHz Sampling Rate
Table 1. Dx Decoder
DECODER INPUT
DECODER OUTPUT
Vx (11)
Vx (10)
Vx (9)
Vx (8)
Dx (2)
Dx (1)
Dx (0)
DIGS
DIGL
0
1
X
X
H
H
L
L
H
0
0
1
X
H
H
L
L
H
0
0
0
1
H
H
L
L
H
0
0
0
0
H
H
H
L
L
1
1
1
1
L
L
H
H
L
1
1
1
0
L
H
L
H
H
1
1
0
X
L
H
L
H
H
1
0
X
X
L
H
L
H
H
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MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
PARAMETER MEASUREMENT INFORMATION
ADCLK
ta
ADOUT
Figure 3. Transmit Access Timing Waveforms
ADCLK
tsu3
th
DIGS
or
DIGL
Figure 4. Receive Setup and Hold Time Waveforms
10
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MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
TYPICAL CHARACTERISTICS
RECEIVE IDLE CHANNEL†
SINGLE-FREQUENCY NOISE SPECTRUM
TRANSMIT IDLE CHANNEL
SINGLE-FREQUENCY NOISE SPECTRUM
– 60
VDD = 4.75 V to 5.25 V
TA = 25°C
Output Signal Magnitude – dBrl
VDD = 4.75 V to 5.25 V
– 55 TA = 25°C
– 70
(7, – 72)
– 75 (0.05, – 80)
(4, – 80)
(3.4, – 82)
– 80
(0.3, – 82)
– 85
– 90
– 95
– 60
(100, – 64)
(10, – 64)
– 65
– 70
– 75
– 80
(3, – 82)
– 85 (0.01, – 82)
– 90
– 95
– 100
– 100
0
5
10
15
20
0
Output Signal Frequency – kHz
20
40
60
80
100
Output Signal Frequency – kHz
† This parameter is characterized but not tested.
Figure 5
Receive Signal-to-Total-Noise-Plus-Distortion Ratio – dB
Output Signal Magnitude – dBrl
– 65
– 50
(20, – 64)
(12, – 65)
Figure 6
RECEIVE SIGNAL-TO-TOTAL-NOISEPLUS-DISTORTION RATIO
vs
DIGITAL INPUT SIGNAL MAGNITUDE
70
G
VDD = 5.25 V
TA = 25°C
60 See Note A
H
I
F
50
E
40
(–1, 50)
(–20, 50)
D
C
30
B
20
10
A
(–70, 0)
0
– 80
– 60
– 40
– 20
SET OF
POINTS
LOCATION
A
(–70,9)
B
(–58, 23)
C
(–53, 28)
D
(–43, 38)
E
(–35, 46)
F
(–28, 53)
G
(–13, 67)
H
(–5, 69)
I
(–1, 64)
0
Digital Input Signal Magnitude – dBrl
NOTE A: The three points on the dashed line are minimum
qualification standards, which every MSP58C20 must
pass. The curve shows empirical data from a
representative lot.
Figure 7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
Transmit Signal-to-Total-Noise-Plus-Distortion Ratio – dB
TYPICAL CHARACTERISTICS
TRANSMIT SIGNAL-TO-TOTAL-NOISEPLUS-DISTORTION RATIO
vs
ANALOG INPUT SIGNAL MAGNITUDE
70
G
VDD = 5.25 V
60 TA = 25°C
See Note A
50
H I
F
(–1, 50)
E
40
(–20, 50)
D
30
C
B
20
10
A
0
– 10
(–70, – 13)
– 20
– 80
– 70
– 60
– 50
– 40
– 30
– 20
– 10
0
Analog Input Signal Magnitude – dBrl
NOTE A. The three points on the dashed line are minimum
qualification standards, which every MSP58C20 must
pass. The curve shows empirical data from a
representative lot.
Figure 8
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SET OF
POINTS
LOCATION
A
(–70,8)
B
(–58, 20)
C
(–53, 24)
D
(–43, 32)
E
(–35, 40)
F
(–28, 48)
G
(–13, 65)
H
(–5, 69)
I
(–1, 69)
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
MAXIMUM AND MINIMUM CHARACTERISTICS
RECEIVE GAIN VARIATIONS
vs
INPUT SINE-WAVE FREQUENCY
4
Receive Gain Variations – dB
2
A
VDD = 4.75 V
TA = 25°C
B
SET OF
POINTS
C
0
D
Maximum
–2
E
Minimum
–4
F
–6
G
H
–8
– 10
I
– 12
– 14
0
2
4
6
8
10
12
14
16
MIN
MAX
A
(0.156, – 0.6)
(0.156, 0.6)
B
(4, – 0.6)
(4, 0.6)
C
(4.6875, – 0.7)
(4.6875, – 0.4)
D
(6.25, – 1.75)
(6.25, – 1.4)
E
(7.8125, – 3.35)
(7.8125, – 2.9)
F
(9.375, – 5.25)
(9.375, – 4.8)
G
(10.9375, – 7.25) (10.9375, – 6.8)
H
(12.5, – 9.2)
(12.5, – 8.7)
I
(15.625, – 12.8)
(15.625, – 12.2)
18
Input Sine-Wave Frequency – kHz
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
MSP58C20
AUDIO-BAND CONVERTER
SPSS015B – DECEMBER 1993 – REVISED JULY 1996
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
PINS **
0.050 (1,27)
16
20
24
28
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.299 (7,59)
0.293 (7,45)
0.010 (0,25) NOM
Gage Plane
0.010 (0,25)
1
8
0°– 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
4040000 / B 03/95
NOTES: A.
B.
C.
D.
14
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
MSP58C20DW
OBSOLETE
SOIC
DW
20
TBD
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MSP58C20DWR
OBSOLETE
SOIC
DW
20
TBD
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MSP58C20S1DW
OBSOLETE
SOIC
DW
20
TBD
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MSP58C20S2DW
OBSOLETE
SOIC
DW
20
TBD
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SP58C20DW
OBSOLETE
SOIC
DW
20
TBD
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SP58C20DWR
OBSOLETE
SOIC
DW
20
TBD
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(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
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Addendum-Page 1
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