HD74HC670 4-by-4 Register File (with 3-state outputs) Description The HD74HC670, 16-bit register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data. This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, (G W ) is high, the data inputs are inhibited and their levels can cuase no change in the information stored in the internal latches. When the read-enable input, (GR) is high, the data outputs are inhibited and go into the high-impedance state. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. when the read address is made in conjunction with the read-enable signal, the word appears at the four outputs. Features • • • • • High Speed Operation: tpd (Read Select to Q) = 21 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC670 Function Table Write Inputs Word WB WA GW 0 1 2 3 L L L Q=D Q0 Q0 Q0 L H L Q0 Q=D Q0 Q0 H L L Q0 Q0 Q=D Q0 H H L Q0 Q0 Q0 Q=D X X H Q0 Q0 Q0 Q0 Read Inputs Outputs RB RA GR Q1 Q2 Q3 Q4 L L L W0 B 1 W0 B 2 W0 B 3 W0 B 4 L H L W1 B 1 W1 B 2 W1 B 3 W1 B 4 H L L W2 B 1 W2 B 2 W2 B 3 W2 B 4 H H L W3 B 1 W3 B 2 W3 B 3 W3 B 4 X X H Z Z Z Z H : high level L : low level X : irrelevant Z : high impedance (off) (Q = D) : The four selected internal flip-flop outputs will assume the states applied to the four external data inputs. Q0 : The level of Q before the indicated input conditions were established. W0 B 1 : The first bit of word 0, etc. 2 HD74HC670 Pin Arrangement 16 VCC D1 15 Data D1 D4 WA 14 WA 4 RB WB 13 WB RA 5 RA CW 12 Write Q4 6 Q4 CR 11 Read Q3 7 Q3 Q1 10 Q1 GND 8 9 Q2 Data Read select D2 1 D3 2 D3 D4 3 RB D2 Write select Enable Outputs Q2 Outputs (Top view) Logic Diagram To other three bits D G Q D G Q D G Q D G VCC Q Q Data WA RA WB GR GW RB 3 HD74HC670 DC Characteristics Ta = –40 to +85°C Ta = 25°C Item Symbol VCC (V) Min Typ Max Min Max Unit Input voltage VIH 2.0 1.5 — — 1.5 — V 4.5 3.15 — — 3.15 — 6.0 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 — — 1.8 — 1.8 2.0 1.9 2.0 — 1.9 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — I OH = –6 mA 6.0 5.68 — — 5.63 — I OH = –7.8 mA 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 I OL = 6 mA 6.0 — — 0.26 — 0.33 I OL = 7.8 mA VIL Output voltage VOH VOL Test Conditions V V V Vin = VIH or VIL I OH = –20 µA Vin = VIH or VIL I OL = 20 µA Off-state output current I OZ 6.0 — — ±0.5 — ±5.0 µA Vin = VIN or VIL, Vout = VCC or GND Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply current I CC 6.0 — — 4.0 40 µA Vin = VCC or GND, Iout = 0 µA 4 — HD74HC670 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Ta = –40 to +85°C Ta = 25°C VCC (V) Min Typ Max Min Max Unit Test Conditions Propagation delay t PLH 2.0 — — 160 — 200 ns Read select to Q time 4.5 — 21 32 — 40 6.0 — — 27 — 34 t PLH 2.0 — — 200 — 250 ns Write enable to Q t PHL 4.5 — 24 40 — 50 6.0 — — 34 — 43 t PLH 2.0 — — 150 — 190 ns Data to Q t PHL 4.5 — 18 30 — 38 6.0 — — 26 — 33 Item Symbol t PHL Output enable t ZH 2.0 — — 150 — 190 time t ZL 4.5 — 18 30 — 38 6.0 — — 26 — 33 Output disable t HZ 2.0 — — 150 — 190 time t LZ 4.5 — 17 30 — 38 6.0 — — 26 — 33 2.0 80 — — 100 — 4.5 16 — — 20 — 6.0 14 — — 17 — 2.0 60 — — 75 — 4.5 12 4 — 15 — 6.0 10 — — 13 — 2.0 60 — — 75 — 4.5 12 — — 15 — 6.0 10 — — 13 — 2.0 50 — — 63 — 4.5 10 6 — 13 — 6.0 9 — — 11 — 2.0 50 — — 63 — 4.5 10 — — 13 — 6.0 9 — — 11 — Pulse width Setup time tw t su t su Hold time th ns ns ns ns Data to Write enable ns Write select to Write enable ns Write enable to Data ns Write enable to Write select 5 HD74HC670 AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont) Ta = –40 to +85°C Ta = 25°C VCC (V) Min Typ Max Min Max Unit Latch time for new t latch 2.5 100 — — 125 — ns data 4.5 20 — — 25 — 6.0 17 — — 21 — Item Symbol Output rise/fall t TLH 2.0 — — 75 — 95 time t THL 4.5 — 5 15 — 19 6.0 — — 13 — 16 — — 5 10 — 10 Input capacitance 6 Cin ns pF Test Conditions Unit: mm 19.20 20.00 Max 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max 7.62 + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DA — Conforms 0.24 g Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.42 ± 0.08 0.40 ± 0.06 0.15 *0.22 ± 0.03 0.20 ± 0.03 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.25 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-16DN Conforms Conforms 0.15 g Cautions 1. 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