18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS Features HG74ALVC16835C Jan 1999 General Description l Ideal for Use in PC100 Registered DIMM l 0.5µm CMOS Technology l 2.3 ~ 3.6 VCC Operation l Balanced Output Drive(±24mA) l Package Options Include Plastic Thin Shrink Small-Outline Packages, Shrink Small-Outline Packages (TSSOP 56 Pins, SSOP 56 Pins, TVSOP56 Pins) The HG74ALVC16835C is an 18-bit universal bus driver designed for 2.3V to 3.6 V VCC Operation. The Output-Enable(OE) controls data flow from A to Y. The device operates in transparent mode when the latch-enable(LE) input is high. When LE is low, the A data is latched if the clock input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the Outputs are in the high impedance state. OE should be tied to VCC through a pull up resistor to ensure the high impedance state during power up or power down. Pin Configuration (TOP VIEW) NC 1 56 GND NC 2 55 NC Y1 3 54 A1 GND 4 53 GND Y2 5 52 A2 Y3 6 51 A3 Vcc 7 50 Vcc Y4 8 49 A4 Y5 9 48 A5 Y6 10 47 A6 GND 11 46 GND Y7 12 45 A7 Y8 13 44 A8 Y9 14 43 A9 Y10 15 42 A10 Y11 16 41 A11 Y12 17 40 A12 GND 18 39 GND Y13 19 38 A13 Y14 20 37 A14 Y15 21 36 A15 Vcc 22 35 Vcc Y16 23 34 A16 Y17 24 33 A17 GND 25 32 GND Y18 26 31 A18 OE 27 30 CLK LE 28 29 GND The HG74ALVC16835C is characterized for operation from -40°C to 85°C. Function Table INPUTS OE H L L L L L LE CLK A OUTPUT Y X H H L L L X X X ↑ ↑ L or H X L H L H X Z L H L H YO= =Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low. NC- No ineternal connection 1 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Logic Diagram (positive logic) 27 OE 30 CLK LE A1 28 54 3 1D Y1 C1 CLK TO 17 Other Channels Absolute Maximum Ratings Over Operating Free-air Temperature Range= Symbols VCC VI VO IIK IOK IO ICC IGND Tstg Parameter Supply Voltage Range Input Voltage Range (see note 1) Output Voltage Range (see note 1 and 2) Input Clamp Current Output Clamp Current Continuous Output Current Continuous Current through each VCC Continuous Current through each GND Storage Temperature Range Value -0.5 V to 4.6 V -0.5V to VCC+0.5V -0.5V to VCC+0.5V ±50 mA ±50 mA ± 50 mA +100 mA -100 mA -65°C to 150°C Conditions VI < 0 VO <0 or VO >VCC VO =0 to VCC =Stresses beyond those listed under “ absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. Note 1) The input and output voltage ratings may be exceeded if the input and output clamp current are observed. Note 2) This value is limited to 4.6 V maximum. 2 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Recommended Operating Conditions (see Note 3) Symbols VCC Supply Voltage VIH High -level input Voltage VIL Low-level input Voltage VI VO Input Voltage Output Voltage IOH High-level output current IOL Low-level output current ∆t/∆v TA Value Parameter MIN 2.3 1.7 2 0 -40 Conditions V V V V V V V mA mA mA mA mA mA ns/V °C 0.7 0.8 VCC VCC -12 -12 -24 12 12 24 10 85 0 0 Input transition rise or fall rate Operating free-air temperature Units MAX 3.6 VCC =2.3V to 2.7V VCC =2.7V to 3.6V VCC =2.3V to 2.7V VCC =2.7V to 3.6V VCC =2.3V VCC =2.7V VCC =3V VCC =2.3V VCC =2.7V VCC =3V Note 3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Electrical Characteristics Over Recommended Operating Free-air Temperature Range Parameter Test Conditions IOH = -100µA IOH = - 6mA VOH IOH = -12mA VIH =1.7V VIH =1.7V VIH = 2V IOH = -24 mA IOL = 100µA IOL = 6mA IOL = 12mA VOL VIH = 2V Min Value Typ= VCC−0.2 2 1.7 2.2 2.4 2 ICC ∆ICC Co 0.2 0.4 0.7 0.4 0.55 ±5 ±10 VIL = 0.7V VIL = 0.7V VIL = 0.8V VIL = 0.8V Control Inputs CI Data Inputs Outputs 40 5 VO= VCC or GND 7 = All typical Values are at VCC =3.3V, TA = 25°C. 3 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS V µA 750 3.5 VI = VCC or GND Units V IOL =24mA VI= VCC or GND VO = VCC or GND VI = VCC or GND IO = 0 One input at VCC - 0.6V, Other inputs at VCC or GND IL IOZ Max VCC 2.3V to 3.6V 2.3V 2.3V 2.7V 3V 3V 2.3V to 3.6V 2.3V 2.3V 2.7V 3V 3.6V 3.6V 3.6V 3V to 3.6V ρF 3.3V ρF 3.3V 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Timing Requirements Over Recommended Operating Free-air Temperature Range(see figure1~10 ) Symbol Vcc=2.5V±0.2V Condition Parameter Min tW Clock frequency Pulse Duration tsu Setup time th Hold time fclock LE high CLK high or low Data before CLK↑ Data before LE↓ CLK high CLK low Data after CLK↑ CLK high Data after LE↓ or low Max Vcc=2.7V Min Max 150 150 Vcc=3.3V±0.3V Min Unit Max 150 MHz 3.3 3.3 0.9 1.9 1.3 1.0 3.3 3.3 0.9 1.6 1.1 1.0 3.3 3.3 0.7 1.5 1 1.1 ns ns ns ns ns ns 1.4 1.7 1.4 ns Switching Characteristics Over Recommended Operating Free-air Temperature Range Parameter Output Input (From) (to) Min 150 1 1.3 1.4 1.4 1 fmax A LE CLK tpd ten Idis Y Y Y OE OE VCC =2.7V VCC =2.5V± 0.2V Max Min 150 VCC =3.3V±0.3V Max 4.2 5 5.5 5.5 4.5 4.2 4.9 5.2 5.6 4.3 Min 150 1 1.3 1.4 1.1 1.3 Max 3.6 4.2 4.5 4.6 3.9 Unit MHz ns ns ns ns ns Switching Characteristics From 0°C to 65°C, CL=50ρF Parameter Input (From) Output (To) CLK Y tpd VCC=3.3V± 0.15V Min 1.7 Unit Max 4.5 ns Parameter Measurement (VCC=2.5V±0.2V) 2 x Vcc 500Ω From Output S1 Under Test Open GND C L = 30pF ( see Note) Test tpd tPLZ / tPZL tPHZ /tPZH 500Ω S1 Open 2 x VCC GND Figure 1. Load Circuit Note) CL includes probe and jig capacitance 4 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Voltage Waveforms VCC Timing VCC /2 0V Input tw th tsu Data VCC /2 VCC /2 Input VCC VCC VCC /2 0V VCC /2 Input 0V Figure 2. Set up and Hold Times Figure 3. Pulse Duration VCC VCC /2 VCC /2 Input 0V tPHL tPLH VOH Output VCC /2 VCC/2 VOL Figure 4. Propagation Delay times Output Control VCC (Low-level enabling) VCC /2 VCC /2 0V Output Waveform 1 tPZL tPLZ VCC S1 at 2 x VCC VCC /2 VOL + 0.15V VOL (See Note 1 ) tPZH tPHZ VOH Output Waveform 2 VCC /2 S1 at GND VOH - 0.15V 0V (See Note 1 ) Figure 5. Enable and Disable Times Note 1 )Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control Note 2) All input pulses are supplied by generators having the following characteristics: PRR ⊆ 10Mhz, Zo = 50Ω , tr ⊆ 2ns, tf ⊆ 2ns. Note 3) The output are measured one at a time with one transition per measurement. Note 4) tPLZ and tPHZ are the same as tdis. Note 5) tPZL and tPZH are the same as ten . Note 6) tPLH and tPHL are the same as tpd. 5 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS HG74ALVC16835C Jan 1999 Parameter Measurement (Vcc=2.7V and 3.3V±0.3V) From Output Under Test 6V 500 S1 Test tpd tPLZ / tPZL Open GND tPHZ /tPZH CL = 50pF (see note) S1 Open 6V GND 500 Figure 6. Load Circuit Note) CL includes probe and jig capacitance Voltage Waveforms 2.7V Timing 1.5V Input 0V tsu tw th 2.7V Input Data 2.7V 1.5V 1.5V 1.5V 0V 1.5V Input 0V Figure 8. Pulse Duration Figure 7. Set up and Hold Times 2.7V 1.5V 1.5V Input 0V tPLH tPHL VOH 1.5V Output 1.5V VOL Figure 9. Propagation Delay times 6 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS Output Control (Low-level enabling) HG74ALVC16835C Jan 1999 2.7V 1.5V 1.5V 0V Output Waveform 1 S1 at 6V (See Note1) tPLZ tPZL 3V 1.5V VCC + 0.3V VOL tPHZ tPZH Output Waveform 2 S1 at GND (See Note1) VOH 1.5V VOH - 0.3V 0V Figure 10. Enable and Disable Times Note 1 ) Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control Note 2) All input pulses are supplied by generators having the following characteristics : PRR ⊆ 10MHz, Zo = 50Ω, tr ⊆ 2.5ns, tf ⊆ 2.5ns. Note 3) The output are measured one at a time with one transition per measurement. Note 4) tPLZ and tPHZ are the same as tdis. Note 5) tPZL and tPZH are the same as ten . Note 6) tPLH and tPHL are the same as tpd. 7 Copyright ©1999, Hyundai Electronics Industries Co., Ltd. ELECTRONICS