TI SN74ALVC7804

SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
•
•
•
•
•
•
•
•
•
•
Operates at 3-V to 3.6-V VCC
Load Clock and Unload Clock Can Be
Asynchronous or Coincident
Low-Power Advanced CMOS Technology
Full, Empty, and Half-Full Flags
Programmable Almost-Full/Almost-Empty
Flag
Fast Access Times of 18 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
Data Rates From 0 to 40 MHz
3-State Outputs
Pin Compatible With SN74ACT7804
Packaged in Shrink Small-Outline 300-mil
Package (DL) Using 25-mil Center-to-Center
Spacing
description
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ALVC7804 is
an 18-bit FIFO with high speed and fast access
times. Data is processed at rates up to 40 MHz
with access times of 18 ns in a bit-parallel format.
The SN74ALVC7804 is designed for 3-V to 3.6-V
VCC operation.
DL PACKAGE
(TOP VIEW)
RESET
D17
D16
D15
D14
D13
D12
D11
D10
VCC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
LDCK
NC
NC
FULL
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
OE
Q17
Q16
Q15
GND
Q14
VCC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
VCC
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY
Data is written into memory on a low-to-high
27
30
transition of the load clock (LDCK) and is read out
28
29
on a low-to-high transition of the unload clock
(UNCK). The memory is full when the number of
words clocked in exceeds the number of words clocked out by 512. When the memory is full, LDCK has no effect
on the data residing in memory. When the memory is empty, UNCK has no effect.
Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almostfull/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory
is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output
is high whenever the FIFO contains 256 or more words and is low when it contains 255 or less words. The AF/AE
status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to
program the almost-empty offset value (X) and the almost-full offset value (Y), if program enable (PEN) is low.
The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. The AF/AE
flag is low when the FIFO contains between (X plus 1) and (511 minus Y) words.
A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low,
and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power
up. The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs.
The data outputs are in the high-impedance state when the output-enable (OE) is high.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
logic symbol†
Φ
FIFO 512 × 18
1
RESET
LDCK
UNCK
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
23
21
Full
LDCK
32
56
PEN
RESET
25
Half-Full
UNCK
Almost Full/Empty
EN1
Empty
22
24
FULL
HF
AF/AE
29
EMPTY
Program Enable
0
0
33
20
34
19
36
18
37
17
38
16
40
15
41
14
42
12
43
11
45
Data
Data
1
9
46
8
47
7
48
6
49
5
51
4
53
3
54
2
55
17
17
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
functional block diagram
OE
D0 – D17
RAM
Read
Pointer
UNCK
512 × 18
Write
Pointer
LDCK
Q0 – Q17
EMPTY
Reset
Logic
RESET
StatusFlag
Logic
PEN
FULL
HF
AF/AE
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AF/AE
24
O
Almost full/almost empty flag. Depth offset values can be programmed for AF/AE, or the default
value of 64 can be used for both the almost empty offset (X) and the almost full offset (Y). AF/AE
is high when memory contains X or less words or (512 – Y) or more words. AF/AE is high after
reset.
D0 – D17
21 – 14, 12 – 11,
9–2
I
18-bit data input port
EMPTY
29
O
Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL
28
O
Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF
22
O
Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
LDCK
25
I
Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE
56
I
Output enable. When OE is high, the data outputs are in the high-impedance state.
PEN
23
I
Program enable. After reset and before the first word is written to the FIFO, the binary value on
D0 – D7 is latched as an AF/AE offset value when PEN is low and WRTCLK is high.
Q0 – Q17
33 – 34, 36 – 38,
40 – 43, 45 – 49,
51, 53 – 55
O
18-bit data output port
RESET
1
I
Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and
EMPTY low.
UNCK
32
I
Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
0
ÉÉ
ÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
LDCK
D0–D17
W1
W2
W
(X+1)
A
B
Don’t Care
C
1
OE
W1
W2
W
(Y+1)
W
(Y+2)
D
E
F
EMPTY
AF/AE
HF
FULL
Define the AF/AE Flag
Using the Default Value of X and Y
Figure 1. Write, Read, and Flag Timing Reference
G
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
• DALLAS, TEXAS 75265
Q0–Q17
0
ÉÉ ÉÉÉÉ ÉÉ
ÉÉ ÉÉÉÉ ÉÉ
POST OFFICE BOX 655303
UNCK
H
I
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
1
PEN
SCAS432 – JANUARY 1995
4
RESET
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
DATA WORD NUMBERS FOR FLAG TRANSITIONS
DEVICE
SN74ALVC7804
TRANSITION WORD
A
B
C
D
E
F
G
H
I
W256
W(512 – Y)
W512
W257
W258
W(512 – X)
W(513 – X)
W511
W512
offset values for AF/AE
The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value
(Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The AF/AE
flag is high when the FIFO contains X or less words or (512 minus Y) or more words.
To program the offset values, PEN can be brought low after reset. On the following low-to-high transition of
LDCK, the binary value on D0 – D7 is stored as the almost empty offset value (X) and the almost full offset value
(Y). Holding PEN low for another low-to-high transition of LDCK reprograms Y to the binary value on D0 – D7
at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are disabled while the offsets
are programmed. A maximum value of 255 can be programmed for either X or Y (see Figure 2). To use the
default values of X = Y = 64, PEN must be held high.Figure 1
RESET
LDCK
PEN
D0 – D17
Don’t Care
Don’t Care
X and Y
Y
EMPTY
Figure 2. Programming X and Y Separately
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• DALLAS, TEXAS 75265
5
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
50 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
*
"
"
"
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
recommended operating conditions
′ALVC7804-25
VCC = 3.3 V
0.3 V
MIN
MAX
"
VIH
VIL
High-level input voltage
2
Low-level input voltage
′ALVC7804-40
VCC = 3.3 V
0.3 V
MIN
MAX
"
2
0.8
VI
VO
0
0
VCC
VCC
0
0
UNIT
V
0.8
V
VCC
VCC
V
V
IOH
High-level
output current,,
g
Q outputs, Flags
VCC = 3 V
–8
–8
mA
IOL
Low-level output current,,
Q outputs, Flags
VCC = 3 V
16
16
mA
fclock
Clock frequency
25
MHz
tw
Pulse duration
40
D0 – D17 high or low
8
12
LDCK high or low
8
12
UNCK high or low
8
12
PEN low
8
12
RESET low
tsu
th
TA
6
Setup time
Hold time
10
12
D0 – D17 before LDCK↑
5
5
LDCK inactive before RESET high
6
6
PEN before LDCK↑
8
8
D0 – D17 after LDCK↑
0
0
PEN high after LDCK low
0
0
PEN low after LDCK↑
3
3
LDCK inactive after RESET high
6
6
Operating free-air temperature
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
70
0
ns
ns
ns
70
°C
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
TYP‡
MIN
MAX
UNIT
VCC = MIN to MAX,
VCC = 3 V,
IOH = – 100 µA
IOH = – 8 mA
VCC = MIN to MAX,
VCC = 3 V,
IOL = 100 µA
IOL = 8 mA
VCC = 3 V,
VCC = 3.6 V,
IOL = 16 mA
VI =VCC or GND
0.55
±5
µA
VCC = 3.6 V,
VCC = 3.6 V,
VO =VCC or GND
VI = VCC or GND and IO = 0
±10
µA
40
µA
∆ICC§
VCC = 3.6 V,
Other inputs at VCC or GND
One input at VCC – 0.6 V,
500
µA
Ci
VCC = 3.3 V,
VCC = 3.3 V,
VI = VCC or GND
VO = VCC or GND
VOH
Flags Q outputs
Flags,
Flags, Q outputs
VOL
Flags
Q outputs
II
IOZ
ICC
Co
VCC – 0.2
2.4
V
0.2
0.4
V
3
pF
6
pF
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
§ This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 5)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
′ALVC7804-25
VCC = 3.3 V
0.3 V
MIN
MAX
"
′ALVC7804-40
VCC = 3.3 V
0.3 V
MIN
MAX
"
fmax
tpd
LDCK or UNCK
40
LDCK↑
9
22
9
24
tpd
tPLH
UNCK↑
6
18
6
20
6
17
6
19
tPHL
tPHL
UNCK↑
6
17
6
19
RESET low
4
18
4
20
LDCK↑
6
17
6
19
6
17
6
19
tPHL
tPLH
Any Q
LDCK↑
EMPTY
UNCK↑
FULL
25
MHz
tPLH
tpd
RESET low
4
20
4
22
LDCK↑
7
20
7
22
tpd
tPLH
UNCK↑
7
20
7
22
RESET low
2
12
2
14
LDCK↑
5
20
5
22
7
20
7
22
3
14
3
16
2
10
2
11
2
11
2
12
tPLH
tPHL
tPHL
ten
tdis
AF/AE
UNCK↑
HF
RESET low
Any Q
OE
UNIT
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per FIFO channel
Outputs enabled
POST OFFICE BOX 655303
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 5 MHz
TYP
UNIT
53
pF
7
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
APPLICATION INFORMATION
′ALVC78xx
LDCK
LDCK
UNCK
UNCK
EMPTY
FULL
EMPTY
FULL
OE
D18 – D35
D0 – D17
OE
Q18 – Q35
Q0 – Q17
′ALVC78xx
LDCK
FULL
UNCK
EMPTY
OE
D0 – D17
D0 – D17
Q0 – Q17
Figure 3. Word-Width Expansion: 512
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Q0 – Q17
36 Bit
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
140
fdata = 1/2 fclock
TA = 75°C
CL = 0 pF
I CC(f) – Supply Current – mA
120
VCC = 3.6 V
100
VCC = 3.3 V
80
60
VCC = 3 V
40
20
0
0
10
20
30
40
50
60
70
80
90
fclock – Clock Frequency – MHz
Figure 4
calculating power dissipation
With ICC(f) taken from Figure 4, the dynamic power (Pd), based on all data outputs changing states on each read,
can be calculated by using:
Pd = VCC × [ICC(f) + (N × ∆ICC × dc)] + ∑(CL × VCC2 × fo)
A more accurate total power (PT) can be calculated if quiescent power (Pq) is also taken into consideration.
Quiescent power (Pq) can be calculated using:
Pq = VCC × [ICCI + (N × ∆ICC × dc)]
Total power will be:
PT = Pd + Pq
The above equations provide worst-case power calculations.
Where:
N
∆ICC
dc
CL
fo
ICCI
=
=
=
=
=
=
number of inputs driven by TTL levels
increase in power supply current for each input at a TTL high level
duty cycle of inputs at a TTL high level of 3.4 V
output capacitance load
switching frequency of an output
idle current, supply current when FIFO is idle ≈ pF × fclock = 0.2 × fclock
(current is due to free-running clocks)
pF
= power factor (the slope of idle ICC versus frequency)
ICC(f) = active current, supply current when FIFO is transferring data
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
LOAD CIRCUIT FOR OUTPUTS
tw
3V
3V
Timing
Input
Input
1.5 V
tsu
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
1.5 V
1.5 V
1.5 V
0V
tPLH
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.5 V
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
VOL
1.5 V
0V
tPZL
3V
1.5 V
3V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
3V
Data
Input
Input
1.5 V
0V
1.5 V
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOH
1.5 V
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
v
v
3-STATE OUTPUTS (ANY Q)
PARAMETER
R1, R2
CL†
ten
tPZH
tPZL
500 Ω
50 pF
tdi
dis
tPHZ
tPLZ
500 Ω
50 pF
tpd
tPLH / tPHL
500 Ω
50 pF
S1
GND
6V
GND
6V
Open
† Includes probe and test-fixture capacitance
Figure 5. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
v
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright  1999, Texas Instruments Incorporated