TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference Check for Samples: TPS51216 FEATURES DESCRIPTION • The TPS51216 provides a complete power supply for DDR2, DDR3 and DDR3L memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51216 employs D-CAP™ mode coupled with 300 kHz/400 kHz frequencies for ease-of-use and fast transient response. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2A sink/source peak current capabilities, requires only 10-mF of ceramic capacitance. In addition, a dedicated LDO supply input is available. 1 2 • • • Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 V to 28 V – Output Voltage Range: 0.7 V to 1.8 V – 0.8% VREF Accuracy – D-CAP™ Mode for Fast Transient Response – Selectable 300 kHz/400 kHz Switching Frequencies – Optimized Efficiency at Light and Heavy Loads with Auto-skip Function – Supports Soft-Off in S4/S5 States – OCL/OVP/UVP/UVLO Protections – Powergood Output 2-A LDO(VTT), Buffered Reference(VTTREF) – 2-A (Peak) Sink and Source Current – Requires Only 10-m mF of Ceramic Output Capacitance – Buffered, Low Noise, 10-mA VTTREF Output – 0.8% VTTREF, 20-mV VTT Accuracy – Support High-Z in S3 and Soft-Off in S4/S5 Thermal Shutdown 20-Pin, 3 mm × 3 mm, QFN Package The TPS51216 provides rich useful functions as well as excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (softoff) in S4/S5 state. Programmable OCL with low-side MOSFET RDS(on) sensing, OVP/UVP/UVLO and thermal shutdown protections are also available. The TPS51216 is available in a 20-pin, 3 mm × 3 mm, QFN package and is specified for ambient temperature from –40°C to 85°C. VIN 5VIN PGND APPLICATIONS • • DDR2/DDR3/DDR3L Memory Power Supplies SSTL_18, SSTL_15, SSTL_135 and HSTL Termination PGND TPS51216 VBST 15 12 V5IN S3 17 S3 S5 16 S5 VDDQ DRVH 14 SW 13 DRVL 11 6 VREF PGND 10 PGOOD 20 8 7 REFIN GND 19 MODE 18 TRIP AGND VDDQSNS 9 VLDOIN 2 VTT 3 VTTSNS 1 VTTGND 4 VTTREF 5 Powergood VTT VTTREF AGND PGND UDG-10138 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D-CAP is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) ORDERABLE DEVICE NUMBER TA PACKAGE –40°C to 85°C Plastic Quad Flat Pack (20 pin QFN) (1) TPS51216RUKR TPS51216RUKT PINS 20 OUTPUT SUPPLY MINIMUM QUANTITY Tape and reel 3000 Mini reel 250 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN MAX VBST –0.3 36 VBST (3) –0.3 6 –5 30 VLDOIN, VDDQSNS, REFIN –0.3 3.6 VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN, S3, S5, TRIP, MODE –0.3 6 –5 36 DRVH (3) –0.3 6 VTTREF, VREF –0.3 3.6 VTT –0.3 3.6 DRVL –0.3 6 PGOOD –0.3 6 SW Input voltage range (2) DRVH Output voltage range (2) Junction temperature range, TJ Storage temperature range, TSTG (1) (2) (3) UNIT –55 V V 125 °C 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. THERMAL INFORMATION THERMAL METRIC TPS51216 QFN (20) PINS qJA Junction-to-ambient thermal resistance 94.1 qJCtop Junction-to-case (top) thermal resistance 58.1 qJB Junction-to-board thermal resistance 64.3 yJT Junction-to-top characterization parameter 31.8 yJB Junction-to-board characterization parameter 58.0 qJCbot Junction-to-case (bottom) thermal resistance 5.9 2 Submit Documentation Feedback UNITS °C/W Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage 5.5 VBST –0.1 33.5 VBST (1) –0.1 5.5 -3 28 SW (2) –4.5 28 VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3, S5, TRIP, MODE –0.1 5.5 –3 33.5 DRVH Output voltage range TA (1) (2) MAX 4.5 SW Input voltage range TYP V5IN DRVH (1) –0.1 5.5 DRVH (2) –4.5 33.5 VTTREF, VREF –0.1 3.5 VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 Operating free-air temperature –40 85 UNIT V V V °C Voltage values are with respect to the SW terminal. This voltage should be applied for less than 30% of the repetitive period. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 3 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, VMODE=0V, VS3=VS5=5V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5IN(S0) V5IN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 590 IV5IN(S3) V5IN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 IV5INSDN V5IN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 1 mA IVLDOIN(S0) VLDOIN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 5 mA IVLDOIN(S3) VLDOIN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 mA IVLDOINSDN VLDOIN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 5 mA V mA mA VREF OUTPUT IVREF = 30 mA, TA = 25°C VVREF Output voltage IVREFOCL Current limit 1.8000 0 mA ≤ IVREF <300 mA, TA = –10°C to 85°C 1.7856 1.8144 0 mA ≤ IVREF <300 mA, TA = –40°C to 85°C 1.7820 1.8180 VVREF = 1.7 V 0.4 0.8 mA VTTREF OUTPUT VVTTREF Output voltage VVDDQSNS/2 |IVTTREF| <100 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V 49.2% |IVTTREF| <10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V 49% V 50.8% VVTTREF Output voltage tolerance to VVDDQ IVTTREFOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTTREF= 0 V 10 18 mA IVTTREFOCLSNK Sink current limit VVDDQSNS = 1.8 V, VVTTREF = 1.8 V 10 17 mA IVTTREFDIS VTTREF discharge current TA = 25°C, VS3 = VS5 = 0 V, VVTTREF = 0.5 V 0.8 1.3 mA |IVTT| ≤ 10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF = 0 A –20 20 |IVTT| ≤ 1 A, 1.2 ≤ VVDDQSNS ≤ 1.8 V, IVTTREF = 0 A –30 30 |IVTT| ≤ 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF = 0 A –40 40 |IVTT| ≤ 1.5 A, 1.2 V ≤ VVDDQSNS ≤ 1.4 V, IVTTREF = 0 A –40 40 51% VTT OUTPUT VVTT Output voltage VVTTTOL Output voltage tolerance to VTTREF VVTTREF V IVTTOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V, IVTTREF = 0 A IVTTOCLSNK Sink current limit VVDDQSNS = 1.8V, VVTT = VVTTSNS = 1.1 V, IVTTREF = 0 A IVTTLK Leakage current TA = 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF IVTTSNSBIAS VTTSNS input bias current VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF –0.5 0.0 0.5 IVTTSNSLK VTTSNS leakage current VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF –1 0 1 IVTTDIS VTT Discharge current TA = 25°C, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V, VVTT = 0.5 V, IVTTREF = 0 A 2 3 2 3 mV A 5 7.8 mA mA VDDQ OUTPUT VVDDQSNS VDDQ sense voltage VVDDQSNSTOL VDDQSNS regulation voltage tolerance to REFIN VREFIN TA = 25°C IVDDQSNS VDDQSNS input current VVDDQSNS = 1.8 V IREFIN REFIN input current VREFIN = 1.8 V IVDDQDIS VDDQ discharge current VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled down to GND through 47kΩ (Non-tracking) 12 mA IVLDOINDIS VLDOIN discharge current VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled down to GND through 100kΩ (Non-tracking) 1.2 A –3 3 39 –0.1 0.0 mV mA 0.1 mA SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 100 kΩ 300 VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 200 kΩ 400 fSW VDDQ switching frequency tON(min) Minimum on time DRVH rising to falling (1) tOFF(min) Minimum off time DRVH falling to rising (1) 4 kHz 60 200 320 450 ns Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, VMODE=0V, VS3=VS5=5V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX Source, IDRVH = –50 mA 1.6 3.0 Sink, IDRVH = 50 mA 0.6 1.5 Source, IDRVL = –50 mA 0.9 2.0 Sink, IDRVL = 50 mA 0.5 1.2 DRVH-off to DRVL-on 10 DRVL-off to DRVH-on 20 UNIT VDDQ MOSFET DRIVER RDRVH RDRVL tDEAD DRVH resistance DRVL resistance Dead time Ω ns INTERNAL BOOT STRAP SW VFBST Forward Voltage VV5IN-VBST, TA = 25°C, IF = 10 mA IVBSTLK VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.1 0.2 V 0.01 1.5 mA mA LOGIC THRESHOLD IMODE MODE source current MODE 0 VTHMODE MODE threshold voltage VIL S3/S5 low-level voltage VIH S3/S5 high-level voltage VIHYST S3/S5 hysteresis voltage VILK S3/S5 input leak current 14 15 16 580 600 620 MODE 1 829 854 879 MODE 2 1202 1232 1262 MODE 3 1760 1800 1840 mV 0.5 1.8 V 0.25 –1 0 1 mA SOFT START tSS VDDQ soft-start time Internal soft-start time, CVREF = 0.1 mF, S5 rising to VVDDQSNS > 0.99 × VREFIN 1.1 ms PGOOD COMPARATOR VTHPG VDDQ PGOOD threshold IPG PGOOD sink current tPGDLY PGOOD delay time tPGSSDLY PGOOD start-up delay PGOOD in from higher 106% 108% PGOOD in from lower 90% 92% 94% PGOOD out to higher 114% 116% 118% PGOOD out to lower 82% 84% 86% 3 5.9 0.8 1 VPGOOD = 0.5 V Delay for PGOOD in 110% mA 1.2 ms Delay for PGOOD out, with 100 mV over drive 330 ns CVREF = 0.1 mF, S5 rising to PGOOD rising 2.5 ms Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 5 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, VMODE=0V, VS3=VS5=5V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX 9 10 11 UNIT PROTECTIONS ITRIP TRIP source current TCITRIP TRIP source current temperature coefficient (2) VTRIP VTRIP voltage range VOCL Current limit threshold VOCLN Negative current limit threshold VZC TA = 25°C, VTRIP = 0.4 V 4700 0.2 ppm/°C 3 VTRIP = 3.0 V 360 375 390 VTRIP = 1.6 V 190 200 210 VTRIP = 0.2 V 20 25 30 VTRIP = 3.0 V –390 –375 –360 VTRIP = 1.6 V –210 –200 –190 VTRIP = 0.2 V –30 –25 –20 Wake-up 4.2 4.4 4.5 Shutdown 3.7 3.9 4.1 118% 120% 122% Zero cross detection offset 0 VUVLO V5IN UVLO threshold voltage VOVP VDDQ OVP threshold voltage OVP detect voltage tOVPDLY VDDQ OVP propagation delay With 100 mV over drive VUVP VDDQ UVP threshold voltage UVP detect voltage tUVPDLY VDDQ UVP delay tUVPENDLY VDDQ UVP enable delay VOOB OOB Threshold voltage 68% V mV mV mV 430 66% mA V ns 70% 1 ms 1.2 ms 108% THERMAL SHUTDOWN TSDN (2) 6 Thermal shutdown threshold Shutdown temperature (2) Hysteresis (2) 140 10 °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 DEVICE INFORMATION PGOOD MODE TRIP S3 S5 RUK PACKAGE (TOP VIEW) 20 19 18 17 16 VTTSNS 1 15 VBST VLDOIN 2 14 DRVH VTT 3 13 SW VTTGND 4 12 V5IN VTTREF 5 11 DRVL 8 GND REFIN 9 10 PGND 7 VDDQSNS 6 VREF TPS51216 PowerPAD™ PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. DRVH 14 O High-side MOSFET gate driver output. DRVL 11 O Low-side MOSFET gate driver output. GND 7 – Signal ground. MODE 19 I Connect resistor to GND to configure switching frequency and discharge mode. (See Table 2) PGND 10 – Gate driver power ground. RDS(on) current sensing input(+). PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range. REFIN 8 I Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation. SW 13 S3 17 I S3 signal input. (See Table 1) S5 16 I S5 signal input. (See Table 1) TRIP 18 I Connect resistor to GND to set OCL at VTRIP/8. Output 10-mA current at room temperature, TC = 4700 ppm/°C. VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin. VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF. VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application. VREF 6 O 1.8-V reference output. VTT 3 O VTT 2-A LDO output. Need to connect 10mF or larger capacitance for stability. VTTGND 4 – Power ground for VTT LDO. VTTREF 5 O Buffered VTT reference output. Need to connect 0.22mF or larger capacitance for stability. VTTSNS 1 I VTT output voltage feedback. V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers. Thermal pad – – Connect to GND I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 7 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VREFIN –32% + UV + OV VREFIN +8/16 % 20 PGOOD + Delay + VREFIN +20% VREFIN –8/16 % 15 mA REFIN VREF 8 UVP 6 Reference + + PWM 19 MODE 15 VBST 9 14 DRVH 10 mA 13 SW 8R + TRIP 18 OC XCON + S5 16 7R tON OneShot R S3 17 GND On-Time Discharge Type Selection OVP Soft-Start VDDQSNS Control Logic NOC + 7 12 V5IN R 11 DRVL + ZC VTT Discharge VDDQ Discharge V5OK VTTREF Discharge VTTREF 5 10 PGND 2 VLDOIN 3 VTT 4 VTTGND + + + VTTSNS + 4.4 V/3.9 V 1 + TPS51216 UDG-10135 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 TYPICAL CHARACTERISTICS 10 V5IN Shutdown Current (µA) V5IN Suppy Current (µA) 1000 800 600 400 200 0 −50 −25 0 25 50 75 Junction Temperature (°C) 100 4 2 −25 0 25 50 75 Junction Temperature (°C) 100 125 Figure 2. V5IN Shutdown Current vs Junction Temperature 10 16 14 8 TRIP Source Current (µA) VLDOIN Suppy Current (µA) 6 0 −50 125 Figure 1. V5IN Supply Current vs Junction Temperature 6 4 2 12 10 8 6 0 −50 −25 0 25 50 75 Junction Temperature (°C) 100 4 −50 125 Figure 3. VLDOIN Supply Current vs Junction Temperature 0 25 50 75 Junction Temperature (°C) 100 125 130 120 110 100 90 80 70 60 −25 0 25 50 75 Junction Temperature (°C) 100 125 Figure 5. OVP/UVP Threshold vs Junction Temperature VDDQSNS Discharge Current (mA) 15 OVP UVP 140 50 −50 −25 Figure 4. Current Sense Current vs Junction Temperature 150 OVP/UVP Threshold (%) 8 12 9 6 3 0 −50 −25 0 25 50 75 Junction Temperature (°C) 100 125 Figure 6. VDDQSNS Discharge Current vs Junction Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 9 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 800 8 Switching Frequency (kHz) VTT Discharge Current (mA) 10 6 4 2 700 600 500 400 300 0 −50 −25 0 25 50 75 Junction Temperature (°C) 100 200 125 Figure 7. VTT Discharge Current vs Junction Temperature 500 400 Switching Frequency (kHz) Switching Frequency (kHz) 600 12 14 16 Input Voltage (V) 18 20 22 VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V 600 500 400 300 200 100 6 8 10 12 14 16 Input Voltage (V) 18 20 0 22 Figure 9. Switching Frequency vs Input Voltage 0 2 4 6 8 10 12 14 VDDQ Output Current (A) 16 18 20 Figure 10. Switching Frequency vs Load Current 800 1.55 VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V 600 500 400 300 200 100 RMODE = 200 kΩ VIN = 12 V 1.54 VDDQ Output Voltage (V) RMODE = 200 kΩ VIN = 12 V 700 1.53 1.52 1.51 1.50 1.49 1.48 1.47 1.46 0 2 4 6 8 10 12 14 VDDQ Output Current (A) 16 18 20 1.45 0 Figure 11. Switching Frequency vs Load Current 10 10 RMODE = 100 kΩ VIN = 12 V 700 300 Switching Frequency (kHz) 8 800 VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V RMODE = 200 kΩ IVDDQ = 10 A 700 0 6 Figure 8. Switching Frequency vs Input Voltage 800 200 VVDDQ = 1.20 V VVDDQ = 1.35 V VVDDQ = 1.50 V RMODE = 100 kΩ IVDDQ = 10 A Submit Documentation Feedback 2 4 6 8 10 12 14 VDDQ Output Current (A) 16 18 20 Figure 12. Load Regulation Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) 1.55 0.770 0.765 1.53 VTTREF Voltage (V) VDDQ Output Voltage (V) IVDDQ = 0 A IVDDQ = 20 A RMODE = 200 kΩ 1.54 1.52 1.51 1.50 1.49 1.48 0.760 0.755 0.750 0.745 0.740 1.47 0.735 1.46 1.45 VVDDQ = 1.5 V 6 8 10 12 14 16 Input Voltage (V) 18 20 0.730 −10 22 −5 Figure 13. Line Regulation 0.620 0.690 0.615 VTTREF Voltage (V) VTTREF Voltage (V) 0.685 0.680 0.675 0.670 0.665 0.660 10 0.610 0.605 0.600 0.595 0.590 0.585 VVDDQ = 1.35 V 0.650 −10 −5 VVDDQ = 1.2 V 0 VTTREF Current (mA) 5 0.580 −10 10 Figure 15. VTTREF Load Regulation −5 0 VTTREF Current (mA) 5 10 Figure 16. VTTREF Load Regulation 0.790 0.715 0.780 0.705 0.770 0.695 VTT Voltage (V) VTT Voltage (V) 5 Figure 14. VTTREF Load Regulation 0.695 0.655 0 VTTREF Current (mA) 0.760 0.750 0.740 0.730 0.685 0.675 0.665 0.655 0.720 0.645 VVDDQ = 1.5 V 0.710 −2.0 −1.5 −1.0 −0.5 0.0 0.5 VTT Current (V) 1.0 1.5 2.0 VVDDQ = 1.35 V 0.635 −2.0 −1.5 −1.0 Figure 17. VTT Load Regulation −0.5 0.0 0.5 VTT Current (V) 1.0 1.5 Figure 18. VTT Load Regulation Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 2.0 11 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) 0.640 100 0.630 90 80 70 Efficiency (%) VTT Voltage (V) 0.620 0.610 0.600 0.590 60 50 40 30 0.580 20 0.570 VVDDQ = 1.2 V 0.560 −2.0 −1.5 −1.0 12 10 −0.5 0.0 0.5 VTT Current (V) 1.0 1.5 2.0 VVDDQ = 1.5 V RMODE = 200 kΩ 0 0.001 0.01 0.1 1 VDDQ Output Current (A) VIN = 20 V VIN = 12 V VIN = 8 V 10 Figure 19. VTT Load Regulation Figure 20. Efficiency Figure 21. 1.5-V Load Transient Response Figure 22. VTT Load Transient Response Submit Documentation Feedback 100 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) Figure 23. 1.5-V Startup Waveforms Figure 24. 1.5-V Startup Waveforms (0.5-V Pre-Biased) Figure 25. 1.5-V Soft-Stop Waveforms (Tracking Discharge) Figure 26. 1.5-V Soft-Stop Waveforms (Non-Tracking Discharge) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 13 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com 180 60 135 60 135 40 90 40 90 20 45 20 45 0 0 0 0 −20 −45 −40 −60 Gain Phase IVTT = −1 A −80 10000 −20 −45 −90 −40 −90 −135 −60 −180 10000000 100000 1000000 Frequency (Hz) −80 10000 Figure 27. VTT Bode Plot (Sink) 14 Gain Phase IVTT = 1 A Submit Documentation Feedback 100000 1000000 Frequency (Hz) Phase (°) 80 Gain (dB) 180 Phase (°) Gain (dB) TYPICAL CHARACTERISTICS (continued) 80 −135 −180 10000000 Figure 28. VTT Bode Plot (Source) Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 APPLICATION INFORMATION VDDQ Switch Mode Power Supply Control TPS51216 supports D-CAP™ mode which does not require complex external compensation networks and is suitable for designs with small external components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent series resistance (ESR) on the output capacitors. An adaptive on-time control scheme is used to achieve pseudo-constant frequency. The TPS51216 adjusts the on-time (tON) to be inversely proportional to the input voltage (VIN) and proportional to the output voltage (VDDQ). This makes a switching frequency fairy constant over the variation of input voltage at the steady state condition. VREF and REFIN, VDDQ Output Voltage The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-mA (max) current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of 0.1-mF or larger should be attached close to the VREF terminal. The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for stable operation. Soft-Start and Powergood TPS51216 provides integrated VDDQ soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference voltage ramping up. Figure 29 shows the start-up waveforms. The switching regulator waits for 400ms after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700ms. TPS51216 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The PGOOD comparator is enabled 1.1 ms after VREF is raised high and the start-up delay is 2.5 ms. Note that the time constant which is composed of the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD comparator enabled. S5 VREF VDDQ PGOOD 400 ms 700 ms 1.4 ms UDG-10137 Figure 29. Typical Start-up Waveforms Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 15 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com Power State Control The TPS51216 has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ, VTTREF and VTT are turned on at S0 state (S3=S5=high). In S3 state (S3=low, S5=high), VDDQ and VTTREF voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output floats and does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are turned off and discharged to GND according to the discharge mode selected by MODE pin. Each state code represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 1) Table 1. S3/S5 Power State Control STATE S3 S5 VREF VDDQ VTTREF S0 HI HI ON ON ON VTT ON S3 LO HI ON ON ON OFF(High-Z) S4/S5 LO LO OFF OFF(Discharge) OFF(Discharge) OFF(Discharge) MODE Pin Configuration The TPS51216 reads the MODE pin voltage when the S5 signal is raised high and stores the status in a register. A 15-mA current is sourced from the MODE pin during this time to read the voltage across the resistor connected between the pin and GND. Table 2 shows resistor values, corresponding switching frequency and discharge mode configurations. Table 2. MODE Selection MODE NO. RESISTANCE BETWEEN MODE AND GND ( kΩ) SWITCHING FREQUENCY (kHz) DISCHARGE MODE 3 200 400 Tracking 2 100 300 1 68 300 0 47 400 Non-tracking Discharge Control In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator transistors enabling quick discharge operation. The VTT output maintains tracking of the VTTREF voltage in this mode. (Please refer to Figure 25) After 4 ms of tracking discharge operation, the mode changes to non-tracking discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking mode discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current capability of these MOSFETs. (Please refer to Figure 26) 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 D-CAP™ Mode Figure 30 shows a simplified model of D-CAP™ mode architecture. VIN VDDQSNS DRVH 9 14 Lx PWM + REFIN Control Logic and Driver 8 R1 VREF R2 DRVL 1.8 V VDDQ ESR 6 + High-Side MOSFET 11 Low-Side MOSFET RLOAD COUT UDG-10136 Figure 30. Simplified D-CAP™ Model The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections and provides ease-of-use with a low external component count. However, it requires a sufficient amount of output ripple voltage for stable operation and good jitter performance. The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0 defined in Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin. f 1 £ SW f0 = 2p ´ ESR ´ COUT 3 where • • • ESR is the effective series resistance of the output capacitor COUT is the capacitance of the output capacitor fsw is switching frequency (1) Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage. Figure 31 shows, in the same noise condition, a jitter is improved by making the slope angle larger. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 17 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com VVDDQSNS Slope (1) Jitter (2) Slope (2) Jitter 20 mV (1) VREFIN VREFIN +Noise tON tOFF UDG-10139 Figure 31. Ripple Voltage Slope and Jitter Performance For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as shown in Figure 31 and Equation 2. VOUT ´ ESR ³ 20mV fSW ´ L X where • • VOUT is the VDDQ output voltage LX is the inductance (2) Light-Load Operation In auto-skip mode, the TPS51216 SMPS control logic automatically reduces its switching frequency to improve light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative inductor current by turning off the low-side MOSFET. Equation 3 shows the boundary load condition of this skip mode and continuous conduction operation. ILOAD(LL) = (VIN - VOUT ) ´ VOUT ´ 2 ´ LX VIN 1 fSW (3) VTT and VTTREF TPS51216 integrates two high performance, low-drop-out linear regulators, VTT and VTTREF, to provide complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-mF (or larger) ceramic capacitor must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-mF (or larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable operation. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high-current line to the VTT pin. (Please refer to the Layout Considerations section for details.) 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 VDDQ Overvoltage and Undervoltage Protection TPS51216 sets the overvoltage protection (OVP) when the VDDQSNS voltage reaches a level 20% (typ) higher than the REFIN voltage. When an OV event is detected, the controller latches DRVH low and DRVL high. VTTREF and VTT are turned off and discharged using the non-tracking discharge MOSFETs regardless of the tracking mode. The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the VDDQ, VTT and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup. To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the undervoltage lockout threshold. VDDQ Overcurrent Protection The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the off-state using the low-side MOSFET RDS(on) and the controller maintains the off-state while the voltage across the low-side MOSFET is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and SW pins so that those should be properly connected to the source and drain terminals of low-side MOSFET. The overcurrent trip level, VTRIP, is determined by Equation 4, where RTRIP is the value of the resistor connected between the TRIP pin and GND, and ITRIP is the current sourced from the TRIP pin. ITRIP is 10 mA typically at room temperature, and has 4700ppm/°C temperature coefficient to compensate the temperature dependency of the low-side MOSFET RDS(on). VTRIP = RTRIP ´ ITRIP (4) Because the comparison is done during the off-state, VTRIP sets the valley level of the inductor current. The load current OCL level, IOCL, can be calculated by considering the inductor ripple current as shown in Equation 5 æ V ö IIND(ripple ) æ V ö 1 V -V VOUT OUT TRIP TRIP ÷+ ÷ + ´ IN =ç ´ IOCL = ç ç 8 ´ RDS(on ) ÷ ç 8 ´ RDS(on ) ÷ 2 2 LX fSW ´ VIN è ø è ø where • IIND(ripple) is inductor ripple current (5) In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down. VTT Overcurrent Protection The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation. V5IN Undervoltage Lockout Protection TPS51216 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower than UVLO threshold voltage, typically 3.93 V, VDDQ, VTT and VTTREF are shut off. This is a non-latch protection. Thermal Shutdown TPS51216 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C (typ), VDDQ, VTT and VTTREF are shut off. The thermal shutdown state of VDDQ is open, VTT and VTTREF are high impedance (high-Z) respectively, and the discharge functions are disabled. This is a non-latch protection and the operation is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 19 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com External Components Selection The external components selection is simple in D-CAP™ mode. 1. DETERMINE THE VALUE OF R1 AND R2 The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in Figure 30. R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin and GND. Setting R1 as 10-kΩ is a good starting point. Determine R2 using Equation 6. R1 R2 = æ ö ç ÷ ç ÷ 1.8 ç ÷ -1 æ IIND(ripple ) ´ ESR ö ÷ ç ÷÷ ç VOUT - ç ç ÷÷ 2 ç è øø è (6) 2. CHOOSE THE INDUCTOR The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps stable operation. LX = 1 IIND(ripple ) ´ fSW IN(max ) - VOUT ´ (V VIN(max ) )´ V OUT = 3 IO(max ) ´ fSW IN(max ) - VOUT ´ (V VIN(max ) )´ V OUT (7) The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 8. IIND(peak ) = VIN(max ) - VOUT ´ VOUT VTRIP 1 + ´ 8 ´ RDS(on ) L X ´ fSW VIN(max ) ( ) (8) 3. CHOOSE THE OCL SETTING RESISTANCE, RTRIP Combining Equation 4 and Equation 5, RTRIP can be obtained using Equation 9. RTRIP æ ö æ (V - VOUT ) ö VOUT ÷ ´ RDS(on) ´ 8 ´ ç IOCL - ç IN ÷ ç (2 ´ L X ) ÷ (fSW ´ VIN ) ÷ ç è ø è ø = ITRIP (9) 4. CHOOSE THE OUTPUT CAPACITORS Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 10 and Equation 11. f 1 £ SW 2p ´ ESR ´ COUT 3 (10) VOUT ´ ESR ³ 20mV fSW ´ L X 20 (11) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com SLUSAB9 – NOVEMBER 2010 TPS51216 Application Circuit V5IN 4.5 V to 5.5 V R2 200 kW R1 100 kW R3 36 kW S5 S3 17 16 MODE TRIP S3 S5 1 VTTSNS 2 VLDOIN 3 VTT 4 VTTGND 5 VTTREF DRVH 14 U1 TPS51216RUK R6 0W C7 0.1 mF C5 0.1 mF C8 10 mF C9 10 mF C10 10 mF PGND Q1 FDMS8680 R7 0 W L1 0.56 mH VDDQ 1.5 V/20 A SW 13 VDDQSNS PGND V5IN 12 6 7 8 9 10 VTTREF 0.75 V VIN 8 V to 20 V VBST 15 REFIN PGND 18 GND VTTGND 19 VREF C1 10 mF 20 PGOOD PGND VTT 0.75 V/2 A 21 PwPad AGND C12 10 mF Q2 FDMS8670AS DRVL 11 Q3 FDMS8670AS C6 1 mF C11 330 mF VDDQ_GND R4 10 kW C2 C3 0.22 mF 0.1 mF C4 10 nF R5 49 kW PGND AGND UDG-10165 Figure 32. DDR3, 400-kHz Application Circuit, Tracking Discharge Table 3. DDR3, 400-kHz Application Circuit, List of Materials REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURE PART NUMBER Taiyo Yuden TMK325BJ106MM C8, C9, C10 3 10 µF, 25 V C11 1 330 µF, 2V, 6 mΩ Panasonic EEFSX0D331XE L1 1 0.56 µH, 21 A, 1.56 mΩ Panasonic ETQP4LR56WFC Q1 1 30 V, 35 A, 8.5 mΩ Fairchild FDMS8680 Q2, Q3 2 30 V, 42 A, 3.5 mΩ Fairchild FDMS8670AS For this example, the bulk output capacitor ESR requirement for D-CAP™ mode is described in Equation 12, whichever is greater. 20mV ´ fSW ´ L 3 ESR ³ or ESR ³ VOUT 2p ´ fSW ´ COUT (12) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 21 TPS51216 SLUSAB9 – NOVEMBER 2010 www.ti.com Layout Considerations Certain issues must be considered before designing a layout using the TPS51216. 2 VLDOIN VTT VTT TPS51216 VIN 3 10 mF VTTGND VTTGND 4 V5IN VTTREF VOUT 1 mF #2 5 DRVL MODE 0.22 mF #1 12 11 19 #3 PGND TRIP 18 10 VREF 6 REFIN 8 GND 7 0.1 mF 10 nF UDG-10166 Figure 33. DC/DC Converter Ground System • • • • 22 VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components should be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines. All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components. The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to suppress generating switching noise. – The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the VIN capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 of Figure 33) – The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of Figure 33) – The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and PGND at ground as close as possible. (Refer to loop #3 of Figure 33) Because the TPS51216 controls output voltage referring to voltage across VOUT capacitor, VDDQSNS should be connected to the positive node of VOUT capacitor. In a same manner GND should be connected to the negative node of VOUT capacitor. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 TPS51216 www.ti.com • • • • • • • • • • • • SLUSAB9 – NOVEMBER 2010 Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling to a high-voltage switching node. Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground should avoid coupling to a high-voltage switching node Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace. The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible. VLDOIN should be connected to VDDQ output with short and wide traces. An input bypass capacitor should be placed as close as possible to the pin with short and wide connections. The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to avoid additional ESR and/or ESL of the trace. VTTSNS should be connected to the positive node of the VTT output capacitor(s) as a separate trace from the high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage at the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s). Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitor(s) is larger than 2 mΩ. VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines. The negative node of the VTT output capacitor(s) and the VTTREF capacitor should be tied together by avoiding common impedance to high-current path of the VTT source/sink current. GND pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND should be connected together at a single point. In order to effectively remove heat from the package, prepare the thermal land and solder to the package thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solderside ground plane(s) should be used to help dissipation. CAUTION Do NOT connect PGND pin directly to this thermal land underneath the package. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS51216 23 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS51216RUKR ACTIVE QFN RUK 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples TPS51216RUKT ACTIVE QFN RUK 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51216RUKR QFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51216RUKT QFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Dec-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51216RUKR QFN RUK 20 3000 346.0 346.0 29.0 TPS51216RUKT QFN RUK 20 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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